void BSP_PreInit (void)
{
BSP_CPU_Init(); /* Initialize CPU Clks & PLLs */
CPU_IntDis(); /* Disable CPU interrupts. */
NVICInit(); /* Initialize hardware interrupt controller*/
CSP_IntInit(); /* Initialize software interrupt controller module. */
}
void BSP_Init (void)
{
CPU_IntDis(); /* Disable all interrupts. */
Xil_ICacheEnable(); /* Enable the instruction cache. */
Xil_DCacheEnable(); /* Enable the Data cache. */
CSP_IntInit(); /* Initialize Interrupt controller module. */
#ifdef STDOUT_IS_PS7_UART
XUartPs Uart_Ps_0; /* Use the PS UART for Zynq devices. */
XUartPs_Config *Config_0;
Config_0 = XUartPs_LookupConfig(UART_DEVICE_ID);
XUartPs_CfgInitialize(&Uart_Ps_0, Config_0, Config_0->BaseAddress);
XUartPs_SetBaudRate(&Uart_Ps_0, 115200);
#elif defined(STDOUT_IS_16550)
XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
#endif
}
void BSP_Init (void)
{
CPU_INT16U reg_to;
CPU_INT32U reg_val;
CPU_SR_ALLOC();
/* ---------------- CLOCK INITIALIZATION -------------- */
BSP_REG_FLASHCFG = BSP_MSK_FLASHCFG_CLK_6 /* Set 6 cycles to acces the Flash memory. */
| BSP_MSK_FLASHCFG_RST_VAL;
/* ----------- MAIN OSCILLATOR INITIALIZATION --------- */
DEF_BIT_CLR(BSP_REG_SCS, BSP_BIT_SCS_OSCRANGE); /* Set the main oscillator range */
reg_to = BSP_VAL_MAX_TO;
DEF_BIT_SET(BSP_REG_SCS, BSP_BIT_SCS_OSCEN); /* Enable the Main Oscillator */
/* Wait until the main oscillator is enabled. */
while (DEF_BIT_IS_CLR(BSP_REG_SCS, BSP_BIT_SCS_OSCSTAT) &&
(reg_to > 0u)) {
reg_to--;
}
if (reg_to == 0u) { /* Configuration fail */
return;
}
BSP_REG_PCLKSEL0 = DEF_BIT_NONE; /* All peripheral clock runrs at CPU_Clk / 4 = 25 Mhz */
BSP_REG_PCLKSEL1 = DEF_BIT_NONE;
/* ------------------ PLL0 CONFIGURATION -------------- */
reg_val = (((25u - 1u) << 0u) & BSP_MSK_PLLCFG0_MSEL) /* PLL0 values M = 25 & N = 2 (see note #6) */
| ((( 2u - 1u) << 16u) & BSP_MSK_PLLCFG0_NSEL);
/* 1. Disconnect PLL0 with one feed sequence if PLL ... */
/* ... already connected. */
if (DEF_BIT_IS_SET(BSP_REG_PLLSTAT(0u), BSP_BIT_PLLSTAT_PLLC0_STAT)) {
DEF_BIT_CLR(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLC);
BSP_PLL_FEED_SEQ(0u);
}
DEF_BIT_CLR(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLE); /* 2. Disable PLL0 with one feed sequence */
BSP_PLL_FEED_SEQ(0u);
BSP_REG_CCLKCFG = (1u - 1u); /* 3. Change the CPU clock divider setting to speed ... */
/* ... operation without PLL0 */
BSP_REG_CLKSRCSEL = BSP_BIT_CLKSRCSEL_MAIN; /* 4. Select the main osc. as the PLL0 clock source */
BSP_REG_PLLCFG(0u) = reg_val; /* 5. Write to the PLLCFG and make it effective with... */
BSP_PLL_FEED_SEQ(0u) /* ... one one feed sequence */
DEF_BIT_SET(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLE); /* 6. Enable PLL0 with one feed sequence */
BSP_PLL_FEED_SEQ(0u);
BSP_REG_CCLKCFG = (3u - 1u); /* 7. Change the CPU clock divider setting for ... */
/* ... operation with PLL0 */
reg_to = BSP_VAL_MAX_TO; /* 8. Wait for PLL0 to achieve lock by monitoring ... */
/* ... the PLOCK0 bit in the PLL0STAT */
while (DEF_BIT_IS_CLR(BSP_REG_PLLSTAT(0u), BSP_BIT_PLLSTAT_PLOCK0) &&
(reg_to > 0u)) {
reg_to--;
}
if (reg_to == 0u) {
return;
}
DEF_BIT_SET(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLC); /* 9. Connect PLL0 with one feed sequence */
BSP_PLL_FEED_SEQ(0u);
/* ------------------ PLL1 CONFIGURATION -------------- */
reg_val = (((4u - 1u) << 0u) & BSP_MSK_PLLCFG1_MSEL) /* PLL1 values M = 4; P = 2 coded as '01' (see note #6) */
| (((0x01u ) << 5u) & BSP_MSK_PLLCFG1_NSEL);
DEF_BIT_CLR(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLC); /* 1. Disconnect PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
DEF_BIT_CLR(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLE); /* 2. Disable PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
BSP_REG_PLLCFG(1u) = reg_val; /* 3. Write to the PLLCFG and make it effective with... */
BSP_PLL_FEED_SEQ(1u); /* ... one one feed sequence */
DEF_BIT_SET(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLE); /* 4. Enable PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
reg_to = BSP_VAL_MAX_TO; /* 5. Wait for PLL1 to achieve lock by monitoring ... */
/* ... the PLOCK1 bit in the PLL1STAT */
while (DEF_BIT_IS_CLR(BSP_REG_PLLSTAT(1u), BSP_BIT_PLLSTAT_PLOCK1) &&
(reg_to > 0u)) {
reg_to--;
}
if (reg_to == 0u) {
return;
}
DEF_BIT_SET(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLC); /* 6. Connect PLL1 with one feed sequence */
BSP_PLL_FEED_SEQ(1u);
BSP_REG_FLASHCFG = BSP_MSK_FLASHCFG_CLK_5 /* Set 5 cycles to acces the Flash memory. */
| BSP_MSK_FLASHCFG_RST_VAL;
CSP_GPIO_Cfg(CSP_GPIO_PORT_NBR_00,
BSP_GPIO0_LED2,
CSP_GPIO_DIR_OUT,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
CSP_GPIO_Cfg(CSP_GPIO_PORT_NBR_01,
BSP_GPIO1_LED1,
CSP_GPIO_DIR_OUT,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
CSP_GPIO_Cfg(CSP_GPIO_PORT_NBR_00,
BSP_GPIO0_BUT1,
CSP_GPIO_DIR_IN,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
CSP_GPIO_Cfg(CSP_GPIO_PORT_NBR_02,
BSP_GPIO2_BUT2,
CSP_GPIO_DIR_IN,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
BSP_LED_Off(0);
CSP_GPIO_Cfg( CSP_GPIO_PORT_NBR_02,
(BSP_GPIO2_JOY_RIGHT |
BSP_GPIO2_JOY_DOWN |
BSP_GPIO2_JOY_LEFT |
BSP_GPIO2_JOY_RIGHT),
CSP_GPIO_DIR_IN,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
CSP_GPIO_Cfg( CSP_GPIO_PORT_NBR_00,
BSP_GPIO0_JOY_CENTER,
CSP_GPIO_DIR_IN,
CSP_GPIO_FLAG_MODE_NONE,
DEF_NO,
0u,
CSP_GPIO_FNCT_00);
CSP_IntInit();
CSP_IntDisAll(CSP_INT_CTRL_NBR_MAIN);
}
