static void bfe_core_reset( struct bfe_softc * sc ) { u_int32_t val; /* Disable the core */ bfe_core_disable(sc); /* and bring it back up */ CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); CSR_READ_4(sc, BFE_SBTMSLOW); DELAY(10); /* Chip bug, clear SERR, IB and TO if they are set. */ if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); val = CSR_READ_4(sc, BFE_SBIMSTATE); if (val & (BFE_IBE | BFE_TO)) CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); /* Clear reset and allow it to move through the core */ CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); CSR_READ_4(sc, BFE_SBTMSLOW); DELAY(10); /* Leave the clock set */ CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); CSR_READ_4(sc, BFE_SBTMSLOW); DELAY(10); }
/* Set a specific pin's in/out state. */ static int aml8726_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) { struct aml8726_gpio_softc *sc = device_get_softc(dev); uint32_t mask = 1U << pin; if (pin >= sc->npins) return (EINVAL); AML_GPIO_LOCK(sc); if ((flags & GPIO_PIN_OUTPUT) != 0) { /* Output. Turn on driver. */ CSR_WRITE_4(sc, AML_GPIO_OE_N_REG, (CSR_READ_4(sc, AML_GPIO_OE_N_REG) & ~mask)); } else { /* Input. Turn off driver. */ CSR_WRITE_4(sc, AML_GPIO_OE_N_REG, (CSR_READ_4(sc, AML_GPIO_OE_N_REG) | mask)); } AML_GPIO_UNLOCK(sc); return (0); }
static int kr_miibus_writereg(device_t dev, int phy, int reg, int data) { struct kr_softc * sc = device_get_softc(dev); int i; i = KR_MII_TIMEOUT; while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i) i--; if (i == 0) device_printf(dev, "phy mii is busy %d:%d\n", phy, reg); CSR_WRITE_4(sc, KR_MIIMADDR, (phy << 8) | reg); i = KR_MII_TIMEOUT; while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i) i--; if (i == 0) device_printf(dev, "phy mii is busy %d:%d\n", phy, reg); CSR_WRITE_4(sc, KR_MIIMWTD, data); i = KR_MII_TIMEOUT; while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i) i--; if (i == 0) device_printf(dev, "phy mii is busy %d:%d\n", phy, reg); return (0); }
void * kse_init(unsigned tag, void *data) { struct local *l; struct desc *txd, *rxd; unsigned i, val, fdx; uint8_t *en; l = ALLOC(struct local, sizeof(struct desc)); /* desc alignment */ memset(l, 0, sizeof(struct local)); l->csr = DEVTOV(pcicfgread(tag, 0x10)); en = data; i = CSR_READ_2(l, MARL); en[0] = i; en[1] = i >> 8; i = CSR_READ_2(l, MARM); en[2] = i; en[3] = i >> 8; i = CSR_READ_2(l, MARH); en[4] = i; en[5] = i >> 8; printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", en[0], en[1], en[2], en[3], en[4], en[5]); CSR_WRITE_2(l, CIDR, 1); mii_dealan(l, 5); val = pcicfgread(tag, PCI_ID_REG); if (PCI_PRODUCT(val) == 0x8841) { val = CSR_READ_4(l, P1SR); fdx = !!(val & (1U << 9)); printf("%s", (val & (1U << 8)) ? "100Mbps" : "10Mbps"); if (fdx) printf("-FDX"); printf("\n"); } txd = &l->txd; rxd = &l->rxd[0]; rxd[0].xd0 = htole32(R0_OWN); rxd[0].xd1 = htole32(FRAMESIZE); rxd[0].xd2 = htole32(VTOPHYS(l->rxstore[0])); rxd[0].xd3 = htole32(VTOPHYS(&rxd[1])); rxd[1].xd0 = htole32(R0_OWN); rxd[1].xd1 = htole32(R1_RER | FRAMESIZE); rxd[1].xd2 = htole32(VTOPHYS(l->rxstore[1])); rxd[1].xd3 = htole32(VTOPHYS(&rxd[0])); l->rx = 0; CSR_WRITE_4(l, TDLB, VTOPHYS(txd)); CSR_WRITE_4(l, RDLB, VTOPHYS(rxd)); CSR_WRITE_4(l, MDTXC, 07); /* stretch short, add CRC, Tx enable */ CSR_WRITE_4(l, MDRXC, 01); /* Rx enable */ CSR_WRITE_4(l, MDRSC, 01); /* start receiving */ return l; }
static void pcn_bcr_write(pcn_t *pcnp, uint32_t reg, uint32_t val) { mutex_enter(&pcnp->pcn_reglock); CSR_WRITE_4(pcnp, PCN_IO32_RAP, reg); CSR_WRITE_4(pcnp, PCN_IO32_BDP, val); mutex_exit(&pcnp->pcn_reglock); }
static __inline void _bs_w(void *v, bus_space_handle_t ioh, bus_size_t off, u_int32_t be, u_int32_t data) { CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE); CSR_WRITE_4(PCI_NP_WDATA, data); if (CSR_READ_4(PCI_ISR) & ISR_PFE) CSR_WRITE_4(PCI_ISR, ISR_PFE); }
void pxa2x0_i2c_reset(struct pxa2x0_i2c_softc *sc) { CSR_WRITE_4(sc, I2C_ICR, ICR_UR); CSR_WRITE_4(sc, I2C_ISAR, 0); CSR_WRITE_4(sc, I2C_ISR, ISR_ALL); while (CSR_READ_4(sc, I2C_ICR) & ~ICR_UR) continue; CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr); }
void dcphy_attach(struct device *parent, struct device *self, void *aux) { struct mii_softc *sc = (struct mii_softc *)self; struct mii_attach_args *ma = aux; struct mii_data *mii = ma->mii_data; struct dc_softc *dc_sc; printf(": internal PHY\n"); sc->mii_inst = mii->mii_instance; sc->mii_phy = ma->mii_phyno; sc->mii_funcs = &dcphy_funcs; sc->mii_pdata = mii; sc->mii_flags = ma->mii_flags; sc->mii_anegticks = 50; sc->mii_flags |= MIIF_NOISOLATE; dc_sc = mii->mii_ifp->if_softc; CSR_WRITE_4(dc_sc, DC_10BTSTAT, 0); CSR_WRITE_4(dc_sc, DC_10BTCTRL, 0); #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) switch(dc_sc->dc_csid) { case COMPAQ_PRESARIO_ID: /* Example of how to only allow 10Mbps modes. */ sc->mii_capabilities = BMSR_ANEG|BMSR_10TFDX|BMSR_10THDX; break; default: if (dc_sc->dc_pmode == DC_PMODE_SIA) { sc->mii_capabilities = BMSR_ANEG|BMSR_10TFDX|BMSR_10THDX; } else { ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), BMCR_LOOP|BMCR_S100); sc->mii_capabilities = BMSR_ANEG|BMSR_100TXFDX|BMSR_100TXHDX| BMSR_10TFDX|BMSR_10THDX; } break; } if (dc_sc->dc_type == DC_TYPE_21145) sc->mii_capabilities = BMSR_10THDX; sc->mii_capabilities &= ma->mii_capmask; if (sc->mii_capabilities & BMSR_MEDIAMASK) mii_phy_add_media(sc); #undef ADD }
/* special I/O functions */ static __inline u_int32_t _bs_r(void *v, bus_space_handle_t ioh, bus_size_t off, u_int32_t be) { u_int32_t data; CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ); data = CSR_READ_4(PCI_NP_RDATA); if (CSR_READ_4(PCI_ISR) & ISR_PFE) CSR_WRITE_4(PCI_ISR, ISR_PFE); return data; }
static int jz4780_hardclock(void *arg) { struct jz4780_timer_softc *sc = (struct jz4780_timer_softc *)arg; CSR_WRITE_4(sc, JZ_TC_TFCR, TFR_FFLAG5); CSR_WRITE_4(sc, JZ_TC_TECR, TESR_TCST5); if (sc->et.et_active) sc->et.et_event_cb(&sc->et, sc->et.et_arg); return (FILTER_HANDLED); }
void _pci_io_bs_w_4(void *v, bus_space_handle_t ioh, bus_size_t off, uint32_t val) { int s; PCI_CONF_LOCK(s); CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_WRITE); CSR_WRITE_4(PCI_NP_WDATA, val); if (CSR_READ_4(PCI_ISR) & ISR_PFE) CSR_WRITE_4(PCI_ISR, ISR_PFE); PCI_CONF_UNLOCK(s); }
int pxa2x0_i2c_write_byte(struct pxa2x0_i2c_softc *sc, uint8_t byte, int flags) { int send_stop = flags & I2C_F_STOP; int error; CSR_WRITE_4(sc, I2C_IDBR, byte); CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr | ICR_TB | (send_stop ? ICR_STOP : 0)); error = pxa2x0_i2c_wait(sc, ISR_ITE | ISR_ALD, flags); if (error) { DPRINTF(("%s: write byte failed\n", device_xname(sc->sc_dev))); return error; } return 0; }
static int aml8726_usb_phy_detach(device_t dev) { struct aml8726_usb_phy_softc *sc = device_get_softc(dev); uint32_t i; uint32_t value; /* * Disable by issuing a power on reset. */ value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG); value |= (AML_USB_PHY_CFG_A_POR | AML_USB_PHY_CFG_B_POR); CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); /* Turn off power */ i = sc->npwr_en; while (i-- != 0) { (void)GPIO_PIN_SET(sc->pwr_en[i].dev, sc->pwr_en[i].pin, PIN_OFF_FLAG(sc->pwr_en[i].pol)); } free (sc->pwr_en, M_DEVBUF); sc->pwr_en = NULL; bus_release_resources(dev, aml8726_usb_phy_spec, sc->res); return (0); }
void __haiku_reenable_interrupts(device_t dev) { struct vge_softc *sc = device_get_softc(dev); CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); }
int pxa2x0_i2c_wait(struct pxa2x0_i2c_softc *sc, int bit, int flags) { uint32_t isr; int error; int i; for (i = I2C_TIMEOUT; i >= 0; --i) { isr = CSR_READ_4(sc, I2C_ISR); if (isr & (bit | ISR_BED)) break; delay(1); } if (isr & (ISR_BED | (bit & ISR_ALD))) error = EIO; else if (isr & (bit & ~ISR_ALD)) error = 0; else error = ETIMEDOUT; CSR_WRITE_4(sc, I2C_ISR, isr); return error; }
/* Toggle a pin's output value. */ static int aml8726_gpio_pin_toggle(device_t dev, uint32_t pin) { struct aml8726_gpio_softc *sc = device_get_softc(dev); uint32_t mask; if (pin >= sc->npins) return (EINVAL); /* * The GPIOAO OUT bits occupy the upper word of the OEN register. */ if (rman_get_start(sc->res[1]) == rman_get_start(sc->res[0])) pin += 16; mask = 1U << pin; AML_GPIO_LOCK(sc); CSR_WRITE_4(sc, AML_GPIO_OUT_REG, CSR_READ_4(sc, AML_GPIO_OUT_REG) ^ mask); AML_GPIO_UNLOCK(sc); return (0); }
int EtherSend(char *pkt, int len) { volatile struct ex_dpd *dpd; int i; dpd = SNDBUF_VIRT; dpd->dpd_nextptr = 0; dpd->dpd_fsh = len; #ifdef _STANDALONE dpd->dpd_frags[0].fr_addr = vtophys(pkt); #else memcpy(SNDBUF_VIRT + 100, pkt, len); dpd->dpd_frags[0].fr_addr = SNDBUF_PHYS + 100; #endif dpd->dpd_frags[0].fr_len = len | EX_FR_LAST; CSR_WRITE_4(ELINK_DNLISTPTR, SNDBUF_PHYS); CSR_WRITE_2(ELINK_COMMAND, ELINK_DNUNSTALL); i = 10000; while (!(dpd->dpd_fsh & 0x00010000)) { if (--i < 0) { printf("3c90xb: send timeout\n"); return -1; } delay(1); } return len; }
uint32_t _pci_io_bs_r_4(void *v, bus_space_handle_t ioh, bus_size_t off) { uint32_t data; int s; PCI_CONF_LOCK(s); CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_READ); data = CSR_READ_4(PCI_NP_RDATA); if (CSR_READ_4(PCI_ISR) & ISR_PFE) CSR_WRITE_4(PCI_ISR, ISR_PFE); PCI_CONF_UNLOCK(s); return data; }
__private_extern__ void bfe_chip_halt( struct bfe_softc * sc ) { BFE_LOCK(sc); /* disable interrupts - not that it actually does..*/ CSR_WRITE_4(sc, BFE_IMASK, 0); CSR_READ_4(sc, BFE_IMASK); CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); DELAY(10); BFE_UNLOCK(sc); }
static int jz4780_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) { struct jz4780_timer_softc *sc = (struct jz4780_timer_softc *)et->et_priv; uint32_t ticks; ticks = (first * et->et_frequency) / SBT_1S; if (ticks == 0) return (EINVAL); CSR_WRITE_4(sc, JZ_TC_TDFR(5), ticks); CSR_WRITE_4(sc, JZ_TC_TCNT(5), 0); CSR_WRITE_4(sc, JZ_TC_TESR, TESR_TCST5); return (0); }
int pxa2x0_i2c_send_stop(struct pxa2x0_i2c_softc *sc, int flags) { CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr | ICR_STOP); delay(I2C_TIMEOUT); return 0; }
__private_extern__ int bfe_writephy( struct bfe_softc * sc, u_int32_t reg, u_int32_t val ) { int status; BFE_LOCK(sc); CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | (reg << BFE_MDIO_RA_SHIFT) | (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | (val & BFE_MDIO_DATA_DATA))); status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); BFE_UNLOCK(sc); return status; }
static int jz4780_timer_stop(struct eventtimer *et) { struct jz4780_timer_softc *sc = (struct jz4780_timer_softc *)et->et_priv; CSR_WRITE_4(sc, JZ_TC_TECR, TESR_TCST5); return (0); }
__private_extern__ void bfe_cam_write( struct bfe_softc * sc, u_char * data, int index ) { u_int32_t val; val = ((u_int32_t) data[2]) << 24; val |= ((u_int32_t) data[3]) << 16; val |= ((u_int32_t) data[4]) << 8; val |= ((u_int32_t) data[5]); CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); val = (BFE_CAM_HI_VALID | (((u_int32_t) data[0]) << 8) | (((u_int32_t) data[1]))); CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | (index << BFE_CAM_INDEX_SHIFT))); bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); }
static int satapresense(struct dkdev_ata *l, int n) { #define VND_CH(n) (((n&02)<<8)+((n&01)<<7)) #define VND_SC(n) (0x100+VND_CH(n)) #define VND_SS(n) (0x104+VND_CH(n)) uint32_t sc = l->bar[5] + VND_SC(n); uint32_t ss = l->bar[5] + VND_SS(n); unsigned val; val = (00 << 4) | (03 << 8); /* any speed, no pwrmgt */ CSR_WRITE_4(sc, val | 01); /* perform init */ delay(50 * 1000); CSR_WRITE_4(sc, val); delay(50 * 1000); val = CSR_READ_4(ss); /* has completed */ return ((val & 03) == 03); /* active drive found */ }
__private_extern__ int bfe_readphy( struct bfe_softc * sc, u_int32_t reg, u_int32_t * val ) { int err; BFE_LOCK(sc); /* Clear MII ISR */ CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | (reg << BFE_MDIO_RA_SHIFT) | (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; BFE_UNLOCK(sc); return err; }
static void bfe_pci_setup( struct bfe_softc * sc, u_int32_t cores ) { u_int32_t bar_orig, pci_rev, val; bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; val = CSR_READ_4(sc, BFE_SBINTVEC); val |= cores; CSR_WRITE_4(sc, BFE_SBINTVEC, val); val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); }
uint16_t _pci_io_bs_r_2(void *v, bus_space_handle_t ioh, bus_size_t off) { uint32_t data, n, be; int s; n = (ioh + off) % 4; be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; PCI_CONF_LOCK(s); CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ); data = CSR_READ_4(PCI_NP_RDATA); if (CSR_READ_4(PCI_ISR) & ISR_PFE) CSR_WRITE_4(PCI_ISR, ISR_PFE); PCI_CONF_UNLOCK(s); return data >> (8 * n); }
void _pci_io_bs_w_2(void *v, bus_space_handle_t ioh, bus_size_t off, uint16_t val) { uint32_t data, n, be; int s; n = (ioh + off) % 4; be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; data = val << (8 * n); PCI_CONF_LOCK(s); CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE); CSR_WRITE_4(PCI_NP_WDATA, data); if (CSR_READ_4(PCI_ISR) & ISR_PFE) CSR_WRITE_4(PCI_ISR, ISR_PFE); PCI_CONF_UNLOCK(s); }
static int dcphy_attach(device_t dev) { struct mii_softc *sc; struct dc_softc *dc_sc; device_t brdev; sc = device_get_softc(dev); mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE, &dcphy_funcs, 0); /*PHY_RESET(sc);*/ dc_sc = sc->mii_pdata->mii_ifp->if_softc; CSR_WRITE_4(dc_sc, DC_10BTSTAT, 0); CSR_WRITE_4(dc_sc, DC_10BTCTRL, 0); brdev = device_get_parent(sc->mii_dev); switch (pci_get_subdevice(brdev) << 16 | pci_get_subvendor(brdev)) { case COMPAQ_PRESARIO_ID: /* Example of how to only allow 10Mbps modes. */ sc->mii_capabilities = BMSR_ANEG | BMSR_10TFDX | BMSR_10THDX; break; default: if (dc_sc->dc_pmode == DC_PMODE_SIA) sc->mii_capabilities = BMSR_ANEG | BMSR_10TFDX | BMSR_10THDX; else sc->mii_capabilities = BMSR_ANEG | BMSR_100TXFDX | BMSR_100TXHDX | BMSR_10TFDX | BMSR_10THDX; break; } sc->mii_capabilities &= sc->mii_capmask; device_printf(dev, " "); mii_phy_add_media(sc); printf("\n"); MIIBUS_MEDIAINIT(sc->mii_dev); return (0); }