static void coresight_cti_restore(void)
{
	struct cti_info *p_cti_info;
	p_cti_info = &per_cpu(cpu_cti_info, smp_processor_id());

	cti_enable_access();
	writel_relaxed(p_cti_info->cti_en_in1, CTI_REG(CTI_EN_IN1_OFFSET));
	writel_relaxed(p_cti_info->cti_en_out6, CTI_REG(CTI_EN_OUT6_OFFSET));
	writel_relaxed(p_cti_info->cti_ctrl, CTI_REG(CTI_CTRL_OFFSET));
}
static void coresight_cti_save(void)
{
	struct cti_info *p_cti_info;
	p_cti_info = &per_cpu(cpu_cti_info, smp_processor_id());

	cti_enable_access();
	p_cti_info->cti_ctrl = readl_relaxed(CTI_REG(CTI_CTRL_OFFSET));
	p_cti_info->cti_en_in1 = readl_relaxed(CTI_REG(CTI_EN_IN1_OFFSET));
	p_cti_info->cti_en_out6 = readl_relaxed(CTI_REG(CTI_EN_OUT6_OFFSET));
}
static void coresight_cti_save(void)
{
	struct cti_info *p_cti_info;
	p_cti_info = &per_cpu(cpu_cti_info, smp_processor_id());

	cti_enable_access();
	p_cti_info->cti_ctrl = readl_relaxed(CTI_REG(0x0));
	p_cti_info->cti_en_in1 = readl_relaxed(CTI_REG(0x24));
	p_cti_info->cti_en_out6 = readl_relaxed(CTI_REG(0xb8));
}
static void coresight_cti_restore(void)
{
	struct cti_info *p_cti_info;
	p_cti_info = &per_cpu(cpu_cti_info, smp_processor_id());

	cti_enable_access();
	writel_relaxed(p_cti_info->cti_ctrl, CTI_REG(0x0));
	writel_relaxed(p_cti_info->cti_en_in1, CTI_REG(0x24));
	writel_relaxed(p_cti_info->cti_en_out6, CTI_REG(0xB8));

	dsb();
	isb();
}
void mmp_pmu_ack(void)
{
	writel_relaxed(0x40, CTI_REG(CTI_INTACK_OFFSET));
}
static inline void cti_enable_access(void)
{
	writel_relaxed(0xC5ACCE55, CTI_REG(CTI_LOCK_OFFSET));
}