void
cyg_spi_at91_bus_init(void)
{
// Create and attach SPI interrupt object
cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_SPI,
4,
(cyg_addrword_t)&cyg_spi_at91_bus,
spi_at91_ISR,
spi_at91_DSR,
&cyg_spi_at91_bus.spi_interrupt_handle,
&cyg_spi_at91_bus.spi_interrupt);
cyg_drv_interrupt_attach(cyg_spi_at91_bus.spi_interrupt_handle);
// Init transfer mutex and condition
cyg_drv_mutex_init(&cyg_spi_at91_bus.transfer_mx);
cyg_drv_cond_init(&cyg_spi_at91_bus.transfer_cond,
&cyg_spi_at91_bus.transfer_mx);
// Init flags
cyg_spi_at91_bus.transfer_end = true;
cyg_spi_at91_bus.cs_up = false;
// Soft reset the SPI controller
HAL_WRITE_UINT32(AT91_SPI+AT91_SPI_CR, AT91_SPI_CR_SWRST);
// Configure SPI pins
// NOTE: here we let the SPI controller control
// the data in, out and clock signals, but
// we need to handle the chip selects manually
// in order to achieve better chip select control
// inbetween transactions.
// Put SPI MISO, MOIS and SPCK pins into peripheral mode
HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_PDR, AT91_PIO_PSR_SPCK |
AT91_PIO_PSR_MISO |
AT91_PIO_PSR_MOIS);
// Put SPI chip select pins in IO output mode
HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_SODR, AT91_SPI_PIO_NPCS(0x0F));
HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_PER, AT91_SPI_PIO_NPCS(0x0F));
HAL_WRITE_UINT32(AT91_SPI_PIO+AT91_PIO_OER, AT91_SPI_PIO_NPCS(0x0F));
// Call upper layer bus init
CYG_SPI_BUS_COMMON_INIT(&cyg_spi_at91_bus.spi_bus);
}
static void spi_at91_init_bus(cyg_spi_at91_bus_t * spi_bus)
{
cyg_uint32 ctr;
// Create and attach SPI interrupt object
cyg_drv_interrupt_create(spi_bus->interrupt_number,
4,
(cyg_addrword_t)spi_bus,
spi_at91_ISR,
spi_at91_DSR,
&spi_bus->spi_interrupt_handle,
&spi_bus->spi_interrupt);
cyg_drv_interrupt_attach(spi_bus->spi_interrupt_handle);
// Init transfer mutex and condition
cyg_drv_mutex_init(&spi_bus->transfer_mx);
cyg_drv_cond_init(&spi_bus->transfer_cond,
&spi_bus->transfer_mx);
// Init flags
spi_bus->transfer_end = true;
spi_bus->cs_up = false;
// Soft reset the SPI controller
HAL_WRITE_UINT32(spi_bus->base+AT91_SPI_CR, AT91_SPI_CR_SWRST);
// Configure SPI pins
// Put SPI chip select pins in IO output mode
for(ctr = 0;ctr<4;ctr++)
{
if(spi_bus->cs_en[ctr])
{
HAL_ARM_AT91_GPIO_CFG_DIRECTION(spi_bus->cs_gpio[ctr],AT91_PIN_OUT);
HAL_ARM_AT91_GPIO_SET(spi_bus->cs_gpio[ctr]);
}
}
// Call upper layer bus init
CYG_SPI_BUS_COMMON_INIT(&spi_bus->spi_bus);
}
/**
*
* QSPI bus initialization function
*
* @param qspi_bus - Driver handle
*
* @return none
*
*****************************************************************************/
static void qspi_xc7z_init_bus(cyg_qspi_xc7z_bus_t * qspi_bus)
{
entry_debug();
volatile cyg_uint32 reg;
// Create and attach SPI interrupt object
cyg_drv_interrupt_create(qspi_bus->interrupt_number,
4,
(cyg_addrword_t)qspi_bus,
qspi_xc7z_ISR,
qspi_xc7z_DSR,
&qspi_bus->qspi_interrupt_handle,
&qspi_bus->qspi_interrupt);
cyg_drv_interrupt_attach(qspi_bus->qspi_interrupt_handle);
cyg_drv_interrupt_mask(qspi_bus->interrupt_number);
// Init transfer mutex and condition
cyg_drv_mutex_init(&qspi_bus->transfer_mx);
cyg_drv_cond_init(&qspi_bus->transfer_cond,
&qspi_bus->transfer_mx);
// Init flags
qspi_bus->transfer_end = true;
qspi_bus->cs_up = false;
// Unlock SLCR regs
HAL_WRITE_UINT32(XC7Z_SYS_CTRL_BASEADDR + XSLCR_UNLOCK_OFFSET, XSLCR_UNLOCK_KEY);
// Enable clock to QSPI module
HAL_READ_UINT32( XC7Z_SYS_CTRL_BASEADDR + XSLCRAPER_CLK_CTRL_OFFSET, reg);
reg |= XSLCRAPER_CLK_CTRL_QSPI_EN;
HAL_WRITE_UINT32(XC7Z_SYS_CTRL_BASEADDR + XSLCRAPER_CLK_CTRL_OFFSET, reg);
// Lock SLCR regs
HAL_WRITE_UINT32(XC7Z_SYS_CTRL_BASEADDR + XSLCR_LOCK_OFFSET, XSLCR_LOCK_KEY);
// Soft reset the SPI controller
HAL_WRITE_UINT32(qspi_bus->base + XQSPIPS_ER_OFFSET, 0x00);
//TODO changed, originally was just setting a value without reading
HAL_READ_UINT32(qspi_bus->base + XQSPIPS_CR_OFFSET, reg);
reg &= (1 << 17); // preserve the reserved bit which is described as "do not modify"
reg |= (1 << 31);
HAL_WRITE_UINT32(qspi_bus->base + XQSPIPS_CR_OFFSET, reg);
// Disable linear mode
HAL_WRITE_UINT32(qspi_bus->base + XQSPIPS_LQSPI_CR_OFFSET, 0x00);
// Clear status
HAL_WRITE_UINT32(qspi_bus->base + XQSPIPS_SR_OFFSET, 0x7F);
// Clear the RX FIFO
HAL_READ_UINT32(qspi_bus->base + XQSPIPS_SR_OFFSET, reg);
while (reg & XQSPIPS_IXR_RXNEMPTY_MASK)
{
HAL_READ_UINT32(qspi_bus->base + XQSPIPS_RXD_OFFSET, reg);
HAL_READ_UINT32(qspi_bus->base + XQSPIPS_SR_OFFSET, reg);
}
HAL_READ_UINT32(qspi_bus->base + XQSPIPS_CR_OFFSET, reg);
reg &= 0xFBFFFFFF; /* Set little endian mode of TX FIFO */
reg |= (XQSPIPS_CR_IFMODE_MASK | XQSPIPS_CR_MANSTRTEN_MASK | XQSPIPS_CR_SSFORCE_MASK |
XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_DATA_SZ_MASK | XQSPIPS_CR_MSTREN_MASK);
HAL_WRITE_UINT32(qspi_bus->base + XQSPIPS_CR_OFFSET, reg);
// Configure SPI pins
// All pins was configured in HAL
// Call upper layer bus init
CYG_SPI_BUS_COMMON_INIT(&qspi_bus->qspi_bus);
}
static void dspi_bus_setup(cyg_spi_freescale_dspi_bus_t* spi_bus_p)
{
cyghwr_devs_freescale_dspi_t* dspi_p = spi_bus_p->setup_p->dspi_p;
cyghwr_hal_freescale_dma_set_t* dma_set_p;
cyghwr_hal_freescale_edma_t* edma_p;
cyg_uint32 dma_chan_i;
// Get the clock frequency from HAL.
spi_bus_p->clock_freq = CYGHWR_IO_SPI_FREESCALE_DSPI_CLOCK;
DEBUG1_PRINTF("DSPI BUS %p: SysClk=%d\n", spi_bus_p, spi_bus_p->clock_freq);
// Set up the pins.
dspi_pin_setup(spi_bus_p->setup_p->spi_pin_list_p,
spi_bus_p->setup_p->cs_pin_list_p,
spi_bus_p->setup_p->cs_pin_num);
// Set up default SPI configuration.
dspi_p->mcr = spi_bus_p->setup_p->mcr_opt | FREESCALE_DSPI_MCR_MSTR_M |
FREESCALE_DSPI_MCR_CLR_RXF_M | FREESCALE_DSPI_MCR_CLR_TXF_M |
FREESCALE_DSPI_MCR_MDIS_M;
// Enable DSPI controller.
dspi_enable(dspi_p);
if((dma_set_p=spi_bus_p->setup_p->dma_set_p)) {
// Initialize DMA channels
hal_freescale_edma_init_chanset(dma_set_p);
#if DEBUG_SPI >= 1
hal_freescale_edma_diag(dma_set_p, 0xffff);
cyghwr_devs_freescale_dspi_diag(spi_bus_p);
#endif
// Set up DMA transfer control descriptors
edma_p = dma_set_p->edma_p;
dma_chan_i = dma_set_p->chan_p[SPI_DMA_CHAN_TX_I].dma_chan_i;
hal_freescale_edma_transfer_init(edma_p, dma_chan_i,
spi_bus_p->tx_dma_tcd_ini_p);
#if DEBUG_SPI >= 1
hal_freescale_edma_transfer_diag(edma_p, dma_chan_i, true);
#endif
dma_chan_i = dma_set_p->chan_p[SPI_DMA_CHAN_RX_I].dma_chan_i;
hal_freescale_edma_transfer_init(edma_p, dma_chan_i,
spi_bus_p->rx_dma_tcd_ini_p);
#if DEBUG_SPI >= 1
hal_freescale_edma_transfer_diag(edma_p, dma_chan_i, true);
#endif
// Enable SPI DMA requests
dspi_p->rser = FREESCALE_DSPI_RSER_TFFF_DIRS_M |
FREESCALE_DSPI_RSER_RFDF_DIRS_M |
FREESCALE_DSPI_RSER_TFFF_RE_M |
FREESCALE_DSPI_RSER_RFDF_RE_M;
}
#if DEBUG_SPI >= 1
cyghwr_devs_freescale_dspi_diag(spi_bus_p);
#endif
// Initialise the synchronisation primitivies.
cyg_drv_mutex_init (&spi_bus_p->transfer_mutex);
cyg_drv_cond_init (&spi_bus_p->transfer_done, &spi_bus_p->transfer_mutex);
// Hook up the ISR and DSR.
cyg_drv_interrupt_create (spi_bus_p->setup_p->intr_num,
spi_bus_p->setup_p->intr_prio,
(cyg_addrword_t) spi_bus_p,
dma_set_p ? dspi_dma_ISR : dspi_nodma_ISR,
dspi_DSR, &spi_bus_p->intr_handle,
&spi_bus_p->intr_data);
cyg_drv_interrupt_attach (spi_bus_p->intr_handle);
dspi_p->ctar[1] = dspi_calc_ctar(&aux_clocking, spi_bus_p->clock_freq);
// Call upper layer bus init.
CYG_SPI_BUS_COMMON_INIT(&spi_bus_p->spi_bus);
}