int
malo_cardbus_detach(struct device *self, int flags)
{
struct malo_cardbus_softc *csc = (struct malo_cardbus_softc *)self;
struct malo_softc *sc = &csc->sc_malo;
cardbus_devfunc_t ct = csc->sc_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
cardbus_function_tag_t cf = ct->ct_cf;
int error;
error = malo_detach(sc);
if (error != 0)
return (error);
/* unhook the interrupt handler */
if (csc->sc_ih != NULL) {
cardbus_intr_disestablish(cc, cf, csc->sc_ih);
csc->sc_ih = NULL;
}
/* release bus space and close window */
Cardbus_mapreg_unmap(ct, CARDBUS_BASE0_REG, sc->sc_mem1_bt,
sc->sc_mem1_bh, csc->sc_mapsize1);
Cardbus_mapreg_unmap(ct, CARDBUS_BASE1_REG, sc->sc_mem2_bt,
sc->sc_mem2_bh, csc->sc_mapsize2);
return (0);
}
int
ex_cardbus_detach(device_t self, int arg)
{
struct ex_cardbus_softc *csc = device_private(self);
struct ex_softc *sc = &csc->sc_softc;
struct cardbus_devfunc *ct = csc->sc_ct;
int rv;
#if defined(DIAGNOSTIC)
if (ct == NULL) {
panic("%s: data structure lacks", device_xname(self));
}
#endif
rv = ex_detach(sc);
if (rv == 0) {
/*
* Unhook the interrupt handler.
*/
cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, sc->sc_ih);
if (csc->sc_cardtype == EX_CB_CYCLONE) {
Cardbus_mapreg_unmap(ct,
CARDBUS_3C575BTX_FUNCSTAT_PCIREG,
csc->sc_funct, csc->sc_funch, csc->sc_funcsize);
}
Cardbus_mapreg_unmap(ct, CARDBUS_BASE0_REG, sc->sc_iot,
sc->sc_ioh, csc->sc_mapsize);
}
return (rv);
}
int
ahc_cardbus_detach(device_t self, int flags)
{
struct ahc_cardbus_softc *csc = device_private(self);
struct ahc_softc *ahc = &csc->sc_ahc;
int rv;
rv = ahc_detach(ahc, flags);
if (rv)
return rv;
if (ahc->ih) {
Cardbus_intr_disestablish(csc->sc_ct, ahc->ih);
ahc->ih = 0;
}
if (csc->sc_bar != 0) {
Cardbus_mapreg_unmap(csc->sc_ct, csc->sc_bar,
ahc->tag, ahc->bsh, csc->sc_size);
csc->sc_bar = 0;
}
return (0);
}
static int
fxp_cardbus_detach(device_t self, int flags)
{
struct fxp_cardbus_softc *csc = device_private(self);
struct fxp_softc *sc = &csc->sc;
struct cardbus_devfunc *ct = csc->ct;
int rv, reg;
#ifdef DIAGNOSTIC
if (ct == NULL)
panic("%s: data structure lacks", device_xname(self));
#endif
rv = fxp_detach(sc);
if (rv == 0) {
/*
* Unhook the interrupt handler.
*/
cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, sc->sc_ih);
/*
* release bus space and close window
*/
if (csc->base0_reg)
reg = CARDBUS_BASE0_REG;
else
reg = CARDBUS_BASE1_REG;
Cardbus_mapreg_unmap(ct, reg, sc->sc_st, sc->sc_sh, csc->size);
}
return (rv);
}
int
rtw_cardbus_detach(struct device *self, int flags)
{
struct rtw_cardbus_softc *csc = (void *)self;
struct rtw_softc *sc = &csc->sc_rtw;
struct rtw_regs *regs = &sc->sc_regs;
struct cardbus_devfunc *ct = csc->sc_ct;
int rv;
#if defined(DIAGNOSTIC)
if (ct == NULL)
panic("%s: data structure lacks", sc->sc_dev.dv_xname);
#endif
rv = rtw_detach(sc);
if (rv)
return (rv);
rtw_cardbus_funcregen(regs, 0);
/*
* Unhook the interrupt handler.
*/
if (csc->sc_ih != NULL)
cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
/*
* Release bus space and close window.
*/
if (csc->sc_bar_reg != 0)
Cardbus_mapreg_unmap(ct, csc->sc_bar_reg,
regs->r_bt, regs->r_bh, csc->sc_mapsize);
return (0);
}
/*
* Cardbus detach function: deallocate all resources
*/
int
re_cardbus_detach(struct device *self, int flags)
{
struct re_cardbus_softc *csc = (void *)self;
struct rl_softc *sc = &csc->sc_rl;
struct cardbus_devfunc *ct = csc->ct;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
/* Remove timeout handler */
timeout_del(&sc->timer_handle);
/* Detach PHY */
if (LIST_FIRST(&sc->sc_mii.mii_phys) != NULL)
mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
/* Delete media stuff */
ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
ether_ifdetach(ifp);
if_detach(ifp);
/* Disable interrupts */
if (csc->sc_ih != NULL)
cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
/* Free cardbus resources */
Cardbus_mapreg_unmap(ct, csc->sc_bar_reg, sc->rl_btag, sc->rl_bhandle,
csc->sc_mapsize);
return (0);
}
int
puc_cardbus_detach(struct device *self, int flags)
{
struct puc_cardbus_softc *sc = (struct puc_cardbus_softc *)self;
struct puc_softc *psc = &sc->sc_psc;
struct cardbus_devfunc *ct = sc->ct;
int i, rv;
for (i = PUC_MAX_PORTS; i--; ) {
if (psc->sc_ports[i].intrhand)
cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf,
psc->sc_ports[i].intrhand);
if (psc->sc_ports[i].dev)
if ((rv = config_detach(psc->sc_ports[i].dev, flags)))
return (rv);
}
for (i = PUC_NBARS; i--; )
if (psc->sc_bar_mappings[i].mapped)
Cardbus_mapreg_unmap(ct, psc->sc_bar_mappings[i].type,
psc->sc_bar_mappings[i].t,
psc->sc_bar_mappings[i].h,
psc->sc_bar_mappings[i].s);
return (0);
}
int
ral_cardbus_detach(struct device *self, int flags)
{
struct ral_cardbus_softc *csc = (struct ral_cardbus_softc *)self;
struct rt2560_softc *sc = &csc->sc_sc;
cardbus_devfunc_t ct = csc->sc_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
cardbus_function_tag_t cf = ct->ct_cf;
int error;
error = (*csc->sc_opns->detach)(sc);
if (error != 0)
return error;
/* unhook the interrupt handler */
if (csc->sc_ih != NULL) {
cardbus_intr_disestablish(cc, cf, csc->sc_ih);
csc->sc_ih = NULL;
}
/* release bus space and close window */
Cardbus_mapreg_unmap(ct, CARDBUS_BASE0_REG, sc->sc_st, sc->sc_sh,
csc->sc_mapsize);
return 0;
}
int
re_cardbus_detach(device_t self, int flags)
{
struct re_cardbus_softc *csc = device_private(self);
struct rtk_softc *sc = &csc->sc_rtk;
struct cardbus_devfunc *ct = csc->sc_ct;
int rv;
#ifdef DIAGNOSTIC
if (ct == NULL)
panic("%s: cardbus softc, cardbus_devfunc NULL",
device_xname(self));
#endif
rv = re_detach(sc);
if (rv)
return rv;
pmf_device_deregister(self);
/*
* Unhook the interrupt handler.
*/
if (csc->sc_ih != NULL)
cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
/*
* Release bus space and close window.
*/
if (csc->sc_bar_reg != 0)
Cardbus_mapreg_unmap(ct, csc->sc_bar_reg,
sc->rtk_btag, sc->rtk_bhandle, csc->sc_mapsize);
return 0;
}
/*
* Attach the interface. Allocate softc structures, do ifmedia
* setup and ethernet/BPF attach.
*/
void
re_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct re_cardbus_softc *csc = (struct re_cardbus_softc *)self;
struct rl_softc *sc = &csc->sc_rl;
struct cardbus_attach_args *ca = aux;
struct cardbus_softc *psc =
(struct cardbus_softc *)sc->sc_dev.dv_parent;
cardbus_chipset_tag_t cc = psc->sc_cc;
cardbus_function_tag_t cf = psc->sc_cf;
cardbus_devfunc_t ct = ca->ca_ct;
bus_addr_t adr;
char intrstr[16];
sc->sc_dmat = ca->ca_dmat;
csc->ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_pc = ca->ca_pc;
csc->sc_intrline = ca->ca_intrline;
/*
* Map control/status registers.
*/
if (Cardbus_mapreg_map(ct, RL_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
&sc->rl_btag, &sc->rl_bhandle, &adr, &csc->sc_mapsize) == 0) {
csc->sc_cben = CARDBUS_MEM_ENABLE;
csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
csc->sc_bar_reg = RL_PCI_LOMEM;
csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
} else {
printf(": can't map mem space\n");
return;
}
/* Enable power */
Cardbus_function_enable(ct);
/* Get chip out of powersave mode (if applicable), initialize
* config registers */
re_cardbus_setup(sc);
/* Allocate interrupt */
csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline,
IPL_NET, re_intr, sc, sc->sc_dev.dv_xname);
if (csc->sc_ih == NULL) {
printf(": couldn't establish interrupt at %d",
ca->ca_intrline);
Cardbus_function_disable(csc->ct);
return;
}
snprintf(intrstr, sizeof(intrstr), "irq %d", ca->ca_intrline);
/* Call bus-independent (common) attach routine */
if (re_attach(sc, intrstr)) {
cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
Cardbus_mapreg_unmap(ct, csc->sc_bar_reg, sc->rl_btag,
sc->rl_bhandle, csc->sc_mapsize);
}
}
void
malo_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct malo_cardbus_softc *csc = (struct malo_cardbus_softc *)self;
struct cardbus_attach_args *ca = aux;
struct malo_softc *sc = &csc->sc_malo;
cardbus_devfunc_t ct = ca->ca_ct;
bus_addr_t base;
int error;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_intrline = ca->ca_intrline;
/* power management hooks */
sc->sc_enable = malo_cardbus_enable;
sc->sc_disable = malo_cardbus_disable;
#if 0
sc->sc_power = malo_cardbus_power;
#endif
/* map control/status registers */
error = Cardbus_mapreg_map(ct, CARDBUS_BASE0_REG,
CARDBUS_MAPREG_TYPE_MEM, 0, &sc->sc_mem1_bt,
&sc->sc_mem1_bh, &base, &csc->sc_mapsize1);
if (error != 0) {
printf(": could not map 1st memory space\n");
return;
}
csc->sc_bar1_val = base | CARDBUS_MAPREG_TYPE_MEM;
/* map control/status registers */
error = Cardbus_mapreg_map(ct, CARDBUS_BASE1_REG,
CARDBUS_MAPREG_TYPE_MEM, 0, &sc->sc_mem2_bt,
&sc->sc_mem2_bh, &base, &csc->sc_mapsize2);
if (error != 0) {
printf(": could not map 2nd memory space\n");
Cardbus_mapreg_unmap(ct, CARDBUS_BASE0_REG, sc->sc_mem1_bt,
sc->sc_mem1_bh, csc->sc_mapsize1);
return;
}
csc->sc_bar2_val = base | CARDBUS_MAPREG_TYPE_MEM;
/* set up the PCI configuration registers */
malo_cardbus_setup(csc);
printf(": irq %d", csc->sc_intrline);
error = malo_attach(sc);
if (error != 0)
malo_cardbus_detach(&sc->sc_dev, 0);
Cardbus_function_disable(ct);
}
static int
njata_cardbus_detach(device_t self, int flags)
{
struct njata32_cardbus_softc *csc = device_private(self);
struct njata32_softc *sc = &csc->sc_njata32;
int rv;
rv = njata32_detach(sc, flags);
if (rv)
return rv;
if (sc->sc_ih)
Cardbus_intr_disestablish(csc->sc_ct, sc->sc_ih);
if (sc->sc_flags & NJATA32_IO_MAPPED)
Cardbus_mapreg_unmap(csc->sc_ct, NJATA32_CARDBUS_BASEADDR_IO,
NJATA32_REGT(sc), NJATA32_REGH(sc), csc->sc_regmap_size);
if (sc->sc_flags & NJATA32_MEM_MAPPED)
Cardbus_mapreg_unmap(csc->sc_ct, NJATA32_CARDBUS_BASEADDR_MEM,
NJATA32_REGT(sc), csc->sc_regmaph, csc->sc_regmap_size);
return 0;
}
static int
njs_cardbus_detach(struct device *self, int flags)
{
struct njsc32_cardbus_softc *csc = (void *) self;
struct njsc32_softc *sc = &csc->sc_njsc32;
int rv;
rv = njsc32_detach(sc, flags);
if (rv)
return rv;
if (sc->sc_ih)
cardbus_intr_disestablish(csc->sc_ct->ct_cc,
csc->sc_ct->ct_cf, sc->sc_ih);
if (sc->sc_flags & NJSC32_IO_MAPPED)
Cardbus_mapreg_unmap(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_IO,
sc->sc_regt, sc->sc_regh, csc->sc_regmap_size);
if (sc->sc_flags & NJSC32_MEM_MAPPED)
Cardbus_mapreg_unmap(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_MEM,
sc->sc_regt, csc->sc_regmaph, csc->sc_regmap_size);
return 0;
}
int
dc_cardbus_detach(struct device *self, int flags)
{
struct dc_cardbus_softc *csc = (struct dc_cardbus_softc *)self;
struct dc_softc *sc = &csc->sc_dc;
struct cardbus_devfunc *ct = csc->sc_ct;
cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, sc->sc_ih);
dc_detach(sc);
/* unmap cardbus resources */
Cardbus_mapreg_unmap(ct,
csc->sc_actype == CARDBUS_IO_ENABLE ? PCI_CBIO : PCI_CBMEM,
sc->dc_btag, sc->dc_bhandle, csc->sc_mapsize);
return (0);
}
int
com_cardbus_detach(struct device *self, int flags)
{
struct com_cardbus_softc *csc = (struct com_cardbus_softc *) self;
struct com_softc *sc = (struct com_softc *) self;
struct cardbus_softc *psc = (struct cardbus_softc *)self->dv_parent;
int error;
if ((error = com_detach(self, flags)) != 0)
return (error);
cardbus_intr_disestablish(psc->sc_cc, psc->sc_cf, csc->cc_ih);
Cardbus_mapreg_unmap(csc->cc_ct, csc->cc_reg, sc->sc_iot, sc->sc_ioh,
csc->cc_size);
return (0);
}
int
athn_cardbus_detach(struct device *self, int flags)
{
struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)self;
struct athn_softc *sc = &csc->sc_sc;
cardbus_devfunc_t ct = csc->sc_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
cardbus_function_tag_t cf = ct->ct_cf;
athn_detach(sc);
/* Unhook the interrupt handler. */
if (csc->sc_ih != NULL)
cardbus_intr_disestablish(cc, cf, csc->sc_ih);
/* Release bus space and close window. */
Cardbus_mapreg_unmap(ct, CARDBUS_BASE0_REG, csc->sc_st, csc->sc_sh,
csc->sc_mapsize);
return (0);
}
int
ehci_cardbus_detach(struct device *self, int flags)
{
struct ehci_cardbus_softc *sc = (struct ehci_cardbus_softc *)self;
struct cardbus_devfunc *ct = sc->sc_ct;
int rv;
rv = ehci_detach(self, flags);
if (rv)
return (rv);
if (sc->sc_ih != NULL) {
cardbus_intr_disestablish(sc->sc_cc, sc->sc_cf, sc->sc_ih);
sc->sc_ih = NULL;
}
if (sc->sc.sc_size) {
Cardbus_mapreg_unmap(ct, CARDBUS_CBMEM, sc->sc.iot,
sc->sc.ioh, sc->sc.sc_size);
sc->sc.sc_size = 0;
}
return (0);
}
int
ath_cardbus_detach(device_t self, int flags)
{
struct ath_cardbus_softc *csc = device_private(self);
struct ath_softc *sc = &csc->sc_ath;
struct cardbus_devfunc *ct = csc->sc_ct;
int rv;
#if defined(DIAGNOSTIC)
if (ct == NULL)
panic("%s: data structure lacks", device_xname(sc->sc_dev));
#endif
rv = ath_detach(sc);
if (rv)
return (rv);
pmf_device_deregister(self);
/*
* Unhook the interrupt handler.
*/
if (csc->sc_ih != NULL) {
cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
csc->sc_ih = NULL;
}
/*
* Release bus space and close window.
*/
Cardbus_mapreg_unmap(ct, ATH_PCI_MMBA, csc->sc_iot, csc->sc_ioh,
csc->sc_mapsize);
ATH_LOCK_DESTROY(sc);
return (0);
}
static int
uhci_cardbus_detach(device_t self, int flags)
{
struct uhci_cardbus_softc *sc = device_private(self);
struct cardbus_devfunc *ct = sc->sc_ct;
int rv;
rv = uhci_detach(&sc->sc, flags);
if (rv)
return (rv);
if (sc->sc_ih != NULL) {
Cardbus_intr_disestablish(ct, sc->sc_ih);
sc->sc_ih = NULL;
}
if (sc->sc.sc_size) {
Cardbus_mapreg_unmap(ct, PCI_CBIO, sc->sc.iot,
sc->sc.ioh, sc->sc.sc_size);
sc->sc.sc_size = 0;
}
#if NEHCI_CARDBUS > 0
usb_cardbus_rem(&sc->sc_cardbus);
#endif
return (0);
}
int
ral_cardbus_detach(device_t self, int flags)
{
struct ral_cardbus_softc *csc = device_private(self);
struct rt2560_softc *sc = &csc->sc_sc;
cardbus_devfunc_t ct = csc->sc_ct;
int error;
error = (*csc->sc_opns->detach)(sc);
if (error != 0)
return error;
/* unhook the interrupt handler */
if (csc->sc_ih != NULL) {
Cardbus_intr_disestablish(ct, csc->sc_ih);
csc->sc_ih = NULL;
}
/* release bus space and close window */
Cardbus_mapreg_unmap(ct, PCI_BAR0, sc->sc_st, sc->sc_sh,
csc->sc_mapsize);
return 0;
}
static void
njs_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct cardbus_attach_args *ca = aux;
struct njsc32_cardbus_softc *csc = (void *) self;
struct njsc32_softc *sc = &csc->sc_njsc32;
const struct njsc32_cardbus_product *prod;
cardbus_devfunc_t ct = ca->ca_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
cardbus_function_tag_t cf = ct->ct_cf;
pcireg_t reg;
int csr;
u_int8_t latency = 0x20;
if ((prod = njs_cardbus_lookup(ca)) == NULL)
panic("njs_cardbus_attach");
printf(": Workbit NinjaSCSI-32 SCSI adapter\n");
sc->sc_model = prod->p_model;
sc->sc_clk = prod->p_clk;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_intrline = ca->ca_intrline;
/*
* Map the device.
*/
csr = PCI_COMMAND_MASTER_ENABLE;
/*
* Map registers.
* Try memory map first, and then try I/O.
*/
if (Cardbus_mapreg_map(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_MEM,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&sc->sc_regt, &csc->sc_regmaph, NULL, &csc->sc_regmap_size) == 0) {
if (bus_space_subregion(sc->sc_regt, csc->sc_regmaph,
NJSC32_MEMOFFSET_REG, NJSC32_REGSIZE, &sc->sc_regh) != 0) {
/* failed -- undo map and try I/O */
Cardbus_mapreg_unmap(csc->sc_ct,
NJSC32_CARDBUS_BASEADDR_MEM,
sc->sc_regt, csc->sc_regmaph, csc->sc_regmap_size);
goto try_io;
}
#ifdef NJSC32_DEBUG
printf("%s: memory space mapped\n", sc->sc_dev.dv_xname);
#endif
csr |= PCI_COMMAND_MEM_ENABLE;
sc->sc_flags = NJSC32_MEM_MAPPED;
(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE);
} else {
try_io:
if (Cardbus_mapreg_map(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_IO,
PCI_MAPREG_TYPE_IO, 0, &sc->sc_regt, &sc->sc_regh,
NULL, &csc->sc_regmap_size) == 0) {
#ifdef NJSC32_DEBUG
printf("%s: io space mapped\n", sc->sc_dev.dv_xname);
#endif
csr |= PCI_COMMAND_IO_ENABLE;
sc->sc_flags = NJSC32_IO_MAPPED;
(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_IO_ENABLE);
} else {
printf("%s: unable to map device registers\n",
sc->sc_dev.dv_xname);
return;
}
}
/* Make sure the right access type is on the CardBus bridge. */
(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
/* Enable the appropriate bits in the PCI CSR. */
reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG);
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
reg |= csr;
cardbus_conf_write(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
/*
* Make sure the latency timer is set to some reasonable
* value.
*/
reg = cardbus_conf_read(cc, cf, ca->ca_tag, CARDBUS_BHLC_REG);
if (CARDBUS_LATTIMER(reg) < latency) {
reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
reg |= (latency << CARDBUS_LATTIMER_SHIFT);
cardbus_conf_write(cc, cf, ca->ca_tag, CARDBUS_BHLC_REG, reg);
}
sc->sc_dmat = ca->ca_dmat;
/*
* Establish the interrupt.
*/
sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_BIO,
njsc32_intr, sc);
if (sc->sc_ih == NULL) {
printf("%s: unable to establish interrupt at %d\n",
sc->sc_dev.dv_xname, ca->ca_intrline);
return;
}
printf("%s: interrupting at %d\n",
sc->sc_dev.dv_xname, ca->ca_intrline);
/* CardBus device cannot supply termination power. */
sc->sc_flags |= NJSC32_CANNOT_SUPPLY_TERMPWR;
/* attach */
njsc32_attach(sc);
}
static void
njata_cardbus_attach(device_t parent, device_t self, void *aux)
{
struct cardbus_attach_args *ca = aux;
struct njata32_cardbus_softc *csc = device_private(self);
struct njata32_softc *sc = &csc->sc_njata32;
const struct njata32_cardbus_product *prod;
cardbus_devfunc_t ct = ca->ca_ct;
pcireg_t reg;
int csr;
uint8_t latency = 0x20;
sc->sc_wdcdev.sc_atac.atac_dev = self;
if ((prod = njata_cardbus_lookup(ca)) == NULL)
panic("njata_cardbus_attach");
aprint_normal(": Workbit NinjaATA-32 IDE controller\n");
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
/*
* Map the device.
*/
csr = PCI_COMMAND_MASTER_ENABLE;
/*
* Map registers.
* Try memory map first, and then try I/O.
*/
if ((prod->p_flags & NJATA32_FL_IOMAP_ONLY) == 0 &&
Cardbus_mapreg_map(csc->sc_ct, NJATA32_CARDBUS_BASEADDR_MEM,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&NJATA32_REGT(sc), &csc->sc_regmaph, NULL, &csc->sc_regmap_size)
== 0) {
if (bus_space_subregion(NJATA32_REGT(sc), csc->sc_regmaph,
NJATA32_MEMOFFSET_REG, NJATA32_REGSIZE, &NJATA32_REGH(sc))
!= 0) {
/* failed -- undo map and try I/O */
Cardbus_mapreg_unmap(csc->sc_ct,
NJATA32_CARDBUS_BASEADDR_MEM, NJATA32_REGT(sc),
csc->sc_regmaph, csc->sc_regmap_size);
goto try_io;
}
#ifdef NJATA32_DEBUG
aprint_normal("%s: memory space mapped, size %u\n",
NJATA32NAME(sc), (unsigned)csc->sc_regmap_size);
#endif
csr |= PCI_COMMAND_MEM_ENABLE;
sc->sc_flags = NJATA32_MEM_MAPPED;
} else {
try_io:
if (Cardbus_mapreg_map(csc->sc_ct, NJATA32_CARDBUS_BASEADDR_IO,
PCI_MAPREG_TYPE_IO, 0, &NJATA32_REGT(sc),
&NJATA32_REGH(sc), NULL, &csc->sc_regmap_size) == 0) {
#ifdef NJATA32_DEBUG
aprint_normal("%s: io space mapped, size %u\n",
NJATA32NAME(sc), (unsigned)csc->sc_regmap_size);
#endif
csr |= PCI_COMMAND_IO_ENABLE;
sc->sc_flags = NJATA32_IO_MAPPED;
} else {
aprint_error("%s: unable to map device registers\n",
NJATA32NAME(sc));
return;
}
}
/* Enable the appropriate bits in the PCI CSR. */
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
reg |= csr;
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
/*
* Make sure the latency timer is set to some reasonable
* value.
*/
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);
if (PCI_LATTIMER(reg) < latency) {
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg |= (latency << PCI_LATTIMER_SHIFT);
Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);
}
sc->sc_dmat = ca->ca_dmat;
/*
* Establish the interrupt.
*/
sc->sc_ih = Cardbus_intr_establish(ct, IPL_BIO, njata32_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error("%s: unable to establish interrupt\n",
NJATA32NAME(sc));
return;
}
/* attach */
njata32_attach(sc);
}
