static void spi_interrupt_transceive(spi_device_t* device) {
Chip_SSP_DATA_SETUP_T* setup = &device->xf_setup;
Chip_SSP_Int_Disable(device->ssp_device); /* Disable all interrupt */
Chip_SSP_Int_RWFrames8Bits(device->ssp_device, setup);
if ((setup->rx_cnt != setup->length) || (setup->tx_cnt != setup->length)) {
Chip_SSP_Int_Enable(device->ssp_device); /* enable all interrupts */
}
else {
portBASE_TYPE woken = pdFALSE;
xSemaphoreGiveFromISR(device->sem_ready, &woken);
portYIELD_FROM_ISR(woken);
}
}
/**
* @brief SSP interrupt handler sub-routine
* @return Nothing
*/
void SSPIRQHANDLER(void)
{
Chip_SSP_Int_Disable(LPC_SSP); /* Disable all interrupt */
if (SSP_DATA_BYTES(ssp_format.bits) == 1) {
Chip_SSP_Int_RWFrames8Bits(LPC_SSP, &xf_setup);
}
else {
Chip_SSP_Int_RWFrames16Bits(LPC_SSP, &xf_setup);
}
if ((xf_setup.rx_cnt != xf_setup.length) || (xf_setup.tx_cnt != xf_setup.length)) {
Chip_SSP_Int_Enable(LPC_SSP); /* enable all interrupts */
}
else {
isXferCompleted = 1;
}
}
static void spi_transceive_internal(spi_device_t* device, uint8_t* read_buffer, const uint8_t* write_buffer, size_t size) {
xSemaphoreTake(device->mutex, portMAX_DELAY);
device->xf_setup.rx_data = read_buffer;
device->xf_setup.tx_data = (void*) write_buffer;
device->xf_setup.length = size;
device->xf_setup.rx_cnt = 0;
device->xf_setup.tx_cnt = 0;
Chip_SSP_Int_FlushData(device->ssp_device);
Chip_SSP_Int_RWFrames8Bits(device->ssp_device, &device->xf_setup);
Chip_SSP_Int_Enable(device->ssp_device);
// Wait till done
xSemaphoreTake(device->sem_ready, portMAX_DELAY);
xSemaphoreGive(device->mutex);
}
static void ssp_irq_handler( LPC_SSP_T * ssp_id )
{
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
Chip_SSP_DATA_SETUP_T * xf_setup;
uint8_t ssp_cfg_index;
if ((ssp_id == LPC_SSP0) && (active_SSP0 != 0xFF)) {
ssp_cfg_index = active_SSP0;
} else if (ssp_id == LPC_SSP1) {
/* The only component in SPI1 is the Flash memory */
ssp_cfg_index = FLASH_SPI;
}
xf_setup = &ssp_cfg[ssp_cfg_index].xf_setup;
/* Disable SSP interrupts */
Chip_SSP_Int_Disable(ssp_id);
if (ssp_cfg[ssp_cfg_index].frame_size <= 8) {
Chip_SSP_Int_RWFrames8Bits(ssp_id, xf_setup);
}
else {
Chip_SSP_Int_RWFrames16Bits(ssp_id, xf_setup);
}
if ((xf_setup->rx_cnt != xf_setup->length) || (xf_setup->tx_cnt != xf_setup->length)) {
/* Enable ssp interrupts, we're going to read/write more data */
Chip_SSP_Int_Enable(ssp_id);
}
else {
/* Transfer is completed, notify the caller task */
vTaskNotifyGiveFromISR(ssp_cfg[ssp_cfg_index].caller_task, &xHigherPriorityTaskWoken);
/* Deassert SSEL pin */
ssp_ssel_control(ssp_cfg_index, DEASSERT);
}
portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
}
/* Select the Transfer mode : Polling, Interrupt or DMA */
static void appSSPTest(void)
{
int key;
DEBUGOUT(sspTransferModeSel);
dmaChSSPTx = Chip_GPDMA_GetFreeChannel(LPC_GPDMA, LPC_GPDMA_SSP_TX);
dmaChSSPRx = Chip_GPDMA_GetFreeChannel(LPC_GPDMA, LPC_GPDMA_SSP_RX);
xf_setup.length = BUFFER_SIZE;
xf_setup.tx_data = Tx_Buf;
xf_setup.rx_data = Rx_Buf;
while (1) {
key = 0xFF;
do {
key = DEBUGIN();
} while ((key & 0xFF) == 0xFF);
Buffer_Init();
switch (key) {
case SSP_POLLING_SEL: /* SSP Polling Read Write Mode */
DEBUGOUT(sspWaitingMenu);
xf_setup.rx_cnt = xf_setup.tx_cnt = 0;
Chip_SSP_RWFrames_Blocking(LPC_SSP, &xf_setup);
if (Buffer_Verify() == 0) {
DEBUGOUT(sspPassedMenu);
}
else {
DEBUGOUT(sspFailedMenu);
}
break;
case SSP_INTERRUPT_SEL:
DEBUGOUT(sspIntWaitingMenu);
isXferCompleted = 0;
xf_setup.rx_cnt = xf_setup.tx_cnt = 0;
Chip_SSP_Int_FlushData(LPC_SSP);/* flush dummy data from SSP FiFO */
if (SSP_DATA_BYTES(ssp_format.bits) == 1) {
Chip_SSP_Int_RWFrames8Bits(LPC_SSP, &xf_setup);
}
else {
Chip_SSP_Int_RWFrames16Bits(LPC_SSP, &xf_setup);
}
Chip_SSP_Int_Enable(LPC_SSP); /* enable interrupt */
while (!isXferCompleted) {}
if (Buffer_Verify() == 0) {
DEBUGOUT(sspPassedMenu);
}
else {
DEBUGOUT(sspFailedMenu);
}
break;
case SSP_DMA_SEL: /* SSP DMA Read and Write: fixed on 8bits */
DEBUGOUT(sspDMAWaitingMenu);
isDmaTxfCompleted = isDmaRxfCompleted = 0;
Chip_SSP_DMA_Enable(LPC_SSP);
/* data Tx_Buf --> SSP */
Chip_GPDMA_Transfer(LPC_GPDMA, dmaChSSPTx,
(uint32_t) &Tx_Buf[0],
LPC_GPDMA_SSP_TX,
GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA,
BUFFER_SIZE);
/* data SSP --> Rx_Buf */
Chip_GPDMA_Transfer(LPC_GPDMA, dmaChSSPRx,
LPC_GPDMA_SSP_RX,
(uint32_t) &Rx_Buf[0],
GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA,
BUFFER_SIZE);
while (!isDmaTxfCompleted || !isDmaRxfCompleted) {}
if (Buffer_Verify() == 0) {
DEBUGOUT(sspPassedMenu);
}
else {
DEBUGOUT(sspFailedMenu);
}
Chip_SSP_DMA_Disable(LPC_SSP);
break;
case 'q':
case 'Q':
Chip_GPDMA_Stop(LPC_GPDMA, dmaChSSPTx);
Chip_GPDMA_Stop(LPC_GPDMA, dmaChSSPRx);
return;
default:
break;
}
DEBUGOUT(sspTransferModeSel);
}
}