/**
* \brief Initialize the DACC controller
* \param pDACC Pointer to an DACC instance.
* \param idDACC identifier of DAC peripheral
* \param trgEn trigger mode, free running mode or external Hardware trigger
* \param word transfer size,word or half word
* \param trgSel hardware trigger selection
* \param sleepMode sleep mode selection
* \param mck value of MCK in Hz
* \param refresh refresh period
* \param user_sel user channel selection ,0 or 1
* \param tag_mode tag for channel number
* \param startup value of the start up time (in DACCClock) (see datasheet)
*/
void DACC_Initialize (Dacc *pDACC,
uint8_t idDACC,
uint8_t trgEn,
uint8_t trgSel,
uint8_t word,
uint8_t sleepMode,
uint32_t mck,
uint8_t refresh,/*refresh period*/
uint8_t user_sel,/*user channel selection*/
uint32_t tag_mode,/*using tag for channel number*/
uint32_t startup
)
{
ASSERT(1024*refresh*1000/(mck/2)<20,"Refresh preriod is too big!");
/* Enable peripheral clock*/
PMC->PMC_PCER0 = 1 << idDACC;
/* Reset the controller */
DACC_SoftReset(pDACC);
/* Write to the MR register */
DACC_CfgModeReg( pDACC,
( trgEn & DACC_MR_TRGEN)
| ( trgSel & DACC_MR_TRGSEL)
| ( word & DACC_MR_WORD)
| ( sleepMode & DACC_MR_SLEEP)
| ( (refresh<<8) & DACC_MR_REFRESH)
| ( (user_sel<<16)& DACC_MR_USER_SEL)
| ( tag_mode & DACC_MR_TAG)
| ( (startup<<24) & DACC_MR_STARTUP));
}
/**
* \brief Initialize the DACC controller
* \param pDACC Pointer to an DACC instance.
* \param idDACC identifier of DAC peripheral
* \param trgEn trigger mode, free running mode or external Hardware trigger
* \param trgSel hardware trigger selection
* \param dacEn enable DAC
* \param word transfer size,word or half word
* \param startup value of the start up time (in DACCClock) (see datasheet)
* \param clkDiv value of the DAC clock divider for internal trigger
*/
extern void DACC_Initialize( Dacc* pDACC,
uint8_t idDACC,
uint8_t trgEn,
uint8_t trgSel,
uint8_t dacEn,
uint8_t word,
uint32_t startup,
uint32_t clkDiv
)
{
/* Enable peripheral clock*/
PMC->PMC_PCER = 1 << idDACC;
/* Reset the controller */
DACC_SoftReset(pDACC);
/* Write to the MR register */
DACC_CfgModeReg( pDACC,
( trgEn & DACC_MR_TRGEN )
| ( trgSel & DACC_MR_TRGSEL )
| ( dacEn & DACC_MR_DACEN )
| ( word & DACC_MR_WORD )
| ( startup & DACC_MR_STARTUP )
| ( clkDiv & DACC_MR_CLKDIV ) );
}
/**
* \brief Initialize the DACC controller
* \param pDACC Pointer to an DACC instance.
* \param idDACC identifier of DAC peripheral
* \param trgEn trigger mode, free running mode or external Hardware trigger
* \param word transfer size,word or half word
* \param trgSel hardware trigger selection
* \param sleepMode sleep mode selection
* \param mck value of MCK in Hz
* \param refresh refresh period
* \param user_sel user channel selection ,0 or 1
* \param tag_mode tag for channel number
* \param startup value of the start up time (in DACCClock) (see datasheet)
*/
extern void DACC_Initialize( Dacc* pDACC,
uint8_t idDACC,
uint8_t trgEn,
uint8_t trgSel,
uint8_t word,
uint8_t sleepMode,
uint32_t mck,
uint8_t refresh, /* refresh period */
uint8_t user_sel, /* user channel selection */
uint32_t tag_mode, /* using tag for channel number */
uint32_t startup
)
{
/* Stop warning */
mck = mck;
/* Enable peripheral clock*/
PMC->PMC_PCER0 = 1 << idDACC;
/* Reset the controller */
DACC_SoftReset(pDACC);
/* Write to the MR register */
DACC_CfgModeReg( pDACC,
( trgEn & DACC_MR_TRGEN)
| DACC_MR_TRGSEL(trgSel)
| ( word & DACC_MR_WORD)
| ( sleepMode & DACC_MR_SLEEP)
| DACC_MR_REFRESH(refresh)
| ( user_sel & DACC_MR_USER_SEL_Msk)
| ( tag_mode & DACC_MR_TAG)
| ( startup & DACC_MR_STARTUP_Msk));
}
