/***************************************************************************//** * @brief dac_datasel *******************************************************************************/ int dac_datasel(struct ad9361_rf_phy *phy, int32_t chan, enum dds_data_select sel) { if (PCORE_VERSION_MAJOR(dds_st[phy->id_no].pcore_version) > 7) { if (chan < 0) { /* ALL */ uint32_t i; for (i = 0; i < dds_st[phy->id_no].num_dds_channels; i++) { dac_write(phy, DAC_REG_CHAN_CNTRL_7(i), sel); } } else { dac_write(phy, DAC_REG_CHAN_CNTRL_7(chan), sel); } } else { uint32_t reg; switch(sel) { case DATA_SEL_DDS: case DATA_SEL_SED: case DATA_SEL_DMA: dac_read(phy, DAC_REG_CNTRL_2, ®); reg &= ~DAC_DATA_SEL(~0); reg |= DAC_DATA_SEL(sel); dac_write(phy, DAC_REG_CNTRL_2, reg); break; default: return -EINVAL; } } return 0; }
int32_t dac_data_src_sel(dac_core *core, int32_t chan, dac_data_src src) { uint32_t pcore_version; uint32_t reg; int32_t i; dac_read(core, DAC_REG_VERSION, &pcore_version); // single core control for all channels if (DAC_PCORE_VERSION_MAJOR(pcore_version) < 7) { dac_read(core, DAC_REG_DATA_CONTROL, ®); reg = (reg & ~DAC_DATA_SEL(~0)) | DAC_DATA_SEL(src); dac_write(core, DAC_REG_DATA_CONTROL, reg); return(0); } // per channel source select for (i = 0; i < (core->no_of_channels * 2); i++) { if ((chan < 0) || (chan == i)) dac_write(core, DAC_REG_DATA_SELECT(i), src); } dac_write(core, DAC_REG_SYNC_CONTROL, DAC_SYNC); return(0); }