//*****************************************************************************
//
// Configure the oscillator input to the a source clock.
//
//*****************************************************************************
void
OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc)
{
// Check the arguments.
ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) ||
(ui32SrcClk & OSC_SRC_CLK_HF));
ASSERT((ui32Osc == OSC_RCOSC_HF) ||
(ui32Osc == OSC_RCOSC_LF) ||
(ui32Osc == OSC_XOSC_HF) ||
(ui32Osc == OSC_XOSC_LF));
// Request the high frequency source clock (using 24 MHz XTAL)
if(ui32SrcClk & OSC_SRC_CLK_HF)
{
// Enable the HF XTAL as HF clock source
DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0,
DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M,
DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S,
ui32Osc);
}
// Configure the low frequency source clock.
if(ui32SrcClk & OSC_SRC_CLK_LF)
{
// Change the clock source.
DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0,
DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M,
DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S,
ui32Osc);
}
}
/*
* ======== Power_LF_clockFunc ========
*/
Void Power_LF_clockFunc(UArg arg)
{
UInt32 sourceLF;
/* query LF clock source */
sourceLF = OSCClockSourceGet(OSC_SRC_CLK_LF);
/* is LF source either RCOSC_LF or XOSC_LF yet? */
if ((sourceLF == OSC_RCOSC_LF) || (sourceLF == OSC_XOSC_LF)) {
/* yes, disable the LF clock qualifiers */
DDI16BitfieldWrite(
AUX_DDI0_OSC_BASE,
DDI_0_OSC_O_CTL0,
DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M|
DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M,
DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S,
0x3
);
/* now finish by releasing the standby disallow constraint */
Power_releaseConstraint(Power_SB_DISALLOW);
}
/* not yet, LF still derived from HF, restart clock to check back later */
else {
/* retrigger LF Clock to fire in 100 msec */
Clock_setTimeout(
ti_sysbios_family_arm_cc26xx_Power_Module_State_lfClockObj(),
(100000 / Clock_tickPeriod));
Clock_start(
ti_sysbios_family_arm_cc26xx_Power_Module_State_lfClockObj());
}
}
//*****************************************************************************
//
//! Configure the oscillator input to the a source clock.
//
//*****************************************************************************
void
OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc)
{
//
// Check the arguments.
//
ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) ||
(ui32SrcClk & OSC_SRC_CLK_MF) ||
(ui32SrcClk & OSC_SRC_CLK_HF));
ASSERT((ui32Osc == OSC_RCOSC_HF) ||
(ui32Osc == OSC_RCOSC_LF) ||
(ui32Osc == OSC_XOSC_HF) ||
(ui32Osc == OSC_XOSC_LF));
//
// Request the high frequency source clock (using 24 MHz XTAL)
//
if(ui32SrcClk & OSC_SRC_CLK_HF)
{
//
// Enable the HF XTAL as HF clock source
//
DDI16BitfieldWrite(AUX_OSCDDI_BASE, OSC_DIG_O_CTL0,
OSC_DIG_CTL0_SCLK_HF_SRC_SEL_M,
OSC_DIG_CTL0_SCLK_HF_SRC_SEL_S,
ui32Osc);
//
// Using 24 MHz Xtal...
//
DDI16BitfieldWrite(AUX_OSCDDI_BASE, OSC_DIG_O_CTL0,
OSC_DIG_CTL0_XTAL_IS_24M_M,
OSC_DIG_CTL0_XTAL_IS_24M_S,
0x1);
}
//
// Configure the medium frequency source clock
//
if(ui32SrcClk & OSC_SRC_CLK_MF)
{
DDI16BitfieldWrite(AUX_OSCDDI_BASE, OSC_DIG_O_CTL0,
OSC_DIG_CTL0_SCLK_MF_SRC_SEL_M,
OSC_DIG_CTL0_SCLK_MF_SRC_SEL_S,
ui32Osc);
}
//
// Configure the low frequency source clock.
//
if(ui32SrcClk & OSC_SRC_CLK_LF)
{
//
// Change the clock source.
//
DDI16BitfieldWrite(AUX_OSCDDI_BASE, OSC_DIG_O_CTL0,
OSC_DIG_CTL0_SCLK_LF_SRC_SEL_M,
OSC_DIG_CTL0_SCLK_LF_SRC_SEL_S,
ui32Osc);
}
}
