[TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
.name = #pg_name, \
.reg_bank = 0, \
.reg = ((r) - PINGROUP_REG_A), \
.drvup_offset = 20, \
.drvup_mask = 0x1f, \
.drvdown_offset = 12, \
.drvdown_mask = 0x1f, \
.slewrise_offset = 28, \
.slewrise_mask = 0x3, \
.slewfall_offset = 30, \
.slewfall_mask = 0x3, \
}
const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
DEFAULT_DRIVE_PINGROUP(AO1, 0x868),
DEFAULT_DRIVE_PINGROUP(AO2, 0x86c),
SET_DRIVE_PINGROUP(AT1, 0x870, 14, 0x1f, 19, 0x1f,
24, 0x3, 28, 0x3),
SET_DRIVE_PINGROUP(AT2, 0x874, 14, 0x1f, 19, 0x1f,
24, 0x3, 28, 0x3),
SET_DRIVE_PINGROUP(AT3, 0x878, 14, 0x1f, 19, 0x1f,
28, 0x3, 30, 0x3),
SET_DRIVE_PINGROUP(AT4, 0x87c, 14, 0x1f, 19, 0x1f,
28, 0x3, 30, 0x3),
SET_DRIVE_PINGROUP(AT5, 0x880, 14, 0x1f, 19, 0x1f,
28, 0x3, 30, 0x3),
DEFAULT_DRIVE_PINGROUP(CDEV1, 0x884),
DEFAULT_DRIVE_PINGROUP(CDEV2, 0x888),
DEFAULT_DRIVE_PINGROUP(CSUS, 0x88c),
DEFAULT_DRIVE_PINGROUP(DAP1, 0x890),
.drvdown_offset = drv_down_offset, \
.drvdown_mask = drv_down_mask, \
}
#define DEFAULT_DRIVE_PINGROUP(pg_name, r) \
[TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
.name = #pg_name, \
.reg = r, \
.drvup_offset = 20, \
.drvup_mask = 0x1f, \
.drvdown_offset = 12, \
.drvdown_mask = 0x1f, \
}
const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
DEFAULT_DRIVE_PINGROUP(AO1, 0x868),
DEFAULT_DRIVE_PINGROUP(AO2, 0x86c),
DEFAULT_DRIVE_PINGROUP(AT1, 0x870),
DEFAULT_DRIVE_PINGROUP(AT2, 0x874),
DEFAULT_DRIVE_PINGROUP(CDEV1, 0x878),
DEFAULT_DRIVE_PINGROUP(CDEV2, 0x87c),
DEFAULT_DRIVE_PINGROUP(CSUS, 0x880),
DEFAULT_DRIVE_PINGROUP(DAP1, 0x884),
DEFAULT_DRIVE_PINGROUP(DAP2, 0x888),
DEFAULT_DRIVE_PINGROUP(DAP3, 0x88c),
DEFAULT_DRIVE_PINGROUP(DAP4, 0x890),
DEFAULT_DRIVE_PINGROUP(DBG, 0x894),
DEFAULT_DRIVE_PINGROUP(LCD1, 0x898),
DEFAULT_DRIVE_PINGROUP(LCD2, 0x89c),
DEFAULT_DRIVE_PINGROUP(SDMMC2, 0x8a0),
DEFAULT_DRIVE_PINGROUP(SDMMC3, 0x8a4),
