return 0;
}
static void console_reset(DeviceState *dev)
{
SCLPEvent *event = SCLP_EVENT(dev);
SCLPConsoleLM *scon = SCLPLM_CONSOLE(event);
event->event_pending = false;
scon->length = 0;
scon->write_errors = 0;
}
static Property console_properties[] = {
DEFINE_PROP_CHR("chardev", SCLPConsoleLM, chr),
DEFINE_PROP_UINT32("write_errors", SCLPConsoleLM, write_errors, 0),
DEFINE_PROP_BOOL("echo", SCLPConsoleLM, echo, true),
DEFINE_PROP_END_OF_LIST(),
};
static void console_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SCLPEventClass *ec = SCLP_EVENT_CLASS(klass);
dc->props = console_properties;
dc->reset = console_reset;
dc->vmsd = &vmstate_sclplmconsole;
ec->init = console_init;
ec->get_send_mask = send_mask;
ec->get_receive_mask = receive_mask;
VirtIORNG *vrng = VIRTIO_RNG(dev);
timer_del(vrng->rate_limit_timer);
timer_free(vrng->rate_limit_timer);
unregister_savevm(dev, "virtio-rng", vrng);
virtio_cleanup(vdev);
}
static Property virtio_rng_properties[] = {
/* Set a default rate limit of 2^47 bytes per minute or roughly 2TB/s. If
* you have an entropy source capable of generating more entropy than this
* and you can pass it through via virtio-rng, then hats off to you. Until
* then, this is unlimited for all practical purposes.
*/
DEFINE_PROP_UINT64("max-bytes", VirtIORNG, conf.max_bytes, INT64_MAX),
DEFINE_PROP_UINT32("period", VirtIORNG, conf.period_ms, 1 << 16),
DEFINE_PROP_END_OF_LIST(),
};
static void virtio_rng_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
dc->props = virtio_rng_properties;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
vdc->realize = virtio_rng_device_realize;
vdc->unrealize = virtio_rng_device_unrealize;
vdc->get_features = get_features;
}
}
};
static const VMStateDescription vmstate_arm_mptimer = {
.name = "arm_mptimer",
.version_id = 2,
.minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_STRUCT_VARRAY_UINT32(timerblock, ARMMPTimerState, num_cpu,
2, vmstate_timerblock, TimerBlock),
VMSTATE_END_OF_LIST()
}
};
static Property arm_mptimer_properties[] = {
DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0),
DEFINE_PROP_END_OF_LIST()
};
static void arm_mptimer_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
sbc->init = arm_mptimer_init;
dc->vmsd = &vmstate_arm_mptimer;
dc->reset = arm_mptimer_reset;
dc->no_user = 1;
dc->props = arm_mptimer_properties;
}
if (qdev_hotplug) {
generic_loader_reset(dev);
}
}
static void generic_loader_unrealize(DeviceState *dev, Error **errp)
{
qemu_unregister_reset_loader(generic_loader_reset, dev);
}
static Property generic_loader_props[] = {
DEFINE_PROP_UINT64("addr", GenericLoaderState, addr, 0),
DEFINE_PROP_UINT64("data", GenericLoaderState, data, 0),
DEFINE_PROP_UINT8("data-len", GenericLoaderState, data_len, 0),
DEFINE_PROP_BOOL("data-be", GenericLoaderState, data_be, false),
DEFINE_PROP_UINT32("cpu-num", GenericLoaderState, cpu_num, CPU_NONE),
DEFINE_PROP_BOOL("force-raw", GenericLoaderState, force_raw, false),
DEFINE_PROP_STRING("file", GenericLoaderState, file),
DEFINE_PROP_UINT16("attrs-requester-id", GenericLoaderState,
attrs.requester_id, 0),
DEFINE_PROP_BOOL("attrs-debug", GenericLoaderState, attrs.debug, false),
DEFINE_PROP_BOOL("attrs-secure", GenericLoaderState, attrs.secure, false),
DEFINE_PROP_END_OF_LIST(),
};
static void generic_loader_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
/* The reset function is not registered here and is instead registered in
* the realize function to allow this device to be added via the device_add
static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
void *opaque, const char *name,
Error **errp)
{
Q35PCIHost *s = Q35_HOST_DEVICE(obj);
visit_type_uint64(v, &s->mch.pci_info.w64.end, name, errp);
}
static Property mch_props[] = {
DEFINE_PROP_UINT64("MCFG", Q35PCIHost, parent_obj.base_addr,
MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 1),
DEFINE_PROP_END_OF_LIST(),
};
static void q35_host_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
hc->root_bus_path = q35_host_root_bus_path;
dc->realize = q35_host_realize;
dc->props = mch_props;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->fw_name = "pci";
}
}
void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
int secondary_ide_enabled)
{
PCIDevice *dev;
dev = pci_create(bus, -1, "cmd646-ide");
qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
qdev_init_nofail(&dev->qdev);
pci_ide_create_devs(dev, hd_table);
}
static Property cmd646_ide_properties[] = {
DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void cmd646_ide_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = pci_cmd646_ide_initfn;
k->exit = pci_cmd646_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_CMD;
k->device_id = PCI_DEVICE_ID_CMD_646;
k->revision = 0x07;
k->class_id = PCI_CLASS_STORAGE_IDE;
dc->props = cmd646_ide_properties;
VMSTATE_INT32(health, GoldfishBatteryDevice),
VMSTATE_INT32(present, GoldfishBatteryDevice),
VMSTATE_INT32(capacity, GoldfishBatteryDevice),
VMSTATE_END_OF_LIST()
}
};
static GoldfishDeviceInfo goldfish_battery_info = {
.init = goldfish_battery_init,
.readfn = goldfish_battery_readfn,
.writefn = goldfish_battery_writefn,
.qdev.name = "goldfish-battery",
.qdev.size = sizeof(GoldfishBatteryDevice),
.qdev.vmsd = &vmstate_goldfish_battery,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("base", GoldfishDevice, base, 0),
DEFINE_PROP_UINT32("id", GoldfishDevice, id, 0),
DEFINE_PROP_UINT32("size", GoldfishDevice, size, 0x1000),
DEFINE_PROP_UINT32("irq", GoldfishDevice, irq, 0),
DEFINE_PROP_UINT32("irq_count", GoldfishDevice, irq_count, 1),
DEFINE_PROP_INT32("ac_online", GoldfishBatteryDevice, ac_online, 1),
DEFINE_PROP_INT32("status", GoldfishBatteryDevice, status, POWER_SUPPLY_STATUS_CHARGING),
DEFINE_PROP_INT32("health", GoldfishBatteryDevice, health, POWER_SUPPLY_HEALTH_GOOD),
DEFINE_PROP_INT32("present", GoldfishBatteryDevice, present, 1), // battery is present
DEFINE_PROP_INT32("capacity", GoldfishBatteryDevice, capacity, 50), // 50% charged
DEFINE_PROP_STRING("name", GoldfishDevice, name),
DEFINE_PROP_END_OF_LIST(),
},
};
static void goldfish_battery_register(void)
vhid->ledstate |= ledbit;
} else {
vhid->ledstate &= ~ledbit;
}
kbd_put_ledstate(vhid->ledstate);
break;
default:
fprintf(stderr, "%s: unknown type %d\n", __func__,
le16_to_cpu(event->type));
break;
}
}
static Property virtio_input_hid_properties[] = {
DEFINE_PROP_STRING("display", VirtIOInputHID, display),
DEFINE_PROP_UINT32("head", VirtIOInputHID, head, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void virtio_input_hid_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
VirtIOInputClass *vic = VIRTIO_INPUT_CLASS(klass);
dc->props = virtio_input_hid_properties;
vic->realize = virtio_input_hid_realize;
vic->unrealize = virtio_input_hid_unrealize;
vic->change_active = virtio_input_hid_change_active;
vic->handle_status = virtio_input_hid_handle_status;
}
* name as before.
*/
if (proxy->id) {
bus_name = g_strdup_printf("%s.0", proxy->id);
virtio_device_set_child_bus_name(VIRTIO_DEVICE(vdev), bus_name);
g_free(bus_name);
}
qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
object_property_set_bool(OBJECT(vdev), true, "realized", errp);
}
static Property virtio_serial_pci_properties[] = {
DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true),
DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2),
DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void virtio_serial_pci_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
k->realize = virtio_serial_pci_realize;
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
dc->props = virtio_serial_pci_properties;
pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET;
pcidev_k->device_id = PCI_DEVICE_ID_VIRTIO_CONSOLE;
pcidev_k->revision = VIRTIO_PCI_ABI_VERSION;
VMSTATE_UINT8(read_reg_select, PICCommonState),
VMSTATE_UINT8(poll, PICCommonState),
VMSTATE_UINT8(special_mask, PICCommonState),
VMSTATE_UINT8(init_state, PICCommonState),
VMSTATE_UINT8(auto_eoi, PICCommonState),
VMSTATE_UINT8(rotate_on_auto_eoi, PICCommonState),
VMSTATE_UINT8(special_fully_nested_mode, PICCommonState),
VMSTATE_UINT8(init4, PICCommonState),
VMSTATE_UINT8(single_mode, PICCommonState),
VMSTATE_UINT8(elcr, PICCommonState),
VMSTATE_END_OF_LIST()
}
};
static Property pic_properties_common[] = {
DEFINE_PROP_UINT32("iobase", PICCommonState, iobase, -1),
DEFINE_PROP_UINT32("elcr_addr", PICCommonState, elcr_addr, -1),
DEFINE_PROP_UINT8("elcr_mask", PICCommonState, elcr_mask, -1),
DEFINE_PROP_BIT("master", PICCommonState, master, 0, false),
DEFINE_PROP_END_OF_LIST(),
};
static void pic_common_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_pic_common;
dc->props = pic_properties_common;
dc->realize = pic_common_realize;
/*
* Reason: unlike ordinary ISA devices, the PICs need additional
s->timer[1] = arm_timer_init(s->freq1);
s->timer[0]->irq = qi[0];
s->timer[1]->irq = qi[1];
memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
return 0;
}
static SysBusDeviceInfo sp804_info = {
.init = sp804_init,
.qdev.name = "sp804",
.qdev.size = sizeof(sp804_state),
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("freq0", sp804_state, freq0, 1000000),
DEFINE_PROP_UINT32("freq1", sp804_state, freq1, 1000000),
DEFINE_PROP_END_OF_LIST(),
}
};
/* Integrator/CP timer module. */
typedef struct {
SysBusDevice busdev;
MemoryRegion iomem;
arm_timer_state *timer[3];
} icp_pit_state;
static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset,
unsigned size)
.version_id = 0,
.minimum_version_id = 0,
.pre_load = ivshmem_pre_load,
.post_load = ivshmem_post_load,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
VMSTATE_MSIX(parent_obj, IVShmemState),
VMSTATE_UINT32(intrstatus, IVShmemState),
VMSTATE_UINT32(intrmask, IVShmemState),
VMSTATE_END_OF_LIST()
},
};
static Property ivshmem_doorbell_properties[] = {
DEFINE_PROP_CHR("chardev", IVShmemState, server_chr),
DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1),
DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD,
true),
DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF),
DEFINE_PROP_END_OF_LIST(),
};
static void ivshmem_doorbell_init(Object *obj)
{
IVShmemState *s = IVSHMEM_DOORBELL(obj);
s->features |= (1 << IVSHMEM_MSI);
s->legacy_size = SIZE_MAX; /* whatever the server sends */
}
static void ivshmem_doorbell_realize(PCIDevice *dev, Error **errp)
isa_register_portio_list(ISA_DEVICE(dev), &s->portio, 0x0,
rs6000mc_port_list, s, "rs6000mc");
}
static const VMStateDescription vmstate_rs6000mc = {
.name = "rs6000-mc",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(port0820_index, RS6000MCState),
VMSTATE_END_OF_LIST()
},
};
static Property rs6000mc_properties[] = {
DEFINE_PROP_UINT32("ram-size", RS6000MCState, ram_size, 0),
DEFINE_PROP_BOOL("auto-configure", RS6000MCState, autoconfigure, true),
DEFINE_PROP_END_OF_LIST()
};
static void rs6000mc_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = rs6000mc_realize;
dc->vmsd = &vmstate_rs6000mc;
dc->props = rs6000mc_properties;
}
static const TypeInfo rs6000mc_info = {
.name = TYPE_RS6000MC,
static void m25p80_reset(DeviceState *d)
{
Flash *s = M25P80(d);
reset_memory(s);
}
static void m25p80_pre_save(void *opaque)
{
flash_sync_dirty((Flash *)opaque, -1);
}
static Property m25p80_properties[] = {
/* This is default value for Micron flash */
DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
DEFINE_PROP_DRIVE("drive", Flash, blk),
DEFINE_PROP_END_OF_LIST(),
};
static const VMStateDescription vmstate_m25p80 = {
.name = "m25p80",
.version_id = 0,
.minimum_version_id = 0,
.pre_save = m25p80_pre_save,
.fields = (VMStateField[]) {
VMSTATE_UINT8(state, Flash),
}
int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs)
{
KVMOpenPICState *opp = KVM_OPENPIC(d);
struct kvm_enable_cap encap = {};
encap.cap = KVM_CAP_IRQ_MPIC;
encap.args[0] = opp->fd;
encap.args[1] = cs->cpu_index;
return kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &encap);
}
static Property kvm_openpic_properties[] = {
DEFINE_PROP_UINT32("model", KVMOpenPICState, model,
OPENPIC_MODEL_FSL_MPIC_20),
DEFINE_PROP_END_OF_LIST(),
};
static void kvm_openpic_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = kvm_openpic_realize;
dc->props = kvm_openpic_properties;
dc->reset = kvm_openpic_reset;
}
static const TypeInfo kvm_openpic_info = {
.name = TYPE_KVM_OPENPIC,
.parent = TYPE_SYS_BUS_DEVICE,
timer_del(s->eof_timer);
timer_free(s->eof_timer);
}
static void usb_ohci_reset_pci(DeviceState *d)
{
PCIDevice *dev = PCI_DEVICE(d);
OHCIPCIState *ohci = PCI_OHCI(dev);
OHCIState *s = &ohci->state;
ohci_hard_reset(s);
}
static Property ohci_pci_properties[] = {
DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus),
DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3),
DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0),
DEFINE_PROP_END_OF_LIST(),
};
static const VMStateDescription vmstate_ohci = {
.name = "ohci",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, OHCIPCIState),
VMSTATE_STRUCT(state, OHCIPCIState, 1, vmstate_ohci_state, OHCIState),
VMSTATE_END_OF_LIST()
}
};
sysbus_init_mmio(sbd, &s->iomem);
}
static const VMStateDescription vmstate_aspeed_scu = {
.name = "aspeed.scu",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS),
VMSTATE_END_OF_LIST()
}
};
static Property aspeed_scu_properties[] = {
DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),
DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void aspeed_scu_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = aspeed_scu_realize;
dc->reset = aspeed_scu_reset;
dc->desc = "ASPEED System Control Unit";
dc->vmsd = &vmstate_aspeed_scu;
dc->props = aspeed_scu_properties;
}
set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
if (tcg_enabled() && !tcg_initialized) {
tcg_initialized = true;
mb_tcg_init();
}
}
static const VMStateDescription vmstate_mb_cpu = {
.name = "cpu",
.unmigratable = 1,
};
static Property mb_properties[] = {
DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void mb_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
mcc->parent_realize = dc->realize;
dc->realize = mb_cpu_realizefn;
mcc->parent_reset = cc->reset;
cc->reset = mb_cpu_reset;
if (new_addr < address_space_start) {
error_setg(errp, "can't add memory [0x%" PRIx64 ":0x%" PRIx64
"] at 0x%" PRIx64, new_addr, size, address_space_start);
} else if ((new_addr + size) > address_space_end) {
error_setg(errp, "can't add memory [0x%" PRIx64 ":0x%" PRIx64
"] beyond 0x%" PRIx64, new_addr, size, address_space_end);
}
out:
g_slist_free(list);
return ret;
}
static Property pc_dimm_properties[] = {
DEFINE_PROP_UINT64(PC_DIMM_ADDR_PROP, PCDIMMDevice, addr, 0),
DEFINE_PROP_UINT32(PC_DIMM_NODE_PROP, PCDIMMDevice, node, 0),
DEFINE_PROP_INT32(PC_DIMM_SLOT_PROP, PCDIMMDevice, slot,
PC_DIMM_UNASSIGNED_SLOT),
DEFINE_PROP_LINK(PC_DIMM_MEMDEV_PROP, PCDIMMDevice, hostmem,
TYPE_MEMORY_BACKEND, HostMemoryBackend *),
DEFINE_PROP_END_OF_LIST(),
};
static void pc_dimm_get_size(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
uint64_t value;
MemoryRegion *mr;
PCDIMMDevice *dimm = PC_DIMM(obj);
PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(obj);
uint32_t val, int l)
{
EHCIPCIState *i = DO_UPCAST(EHCIPCIState, pcidev, dev);
bool busmaster;
pci_default_write_config(dev, addr, val, l);
if (!range_covers_byte(addr, l, PCI_COMMAND)) {
return;
}
busmaster = pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_MASTER;
i->ehci.dma = busmaster ? pci_dma_context(dev) : NULL;
}
static Property ehci_pci_properties[] = {
DEFINE_PROP_UINT32("maxframes", EHCIPCIState, ehci.maxframes, 128),
DEFINE_PROP_END_OF_LIST(),
};
static const VMStateDescription vmstate_ehci_pci = {
.name = "ehci",
.version_id = 2,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(pcidev, EHCIPCIState),
VMSTATE_STRUCT(ehci, EHCIPCIState, 2, vmstate_ehci, EHCIState),
VMSTATE_END_OF_LIST()
}
};
static void ehci_class_init(ObjectClass *klass, void *data)
.name = "milkymist-vgafb",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.post_load = vgafb_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, MilkymistVgafbState, R_MAX),
VMSTATE_END_OF_LIST()
}
};
static SysBusDeviceInfo milkymist_vgafb_info = {
.init = milkymist_vgafb_init,
.qdev.name = "milkymist-vgafb",
.qdev.size = sizeof(MilkymistVgafbState),
.qdev.vmsd = &vmstate_milkymist_vgafb,
.qdev.reset = milkymist_vgafb_reset,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("fb_offset", MilkymistVgafbState, fb_offset, 0x0),
DEFINE_PROP_UINT32("fb_mask", MilkymistVgafbState, fb_mask, 0xffffffff),
DEFINE_PROP_END_OF_LIST(),
}
};
static void milkymist_vgafb_register(void)
{
sysbus_register_withprop(&milkymist_vgafb_info);
}
device_init(milkymist_vgafb_register)
vdev->nvectors = proxy->nvectors;
virtio_init_pci(proxy, vdev);
/* make the actual value visible */
proxy->nvectors = vdev->nvectors;
return 0;
}
static PCIDeviceInfo virtio_9p_info = {
.qdev.name = "virtio-9p-pci",
.qdev.size = sizeof(VirtIOPCIProxy),
.init = virtio_9p_init_pci,
.vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET,
.device_id = 0x1009,
.revision = VIRTIO_PCI_ABI_VERSION,
.class_id = 0x2,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2),
DEFINE_VIRTIO_COMMON_FEATURES(VirtIOPCIProxy, host_features),
DEFINE_PROP_STRING("mount_tag", VirtIOPCIProxy, fsconf.tag),
DEFINE_PROP_STRING("fsdev", VirtIOPCIProxy, fsconf.fsdev_id),
DEFINE_PROP_END_OF_LIST(),
}
};
static void virtio_9p_register_devices(void)
{
pci_qdev_register(&virtio_9p_info);
}
device_init(virtio_9p_register_devices)
sysbus_init_mmio(sbd, &s->iomem);
}
static const VMStateDescription vmstate_a9_scu = {
.name = "a9-scu",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(control, A9SCUState),
VMSTATE_UINT32(status, A9SCUState),
VMSTATE_END_OF_LIST()
}
};
static Property a9_scu_properties[] = {
DEFINE_PROP_UINT32("num-cpu", A9SCUState, num_cpu, 1),
DEFINE_PROP_END_OF_LIST(),
};
static void a9_scu_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->props = a9_scu_properties;
dc->vmsd = &vmstate_a9_scu;
dc->reset = a9_scu_reset;
}
static const TypeInfo a9_scu_info = {
.name = TYPE_A9_SCU,
.parent = TYPE_SYS_BUS_DEVICE,
VMSTATE_END_OF_LIST()
}
};
static void arm_mptimer_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
sbc->init = arm_mptimer_init;
}
static DeviceInfo arm_mptimer_info = {
.name = "arm_mptimer",
.size = sizeof(arm_mptimer_state),
.vmsd = &vmstate_arm_mptimer,
.reset = arm_mptimer_reset,
.no_user = 1,
.class_init = arm_mptimer_class_init,
.props = (Property[]) {
DEFINE_PROP_UINT32("num-cpu", arm_mptimer_state, num_cpu, 0),
DEFINE_PROP_END_OF_LIST()
}
};
static void arm_mptimer_register_devices(void)
{
sysbus_register_withprop(&arm_mptimer_info);
}
device_init(arm_mptimer_register_devices)
#include "sysemu/dma.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/ide/internal.h"
#include "sysemu/block-backend.h"
#include "sysemu/blockdev.h"
#include "hw/block/block.h"
#include "sysemu/sysemu.h"
#include "qapi/visitor.h"
/* --------------------------------- */
static char *idebus_get_fw_dev_path(DeviceState *dev);
static Property ide_props[] = {
DEFINE_PROP_UINT32("unit", IDEDevice, unit, -1),
DEFINE_PROP_END_OF_LIST(),
};
static void ide_bus_class_init(ObjectClass *klass, void *data)
{
BusClass *k = BUS_CLASS(klass);
k->get_fw_dev_path = idebus_get_fw_dev_path;
}
static const TypeInfo ide_bus_info = {
.name = TYPE_IDE_BUS,
.parent = TYPE_BUS,
.instance_size = sizeof(IDEBus),
.class_init = ide_bus_class_init,
qemu_add_kbd_event_handler(kbd_event_handler, s);
pc98_kbd_reset(s);
qemu_register_reset(pc98_kbd_reset, s);
return 0;
}
void pc98_kbd_init(void)
{
isa_create_simple("pc98-kbd");
}
static ISADeviceInfo pc98_kbd_info = {
.qdev.name = "pc98-kbd",
.qdev.desc = "NEC PC-9821 Keyboard",
.qdev.size = sizeof(KeyBoardState),
.qdev.vmsd = &vmstate_kbd,
.init = pc98_kbd_initfn,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("irq", KeyBoardState, irq, 1),
DEFINE_PROP_END_OF_LIST (),
},
};
static void pc98_kbd_register(void)
{
isa_qdev_register(&pc98_kbd_info);
}
device_init(pc98_kbd_register)
static void cg3_reset(DeviceState *d)
{
CG3State *s = CG3(d);
/* Initialize palette */
memset(s->r, 0, 256);
memset(s->g, 0, 256);
memset(s->b, 0, 256);
s->dac_state = 0;
s->full_update = 1;
qemu_irq_lower(s->irq);
}
static Property cg3_properties[] = {
DEFINE_PROP_UINT32("vram-size", CG3State, vram_size, -1),
DEFINE_PROP_UINT16("width", CG3State, width, -1),
DEFINE_PROP_UINT16("height", CG3State, height, -1),
DEFINE_PROP_UINT16("depth", CG3State, depth, -1),
DEFINE_PROP_UINT64("prom-addr", CG3State, prom_addr, -1),
DEFINE_PROP_END_OF_LIST(),
};
static void cg3_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = cg3_realizefn;
dc->reset = cg3_reset;
dc->vmsd = &vmstate_cg3;
dc->props = cg3_properties;
/* Legacy helper function. */
void arm_sysctl_init(uint32_t base, uint32_t sys_id, uint32_t proc_id)
{
DeviceState *dev;
dev = qdev_create(NULL, "realview_sysctl");
qdev_prop_set_uint32(dev, "sys_id", sys_id);
qdev_init_nofail(dev);
qdev_prop_set_uint32(dev, "proc_id", proc_id);
sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
}
static SysBusDeviceInfo arm_sysctl_info = {
.init = arm_sysctl_init1,
.qdev.name = "realview_sysctl",
.qdev.size = sizeof(arm_sysctl_state),
.qdev.reset = arm_sysctl_reset,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
DEFINE_PROP_END_OF_LIST(),
}
};
static void arm_sysctl_register_devices(void)
{
sysbus_register_withprop(&arm_sysctl_info);
}
device_init(arm_sysctl_register_devices)
* Implementation of an interface to adjust firmware path
* for the bootindex property handling.
*/
static char *vhost_scsi_get_fw_dev_path(FWPathProvider *p, BusState *bus,
DeviceState *dev)
{
VHostSCSI *s = VHOST_SCSI(dev);
/* format: channel@channel/vhost-scsi@target,lun */
return g_strdup_printf("/channel@%x/%s@%x,%x", s->channel,
qdev_fw_name(dev), s->target, s->lun);
}
static Property vhost_scsi_properties[] = {
DEFINE_PROP_STRING("vhostfd", VHostSCSI, parent_obj.conf.vhostfd),
DEFINE_PROP_STRING("wwpn", VHostSCSI, parent_obj.conf.wwpn),
DEFINE_PROP_UINT32("boot_tpgt", VHostSCSI, parent_obj.conf.boot_tpgt, 0),
DEFINE_PROP_UINT32("num_queues", VHostSCSI, parent_obj.conf.num_queues, 1),
DEFINE_PROP_UINT32("max_sectors", VHostSCSI, parent_obj.conf.max_sectors,
0xFFFF),
DEFINE_PROP_UINT32("cmd_per_lun", VHostSCSI, parent_obj.conf.cmd_per_lun,
128),
DEFINE_PROP_END_OF_LIST(),
};
static void vhost_scsi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(klass);
dc->props = vhost_scsi_properties;
/* One IRQ line for each timer */
sysbus_init_irq(dev, &timer->irq);
ptimer_set_freq(timer->ptimer, unit->freq_hz);
}
memory_region_init_io(&unit->iomem, &grlib_gptimer_ops, unit, "gptimer",
UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers);
sysbus_init_mmio(dev, &unit->iomem);
return 0;
}
static Property grlib_gptimer_properties[] = {
DEFINE_PROP_UINT32("frequency", GPTimerUnit, freq_hz, 40000000),
DEFINE_PROP_UINT32("irq-line", GPTimerUnit, irq_line, 8),
DEFINE_PROP_UINT32("nr-timers", GPTimerUnit, nr_timers, 2),
DEFINE_PROP_END_OF_LIST(),
};
static void grlib_gptimer_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = grlib_gptimer_init;
dc->reset = grlib_gptimer_reset;
dc->props = grlib_gptimer_properties;
}
