Exemple #1
0
CPU_BOOLEAN  CSP_DMA_XferStartExt (CSP_DEV_NBR     ch_nbr,
                                   void           *p_dest,
                                   void           *p_src,                                   
                                   CPU_SIZE_T      xfer_size,
                                   CSP_OPT_FLAGS   opt)

{   
    CSP_DMA_REG     *p_dma_reg;
    CSP_DMA_CH_REG  *p_dma_ch_reg;
    CPU_INT32U       reg_ctrl;    
    CPU_SR_ALLOC();

                                                                /* ------------------ ARGUMENTS CHECKING -------------- */
#if (CSP_CFG_ARG_CHK_EN == DEF_ENABLED)             
    if (ch_nbr > CSP_DMA_CH_MAX_NBR - 1u) {                     /* Invalid channel number?                              */
        return (DEF_FAIL);
    }
                                                                /* Channel not available?                               */
    if (CSP_DMA_ChTbl[ch_nbr].State != CSP_DMA_CH_STATE_ALLOC) {
        return (DEF_FAIL);
    }

    if ((p_dest == (void *)0) ||                                /* Null pointers?                                        */
        (p_src  == (void *)0)) {
        return (DEF_FAIL);
    }    
#endif    

    p_dma_reg    = (CSP_DMA_REG *)CSP_ADDR_DMA_REG;                  
    p_dma_ch_reg = &(p_dma_reg->CHx[ch_nbr]);
    reg_ctrl     = p_dma_ch_reg->Ctrl;

    DEF_BIT_CLR(reg_ctrl, CSP_DMA_MSK_CH_CTRL_XFER_SIZE |
                          CSP_DMA_BIT_CH_CTRL_SI        |
                          CSP_DMA_BIT_CH_CTRL_DI        |
                          CSP_DMA_BIT_CH_CTRL_I);

    DEF_BIT_SET(reg_ctrl, (xfer_size & CSP_DMA_MSK_CH_CTRL_XFER_SIZE));

    if (DEF_BIT_IS_SET(opt, CSP_DMA_OPT_FLAG_XFER_SRC_INC)) {
        DEF_BIT_SET(reg_ctrl, CSP_DMA_BIT_CH_CTRL_SI);
    }
    
    if (DEF_BIT_IS_SET(opt, CSP_DMA_OPT_FLAG_XFER_DEST_INC)) {
        DEF_BIT_SET(reg_ctrl, CSP_DMA_BIT_CH_CTRL_DI);        
    }        
    
    
    CPU_CRITICAL_ENTER();
    p_dma_ch_reg->SrcAddr     = (CPU_INT32U )p_src;
    p_dma_ch_reg->DestAddr    = (CPU_INT32U )p_dest;       
    p_dma_ch_reg->Ctrl        = reg_ctrl;
    DEF_BIT_CLR(p_dma_ch_reg->Cfg, CSP_DMA_BIT_CH_CFG_ITC   | 
                                   CSP_DMA_BIT_CH_CFG_IE);
    DEF_BIT_SET(p_dma_ch_reg->Cfg, CSP_DMA_BIT_CH_CFG_CH_EN); 
    CPU_CRITICAL_EXIT();

    return (DEF_OK);
}
static  void  SerialDrv_TxStart (SERIAL_DEV  *pdev,
                                 SERIAL_ERR  *perr)
{
    SERIAL_DRV_REG  *p_reg;
    SERIAL_DEV_CFG  *p_cfg;
    
    
    p_cfg   = pdev->Dev_Cfg;           
    p_reg   = (SERIAL_DRV_REG *)p_cfg->BaseAddr;
     
                                                                /* Enable the transmit holding register empty interrupt */
    DEF_BIT_SET(p_reg->DLM, SERIAL_DRV_LPCXXXX_BIT_IER_THRE);
    DEF_BIT_SET(p_reg->TER, SERIAL_DRV_LPCXXXX_BIT_TER_TXEN);
   *perr = SERIAL_ERR_NONE;
}
Exemple #3
0
void  CSP_TmrIntClr (CSP_DEV_NBR tmr_nbr)
{
    CSP_TMR_REG  *p_tmr_reg;
    CSP_DEV_NBR   match_nbr;
    CPU_INT32U    reg_msk;
    CPU_INT32U    reg_stat;
    CPU_INT32U    reg_clr;
    

#if (CSP_CFG_ARG_CHK_EN == DEF_ENABLED)         
    if (tmr_nbr > CSP_TMR_NBR_03) {
        return;
    }
#endif
    
    p_tmr_reg = (CSP_TMR_REG *)CSP_TmrAddrTbl[tmr_nbr];
    reg_clr   = DEF_BIT_NONE;
    reg_msk   = p_tmr_reg->MCR;
    reg_stat  = p_tmr_reg->IR;
    
    for (match_nbr =  0; match_nbr <= CSP_TMR_MATCH_NBR_03; match_nbr++) {
        if ((DEF_BIT_IS_SET(reg_msk,  CSP_TMR_BIT_MCR_MRIx(match_nbr)) == DEF_YES) &&
            (DEF_BIT_IS_SET(reg_stat, DEF_BIT(match_nbr))              == DEF_YES)) {
            DEF_BIT_SET(reg_clr, DEF_BIT(match_nbr));
        }
    }
        
    p_tmr_reg->IR = reg_clr;
}
// LED initialization
void  BSP_LED_Init (void)
{
                                                                /* Enable GPIO clock                                    */
    DEF_BIT_SET(BSP_SYS_REG_RCGCGPIO, (BSP_RCGCGPIO_PORT_F));
	
		DEF_BIT_SET(BSP_SYS_REG_GPIOHBCTL, BSP_GPIOHBCTL_PORT_F); // ahb bus
	
                                                                /* Set PQ7(GREEN) and PQ4(BLUE) pins as output          */
    BSP_GPIO_REG_DIR(BSP_GPIO_PORTF) = (BSP_LED_TRICOLOR_GREEN |
                                        BSP_LED_TRICOLOR_BLUE | BSP_LED_TRICOLOR_RED);

                                                                /* En PQ7(GREEN) and PQ4(BLUE) pins digital functions   */
    BSP_GPIO_REG_DEN(BSP_GPIO_PORTF) = (BSP_LED_TRICOLOR_GREEN |
                                        BSP_LED_TRICOLOR_BLUE | BSP_LED_TRICOLOR_RED);

    //BSP_LED_Off(0);                                             /* Turn OFF LEDs.                                       */

}
static  void  SerialDrv_RxStart (SERIAL_DEV  *pdev,
                                 SERIAL_ERR  *perr)
{
    SERIAL_DRV_REG  *p_reg;
    SERIAL_DEV_CFG  *p_cfg;
    
    
    p_cfg = pdev->Dev_Cfg;           
    p_reg = (SERIAL_DRV_REG *)p_cfg->BaseAddr;    
                                                                /* Enable the Receive Data available & RX line Status.  */
    DEF_BIT_SET(p_reg->DLM, SERIAL_DRV_LPCXXXX_BIT_IER_RBR | SERIAL_DRV_LPCXXXX_BIT_IER_RX_LINE);

   *perr = SERIAL_ERR_NONE;
}
// LED 7 Turn on Function
void  BSP_LED_7_COLORS_SET (CPU_INT08U  led)
{
    switch (led) {
        case 0:
             DEF_BIT_SET(BSP_GPIO_REG_DATA(BSP_GPIO_PORTF),
                         BSP_LED_TRICOLOR_RED);
				

				break;
				
				
				case 1:
             DEF_BIT_SET(BSP_GPIO_REG_DATA(BSP_GPIO_PORTF),
                         BSP_LED_TRICOLOR_BLUE);
      		
				break;
				
				case 2:
             DEF_BIT_SET(BSP_GPIO_REG_DATA(BSP_GPIO_PORTF),
                         BSP_LED_TRICOLOR_GREEN);
            				
				break;
				
				case 3:
            DEF_BIT_SET(BSP_GPIO_REG_DATA(BSP_GPIO_PORTF),
                         (BSP_LED_TRICOLOR_RED | BSP_LED_TRICOLOR_BLUE));
								
				break;


        case 4:
             DEF_BIT_SET(BSP_GPIO_REG_DATA(BSP_GPIO_PORTF),
                         (BSP_LED_TRICOLOR_RED | BSP_LED_TRICOLOR_GREEN));
									
				break;
				
				case 5:
             DEF_BIT_SET(BSP_GPIO_REG_DATA(BSP_GPIO_PORTF),
                         (BSP_LED_TRICOLOR_GREEN| BSP_LED_TRICOLOR_BLUE));
        
				break;
				
				case 6:
             DEF_BIT_SET(BSP_GPIO_REG_DATA(BSP_GPIO_PORTF),
                         (BSP_LED_TRICOLOR_RED | BSP_LED_TRICOLOR_BLUE|BSP_LED_TRICOLOR_GREEN));
			
						break;

       default:
             break;
    }
}
Exemple #7
0
void  BSP_Init (void)
{
    CPU_INT16U    reg_to;
    CPU_INT32U    reg_val;
    CPU_SR_ALLOC();

                                                                /* ---------------- CLOCK INITIALIZATION -------------- */
    BSP_REG_FLASHCFG = BSP_MSK_FLASHCFG_CLK_6                   /* Set 6 cycles to acces the Flash memory.              */
                     | BSP_MSK_FLASHCFG_RST_VAL;
                                                                /* ----------- MAIN OSCILLATOR INITIALIZATION --------- */
    DEF_BIT_CLR(BSP_REG_SCS, BSP_BIT_SCS_OSCRANGE);             /* Set the main oscillator range                        */


    reg_to = BSP_VAL_MAX_TO;

    DEF_BIT_SET(BSP_REG_SCS, BSP_BIT_SCS_OSCEN);                /* Enable the Main Oscillator                           */

                                                                /* Wait until the main oscillator is enabled.           */
    while (DEF_BIT_IS_CLR(BSP_REG_SCS, BSP_BIT_SCS_OSCSTAT) &&
          (reg_to > 0u)) {
        reg_to--;
    }

    if (reg_to == 0u) {                                         /* Configuration fail                                   */
        return;
    }

    BSP_REG_PCLKSEL0 = DEF_BIT_NONE;                            /* All peripheral clock runrs at CPU_Clk / 4 = 25 Mhz   */
    BSP_REG_PCLKSEL1 = DEF_BIT_NONE;

                                                                /* ------------------ PLL0 CONFIGURATION -------------- */

    reg_val  = (((25u - 1u) <<  0u) & BSP_MSK_PLLCFG0_MSEL)     /* PLL0 values M = 25 & N = 2 (see note #6)             */
             | ((( 2u - 1u) << 16u) & BSP_MSK_PLLCFG0_NSEL);
                                                                /* 1. Disconnect PLL0 with one feed sequence if PLL ... */
                                                                /* ... already connected.                               */
    if (DEF_BIT_IS_SET(BSP_REG_PLLSTAT(0u), BSP_BIT_PLLSTAT_PLLC0_STAT)) {
        DEF_BIT_CLR(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLC);
        BSP_PLL_FEED_SEQ(0u);
    }

    DEF_BIT_CLR(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLE);     /* 2. Disable PLL0 with one feed sequence               */
    BSP_PLL_FEED_SEQ(0u);

    BSP_REG_CCLKCFG   = (1u - 1u);                              /* 3. Change the CPU clock divider setting to speed ... */
                                                                /* ... operation without PLL0                           */

    BSP_REG_CLKSRCSEL = BSP_BIT_CLKSRCSEL_MAIN;                 /* 4. Select the main osc. as the PLL0 clock source     */

    BSP_REG_PLLCFG(0u) = reg_val;                               /* 5. Write to the PLLCFG and make it effective with... */
    BSP_PLL_FEED_SEQ(0u)                                        /* ... one one feed sequence                            */

    DEF_BIT_SET(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLE);     /* 6. Enable PLL0 with one feed sequence                */
    BSP_PLL_FEED_SEQ(0u);

    BSP_REG_CCLKCFG   = (3u - 1u);                              /* 7. Change the CPU clock divider setting for ...      */
                                                                /* ... operation with PLL0                              */

    reg_to = BSP_VAL_MAX_TO;                                    /* 8. Wait for PLL0 to achieve lock by monitoring ...   */
                                                                /* ... the PLOCK0 bit in the PLL0STAT                   */
    while (DEF_BIT_IS_CLR(BSP_REG_PLLSTAT(0u), BSP_BIT_PLLSTAT_PLOCK0) &&
          (reg_to > 0u)) {
        reg_to--;
    }

    if (reg_to == 0u) {
        return;
    }

    DEF_BIT_SET(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLC);     /* 9. Connect PLL0 with one feed sequence               */
    BSP_PLL_FEED_SEQ(0u);
                                                                /* ------------------ PLL1 CONFIGURATION -------------- */
    reg_val  = (((4u - 1u)  <<  0u) & BSP_MSK_PLLCFG1_MSEL)     /* PLL1 values M = 4; P = 2 coded as '01' (see note #6) */
             | (((0x01u   ) <<  5u) & BSP_MSK_PLLCFG1_NSEL);

    DEF_BIT_CLR(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLC);     /* 1. Disconnect PLL1 with one feed sequence            */
    BSP_PLL_FEED_SEQ(1u);

    DEF_BIT_CLR(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLE);     /* 2. Disable PLL1 with one feed sequence               */
    BSP_PLL_FEED_SEQ(1u);

    BSP_REG_PLLCFG(1u) = reg_val;                               /* 3. Write to the PLLCFG and make it effective with... */
    BSP_PLL_FEED_SEQ(1u);                                       /* ... one one feed sequence                            */

    DEF_BIT_SET(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLE);     /* 4. Enable PLL1 with one feed sequence                */
    BSP_PLL_FEED_SEQ(1u);

    reg_to = BSP_VAL_MAX_TO;                                    /* 5. Wait for PLL1 to achieve lock by monitoring ...   */
                                                                /* ... the PLOCK1 bit in the PLL1STAT                   */
    while (DEF_BIT_IS_CLR(BSP_REG_PLLSTAT(1u), BSP_BIT_PLLSTAT_PLOCK1) &&
          (reg_to > 0u)) {
        reg_to--;
    }

    if (reg_to == 0u) {
        return;
    }

    DEF_BIT_SET(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLC);     /* 6. Connect PLL1 with one feed sequence               */
    BSP_PLL_FEED_SEQ(1u);


    BSP_REG_FLASHCFG = BSP_MSK_FLASHCFG_CLK_5                   /* Set 5 cycles to acces the Flash memory.              */
                     | BSP_MSK_FLASHCFG_RST_VAL;

    CSP_GPIO_Cfg(CSP_GPIO_PORT_NBR_00,
                 BSP_GPIO0_LED2,
                 CSP_GPIO_DIR_OUT,
                 CSP_GPIO_FLAG_MODE_NONE,
                 DEF_NO,
                 0u,
                 CSP_GPIO_FNCT_00);

    CSP_GPIO_Cfg(CSP_GPIO_PORT_NBR_01,
                 BSP_GPIO1_LED1,
                 CSP_GPIO_DIR_OUT,
                 CSP_GPIO_FLAG_MODE_NONE,
                 DEF_NO,
                 0u,
                 CSP_GPIO_FNCT_00);

    CSP_GPIO_Cfg(CSP_GPIO_PORT_NBR_00,
                 BSP_GPIO0_BUT1,
                 CSP_GPIO_DIR_IN,
                 CSP_GPIO_FLAG_MODE_NONE,
                 DEF_NO,
                 0u,
                 CSP_GPIO_FNCT_00);

    CSP_GPIO_Cfg(CSP_GPIO_PORT_NBR_02,
                 BSP_GPIO2_BUT2,
                 CSP_GPIO_DIR_IN,
                 CSP_GPIO_FLAG_MODE_NONE,
                 DEF_NO,
                 0u,
                 CSP_GPIO_FNCT_00);

    BSP_LED_Off(0);

    CSP_GPIO_Cfg( CSP_GPIO_PORT_NBR_02,
                 (BSP_GPIO2_JOY_RIGHT |
                  BSP_GPIO2_JOY_DOWN  |
                  BSP_GPIO2_JOY_LEFT  |
                  BSP_GPIO2_JOY_RIGHT),
                  CSP_GPIO_DIR_IN,
                  CSP_GPIO_FLAG_MODE_NONE,
                  DEF_NO,
                  0u,
                  CSP_GPIO_FNCT_00);

    CSP_GPIO_Cfg( CSP_GPIO_PORT_NBR_00,
                  BSP_GPIO0_JOY_CENTER,
                  CSP_GPIO_DIR_IN,
                  CSP_GPIO_FLAG_MODE_NONE,
                  DEF_NO,
                  0u,
                  CSP_GPIO_FNCT_00);

    CSP_IntInit();
    CSP_IntDisAll(CSP_INT_CTRL_NBR_MAIN);
}
Exemple #8
0
CPU_BOOLEAN  CSP_DMA_XferAsyncStartExt (CSP_DEV_NBR            ch_nbr, 
                                        void                  *p_dest,                                       
                                        void                  *p_src,
                                        CPU_SIZE_T             xfer_size,
                                        CSP_DMA_CALLBACK_PTR   callback,
                                        void                  *p_arg,
                                        CSP_OPT_FLAGS          opt)
{
    CSP_DMA_REG     *p_dma_reg;
    CSP_DMA_CH_REG  *p_dma_ch_reg; 
    CSP_DMA_CH      *p_dma_ch;
    CPU_INT32U       reg_ctrl;
    CPU_SR_ALLOC();
    
#if (CSP_CFG_ARG_CHK_EN == DEF_ENABLED)             
    if (ch_nbr > CSP_DMA_CH_MAX_NBR - 1u) {                     /* Invalid channel number?                              */
        return (DEF_FAIL);
    }
                                                                /* Channel not available?                               */
    if (CSP_DMA_ChTbl[ch_nbr].State != CSP_DMA_CH_STATE_ALLOC) {
        return (DEF_FAIL);
    }
    
    if (callback == (CSP_DMA_CALLBACK_PTR )0) {
        return (DEF_FAIL);
    }
    
    if ((p_dest  == (void *)0) ||
        (p_src   == (void *)0)) {
        return (DEF_FAIL);
    }
#endif    

    p_dma_reg    = (CSP_DMA_REG *)CSP_ADDR_DMA_REG;                  
    p_dma_ch_reg = &(p_dma_reg->CHx[ch_nbr]);
    p_dma_ch     = &(CSP_DMA_ChTbl[ch_nbr]);    
    reg_ctrl     = p_dma_ch_reg->Ctrl;
    
    DEF_BIT_CLR(reg_ctrl, CSP_DMA_MSK_CH_CTRL_XFER_SIZE |       /* Clears the xfer size mask.                           */
                          CSP_DMA_BIT_CH_CTRL_SI        |       /* Clears the source increment flag.                    */
                          CSP_DMA_BIT_CH_CTRL_DI);              /* Clears the destination increment flag.               */

    DEF_BIT_SET(reg_ctrl, xfer_size & CSP_DMA_MSK_CH_CTRL_XFER_SIZE);
    DEF_BIT_SET(reg_ctrl, CSP_DMA_BIT_CH_CTRL_I);

    if (DEF_BIT_IS_SET(opt, CSP_DMA_OPT_FLAG_XFER_SRC_INC)) {
        DEF_BIT_SET(reg_ctrl, CSP_DMA_BIT_CH_CTRL_SI);
    }
    
    if (DEF_BIT_IS_SET(opt, CSP_DMA_OPT_FLAG_XFER_DEST_INC)) {
        DEF_BIT_SET(reg_ctrl, CSP_DMA_BIT_CH_CTRL_DI);        
    }        
        
    CPU_CRITICAL_ENTER();    
    p_dma_ch_reg->SrcAddr     = (CPU_INT32U )p_src;
    p_dma_ch_reg->DestAddr    = (CPU_INT32U )p_dest;       
    p_dma_ch->CallBackFnctPtr = callback;
    p_dma_ch->CallBackArgPtr  = p_arg;    
    p_dma_ch_reg->Ctrl        = reg_ctrl;

    DEF_BIT_SET(p_dma_ch_reg->Cfg, CSP_DMA_BIT_CH_CFG_ITC   | 
                                   CSP_DMA_BIT_CH_CFG_IE);     
    DEF_BIT_SET(p_dma_ch_reg->Cfg, CSP_DMA_BIT_CH_CFG_CH_EN);
    
    CPU_CRITICAL_EXIT();
        
    return (DEF_OK);
}
Exemple #9
0
CPU_BOOLEAN  CSP_DMA_CH_CfgExt (CSP_DEV_NBR   ch_nbr,
                                CSP_OPT       xfer_type,
                                CSP_OPT       src_burst_size,
                                CSP_OPT       src_width,
                                CSP_OPT       dest_burst_size,
                                CSP_OPT       dest_width,
                                CSP_DEV_NBR   src_req,
                                CSP_DEV_NBR   dest_req)
                                

{   CSP_DMA_REG     *p_dma_reg;
    CSP_DMA_CH_REG  *p_dma_ch_reg;
    CPU_INT32U       reg_cfg;
    CPU_INT32U       reg_ctrl;
    CPU_INT32U       reg_val;
    CPU_SR_ALLOC();
    
                                                                /* ------------------ ARGUMENTS CHECKING -------------- */
#if (CSP_CFG_ARG_CHK_EN == DEF_ENABLED)
    if (ch_nbr > CSP_DMA_CH_MAX_NBR - 1u) {                     /* Invalid channel number?                              */
        return (DEF_FAIL);
    }
                                                                /* Channel not available?                               */
    if (CSP_DMA_ChTbl[ch_nbr].State != CSP_DMA_CH_STATE_ALLOC) {
        return (DEF_FAIL);
    }
    
    if ((src_width != CPU_WORD_SIZE_08) &&                      /* Check src width parameter.                           */
        (src_width != CPU_WORD_SIZE_16) &&
        (src_width != CPU_WORD_SIZE_32)) {
        return (DEF_FAIL);
    }

    if ((dest_width != CPU_WORD_SIZE_08) &&                     /* Check src width parameter.                           */
        (dest_width != CPU_WORD_SIZE_16) &&
        (dest_width != CPU_WORD_SIZE_32)) {
        return (DEF_FAIL);
    }
#endif
                                                                /* Channel configuration.                               */
    reg_cfg  = DEF_BIT_NONE; 
    reg_ctrl = DEF_BIT_NONE;

    if (src_burst_size == 255u) {                               /* Set the source/destination burst size.               */
       reg_val   = 7u;
    } else if (src_burst_size >= 4u) {
        reg_val  = (DEF_INT_32_NBR_BITS - CPU_CntLeadZeros(src_burst_size) - 2u);        
    } else {
        reg_val  = DEF_BIT_NONE; 
    }
            
    DEF_BIT_SET(reg_ctrl, reg_val << 12u);

    if (dest_burst_size == 255u) {
       reg_val  = 7u;
    } else if (dest_burst_size >= 4u) {
        reg_val = (DEF_INT_32_NBR_BITS - CPU_CntLeadZeros(dest_burst_size) - 2u);        
    } else {
        reg_val = DEF_BIT_NONE;
    }

    DEF_BIT_SET(reg_ctrl, reg_val           << 15u);
    DEF_BIT_SET(reg_ctrl, (src_width  - 1u) << 18u);
    DEF_BIT_SET(reg_ctrl, (dest_width - 1u) << 21u);
    


                                                                /* Set the transfer type.                               */
    switch (xfer_type) {
        case CSP_DMA_XFER_TYPE_MEM_TO_PER:
             DEF_BIT_SET(reg_cfg, CSP_DMA_BIT_CH_CFG_XFER_MEM_TO_PER);              
             break;

        case CSP_DMA_XFER_TYPE_MEM_TO_MEM:
             DEF_BIT_SET(reg_cfg, CSP_DMA_BIT_CH_CFG_XFER_MEM_TO_MEM);              
             break;

        case CSP_DMA_XFER_TYPE_PER_TO_MEM:
             DEF_BIT_SET(reg_cfg, CSP_DMA_BIT_CH_CFG_XFER_PER_TO_MEM);              
             break;

        case CSP_DMA_XFER_TYPE_PER_TO_PER:
             DEF_BIT_SET(reg_cfg, CSP_DMA_BIT_CH_CFG_XFER_PER_TO_PER);
             break;
   
        default:
             return (DEF_FAIL);
    }
                                                                /* Configure source request signal  (see note #3)       */
                                                                /* ... transfer from peripheral?                        */
    if (((xfer_type == CSP_DMA_XFER_TYPE_PER_TO_MEM       )  || 
         (xfer_type == CSP_DMA_XFER_TYPE_PER_TO_PER       ))) {    
        
        if (src_req < CSP_DMA_XFER_PER_REQ_UART_00_TX) {
            ;    
        } else if (src_req < CSP_DMA_XFER_PER_REQ_TMR_00_MATCH_0) {
            CPU_CRITICAL_ENTER();
            DEF_BIT_CLR(CSP_DMA_REG_REQ_SEL, DEF_BIT(src_req - CSP_DMA_XFER_PER_REQ_UART_00_TX));
            CPU_CRITICAL_EXIT();
        } else {
            src_req -= CSP_DMA_XFER_PER_REQ_UART_00_TX;
   
            CPU_CRITICAL_ENTER();
            DEF_BIT_SET(CSP_DMA_REG_REQ_SEL, DEF_BIT(src_req - CSP_DMA_XFER_PER_REQ_UART_00_TX)); 
            CPU_CRITICAL_EXIT();
        }
        DEF_BIT_SET(reg_cfg, (src_req & CSP_DMA_MSK_CH_CFG_PER_REQ) << 1u);                
    }
    
    
    if (((xfer_type  == CSP_DMA_XFER_TYPE_MEM_TO_PER       )  || 
         (xfer_type  == CSP_DMA_XFER_TYPE_PER_TO_PER       ))) {

        if (dest_req < CSP_DMA_XFER_PER_REQ_UART_00_TX) {
            ;    
        } else if (dest_req < CSP_DMA_XFER_PER_REQ_TMR_00_MATCH_0) {
            CPU_CRITICAL_ENTER();
            DEF_BIT_CLR(CSP_DMA_REG_REQ_SEL, DEF_BIT(dest_req - CSP_DMA_XFER_PER_REQ_UART_00_TX));
            CPU_CRITICAL_EXIT();
        } else {
            dest_req -= CSP_DMA_XFER_PER_REQ_UART_00_TX;

            CPU_CRITICAL_ENTER();            
            DEF_BIT_SET(CSP_DMA_REG_REQ_SEL, DEF_BIT(dest_req - CSP_DMA_XFER_PER_REQ_UART_00_TX)); 
            CPU_CRITICAL_EXIT();
        }
             
        DEF_BIT_SET(reg_cfg, (dest_req & CSP_DMA_MSK_CH_CFG_PER_REQ) << 6u);        
    }

    p_dma_reg    = (CSP_DMA_REG *)CSP_ADDR_DMA_REG;                  
    p_dma_ch_reg = &(p_dma_reg->CHx[ch_nbr]);
    
    CPU_CRITICAL_ENTER();
    p_dma_ch_reg->Cfg      = (CPU_INT32U)reg_cfg;   
    p_dma_ch_reg->Ctrl     = (CPU_INT32U)reg_ctrl;       
    CPU_CRITICAL_EXIT();

    return (DEF_OK);
}
static  void  SerialDrv_LPC3xxx_Open (SERIAL_DEV     *pdev,
                                      SERIAL_IF_CFG  *pcfg,
                                      SERIAL_ERR    *perr)
{

    CPU_INT32U       br_div;                                    /* Baud Rate divider.                                   */
    CPU_BOOLEAN      flow_ctrl;
    CPU_INT32U       per_clk_freq;                              /* Peripheral Clock frequency.                          */
    CPU_INT32U       reg_val;
    SERIAL_DRV_REG  *p_reg;
    SERIAL_DEV_CFG  *p_cfg;
    
    
    p_cfg  = pdev->Dev_Cfg;        
                                                                /* -------------- BAUD RATE CALCULATION --------------- */
    per_clk_freq  = p_cfg->BSP_API->ClkFreqGet();               /* Get the UART peripheral clock                        */

    if (pcfg->Baudrate > per_clk_freq) {                        /* If baud rate higher than peripheral clock?           */
        *perr =  SERIAL_ERR_DRV_INVALID;
    }

    br_div         =  (((per_clk_freq) / (8u * pcfg->Baudrate)) + 1u) / 2u;
                                                                /* ---------------- UART LINE CONFIGUARTION ----------- */
    reg_val = DEF_BIT_NONE;
    
    switch (pcfg->DataBits) {                                   /* ... World Length Configuration.                      */
        case SERIAL_DATABITS_5:
             reg_val = SERIAL_DRV_LPCXXXX_BIT_LCR_WLS_05;
             break;

        case SERIAL_DATABITS_6:
             reg_val =SERIAL_DRV_LPCXXXX_BIT_LCR_WLS_06;
             break;
             
        case SERIAL_DATABITS_7:
             reg_val = SERIAL_DRV_LPCXXXX_BIT_LCR_WLS_07;
             break;

        case SERIAL_DATABITS_8:
             reg_val = SERIAL_DRV_LPCXXXX_BIT_LCR_WLS_08;
             break;
       
        default:
             *perr = SERIAL_ERR_DRV_INVALID;
             return;             
    }
    
    switch (pcfg->StopBits) {                                   /* ... Stop Bits configuration.                         */
        case SERIAL_STOPBITS_1:
             break;

        case SERIAL_STOPBITS_1_5:
             if (pcfg->DataBits == (CPU_INT08U)SERIAL_DATABITS_5) {
                 DEF_BIT_SET(reg_val, SERIAL_DRV_LPCXXXX_BIT_LCR_STOP_BIT);
             } else {             
                 *perr = SERIAL_ERR_DRV_INVALID;
                  return;
             }
             break;

        case SERIAL_STOPBITS_2:
             DEF_BIT_SET(reg_val, SERIAL_DRV_LPCXXXX_BIT_LCR_STOP_BIT);
             break;

        default:
            *perr = SERIAL_ERR_DRV_INVALID;
            return; 
    }
    
    switch (pcfg->Parity) {
        case SERIAL_PARITY_ODD:
             DEF_BIT_SET(reg_val, SERIAL_DRV_LPCXXXX_BIT_LCR_PAR_EN | 
                                  SERIAL_DRV_LPCXXXX_BIT_LCR_PAR_ODD);
             break;


        case SERIAL_PARITY_EVEN:
             DEF_BIT_SET(reg_val, SERIAL_DRV_LPCXXXX_BIT_LCR_PAR_EN | 
                                  SERIAL_DRV_LPCXXXX_BIT_LCR_PAR_ODD);
             break;


        case SERIAL_PARITY_MARK:
             DEF_BIT_SET(reg_val, SERIAL_DRV_LPCXXXX_BIT_LCR_PAR_EN | 
                                  SERIAL_DRV_LPCXXXX_BIT_LCR_PAR_FORCED_ONE);
             break;

        case SERIAL_PARITY_SPACE:
             DEF_BIT_SET(reg_val, SERIAL_DRV_LPCXXXX_BIT_LCR_PAR_EN | 
                                  SERIAL_DRV_LPCXXXX_BIT_LCR_PAR_FORCED_ZERO);
             break;

        case SERIAL_PARITY_NONE:
             break;
             
        default:
            *perr = SERIAL_ERR_DRV_INVALID;
             return; 
    }

    p_reg = (SERIAL_DRV_REG *)p_cfg->BaseAddr;

    p_cfg->BSP_API->ClkEn(perr);                                /* En dev-specific HW clk.                              */
    if (*perr != SERIAL_ERR_NONE) {
         return;
    }
        
    p_reg->LCR = DEF_BIT_NONE;                                  /* Disable Interrupts.                                  */
    p_reg->DLM = DEF_BIT_NONE;

    p_reg->LCR = reg_val;                                       /* Configure the Line control register.                 */
             
                                                                /* Baud Rate configuration ...                          */
    DEF_BIT_SET(p_reg->LCR, SERIAL_DRV_LPCXXXX_BIT_LCR_DLAB);   /* ... Enable DLAB bit (access Divisor Latch register ) */
    p_reg->RBR   = (br_div      ) & DEF_INT_08_MASK;            /* ... Set LSB Divisor Latch                            */
    p_reg->DLM   = (br_div >> 8u) & DEF_INT_08_MASK;            /* ... Set MSB Divisor Latch                            */
    DEF_BIT_CLR(p_reg->LCR, SERIAL_DRV_LPCXXXX_BIT_LCR_DLAB);   /* ... Disable DLAB bit                                 */    
    
                                                                /* --------------- FIFOs CONFIGURATION  --------------- */
    p_reg->IIR   = SERIAL_DRV_LPCXXXX_BIT_FCR_RX_FIFO_RST       /* Reset the TX and RX FIFOs. FIFO is disabled          */
                 | SERIAL_DRV_LPCXXXX_BIT_FCR_TX_FIFO_RST;
        
                   
    switch (pcfg->FlowCtrl) {
        case SERIAL_FLOW_CTRL_HARDWARE:
             flow_ctrl  = DEF_ENABLED;
             break;

        case SERIAL_FLOW_CTRL_NONE:
        default:
             flow_ctrl  = DEF_DISABLED;
             break;
    }

    p_cfg->BSP_API->CfgGPIO(flow_ctrl, perr);                   /* Cfg dev-specific GPIO.                               */
    if (*perr != SERIAL_ERR_NONE) {
         return;
    }
    p_cfg->BSP_API->CfgInt(pdev, perr);                         /* Cfg dev-specific int.                                */
}
static  void  SerialDrv_Open (SERIAL_DEV     *pdev,
                              SERIAL_IF_CFG  *pcfg,
                              SERIAL_ERR     *perr)
{

    CPU_INT32U       br_div_num;                                /* Baud Rate divider numerator.                         */
    CPU_INT32U       br_div_den;                                /* Baud Rate divider denominator.                       */   
    CPU_INT32U       br_div;                                    /* Baud Rate divider.                                   */
    CPU_INT32U       br_div_tmp;                                /* Baud Rate divider temporal.                          */    
    CPU_INT32U       br_val_err;                                /* Baud Rate value error.                               */
    CPU_INT32U       br_val_err_max;                            /* Baud Rate Maximum error.                             */    
    CPU_INT32U       br_val;                                    /* Baud Rate Maximum error.                             */    
    CPU_BOOLEAN      div_found;
    CPU_INT08U       fp_div;                                    /* Fractional part multiplier.                          */
    CPU_INT08U       fp_div_ix;                                 /* Fractional part multiplier index.                    */
    CPU_BOOLEAN      flow_ctrl;
    CPU_INT32U       per_clk_freq;                              /* Peripheral Clock frequency.                          */
    CPU_INT32U       reg_val;
    SERIAL_DRV_REG  *p_reg;
    SERIAL_DEV_CFG  *p_cfg;
    
    
    p_cfg         = pdev->Dev_Cfg;
                                                                /* -------------- BAUD RATE CALCULATION --------------- */
    per_clk_freq  = p_cfg->BSP_API->ClkFreqGet();               /* Get the UART peripheral clock                        */

    if (pcfg->Baudrate > per_clk_freq) {                        /* If baud rate higher than peripheral clock?           */
        *perr =  SERIAL_ERR_DRV_INVALID;
    }
    
    br_div_num     = (per_clk_freq);
    br_div_den     = (pcfg->Baudrate * 16u);
    div_found      = DEF_NO;
    br_val_err     = DEF_INT_32U_MAX_VAL;
    br_div_tmp     = (br_div_num / br_div_den); 
    br_div         = 0u;
    br_val_err_max = DEF_INT_32U_MAX_VAL;
    fp_div         = 0u;

    if ((br_div_tmp != 0u             ) &&                     /* If the baud rate divider is valid.                   */
        (br_div_tmp <= DEF_INT_16_MASK)) {
        br_div    = br_div_tmp;                                /* ... store the result.                                */
        fp_div    = 0u; 
        div_found = DEF_YES;
        br_val    = (br_div_num / (16u * br_div));
        if (br_val > pcfg->Baudrate) {
            br_val_err_max = br_val - pcfg->Baudrate;
        } else {
            br_val_err_max = pcfg->Baudrate - br_val;        
        }
    }
    
    if ((br_val_err_max != 0u     ) ||
        (div_found      != DEF_YES)) {
    
        br_div_num *= SERIAL_DRV_LPCXXXX_VAL_MULVAL;            /* Pre-calculate the numerator                          */
                                                                /* Try from divider 1 to maximum divider                */
        for (fp_div_ix = 1u; fp_div_ix <= SERIAL_DRV_LPCXXXX_VAL_DIVAL_MAX_IX; fp_div_ix++) {
            br_div_den = (pcfg->Baudrate * 16u)
                       * (SERIAL_DRV_LPCXXXX_VAL_MULVAL + (CPU_INT32U)fp_div_ix);
            br_div_tmp = (br_div_num / br_div_den);             /* Calculate the baud rate divider                      */
            
            if ((br_div_tmp != 0u             ) &&              /* Check if the baud rate is valid                      */
                (br_div_tmp <= DEF_INT_16_MASK)) {
                                                                /* Calculate the remainer                               */
                br_div_den = ((br_div_tmp * 16u)
                           * ((CPU_INT32U)fp_div_ix + SERIAL_DRV_LPCXXXX_VAL_MULVAL));
                br_val     = (br_div_num / br_div_den);
                                                                /* Calculate the error between the found value and ...  */
                                                                /* ... and the expected value.                          */                
                if (br_val > pcfg->Baudrate) {
                    br_val_err = br_val - pcfg->Baudrate;
                } else {
                    br_val_err = pcfg->Baudrate - br_val;        
                }
                
                if (br_val_err < br_val_err_max) {              /* If the value found reduces the error ...             */
                    br_div         = br_div_tmp;                /* ... Store the result to be written to the registers  */
                    fp_div         = fp_div_ix;
                    div_found      = DEF_YES;
                    br_val_err_max = br_val_err;
                }
            }
        }                
    }
    
    if (div_found == DEF_NO) {
       *perr = SERIAL_ERR_DRV_INVALID;
        return;
    }
 
                                                                /* ---------------- UART LINE CONFIGUARTION ----------- */
    reg_val = DEF_BIT_NONE;
    
    switch (pcfg->DataBits) {                                   /* ... World Length Configuration.                      */
        case SERIAL_DATABITS_5:
             reg_val = SERIAL_DRV_LPCXXXX_BIT_LCR_WLS_05;
             break;

        case SERIAL_DATABITS_6:
             reg_val =SERIAL_DRV_LPCXXXX_BIT_LCR_WLS_06;
             break;
             
        case SERIAL_DATABITS_7:
             reg_val = SERIAL_DRV_LPCXXXX_BIT_LCR_WLS_07;
             break;

        case SERIAL_DATABITS_8:
             reg_val = SERIAL_DRV_LPCXXXX_BIT_LCR_WLS_08;
             break;
       
        default:
             *perr = SERIAL_ERR_DRV_INVALID;
             return;             
    }
    
    switch (pcfg->StopBits) {                                   /* ... Stop Bits configuration.                         */
        case SERIAL_STOPBITS_1:
             break;

        case SERIAL_STOPBITS_1_5:
             if (pcfg->DataBits == (CPU_INT08U)SERIAL_DATABITS_5) {
                 DEF_BIT_SET(reg_val, SERIAL_DRV_LPCXXXX_BIT_LCR_STOP_BIT);
             } else {             
                 *perr = SERIAL_ERR_DRV_INVALID;
                  return;
             }
             break;

        case SERIAL_STOPBITS_2:
             DEF_BIT_SET(reg_val, SERIAL_DRV_LPCXXXX_BIT_LCR_STOP_BIT);
             break;

        default:
            *perr = SERIAL_ERR_DRV_INVALID;
            return; 
    }
    
    switch (pcfg->Parity) {
        case SERIAL_PARITY_ODD:
             DEF_BIT_SET(reg_val, SERIAL_DRV_LPCXXXX_BIT_LCR_PAR_EN | 
                                  SERIAL_DRV_LPCXXXX_BIT_LCR_PAR_ODD);
             break;


        case SERIAL_PARITY_EVEN:
             DEF_BIT_SET(reg_val, SERIAL_DRV_LPCXXXX_BIT_LCR_PAR_EN | 
                                  SERIAL_DRV_LPCXXXX_BIT_LCR_PAR_ODD);
             break;


        case SERIAL_PARITY_MARK:
             DEF_BIT_SET(reg_val, SERIAL_DRV_LPCXXXX_BIT_LCR_PAR_EN | 
                                  SERIAL_DRV_LPCXXXX_BIT_LCR_PAR_FORCED_ONE);
             break;

        case SERIAL_PARITY_SPACE:
             DEF_BIT_SET(reg_val, SERIAL_DRV_LPCXXXX_BIT_LCR_PAR_EN | 
                                  SERIAL_DRV_LPCXXXX_BIT_LCR_PAR_FORCED_ZERO);
             break;

        case SERIAL_PARITY_NONE:
             break;
             
        default:
            *perr = SERIAL_ERR_DRV_INVALID;
             return; 
    }

    p_reg = (SERIAL_DRV_REG *)p_cfg->BaseAddr;

    p_cfg->BSP_API->ClkEn(perr);                                /* En dev-specific HW clk.                              */
    if (*perr != SERIAL_ERR_NONE) {
         return;
    }
        
    p_reg->LCR = DEF_BIT_NONE;                                  /* Disable Interrupts.                                  */
    p_reg->DLM = DEF_BIT_NONE;

    p_reg->LCR = reg_val;                                       /* Configure the Line control register.                 */
             
                                                                /* Baud Rate configuration ...                          */
    DEF_BIT_SET(p_reg->LCR, SERIAL_DRV_LPCXXXX_BIT_LCR_DLAB);   /* ... Enable DLAB bit (access Divisor Latch register ) */
    p_reg->RBR   = (br_div      ) & DEF_INT_08_MASK;            /* ... Set LSB Divisor Latch                            */
    p_reg->DLM   = (br_div >> 8u) & DEF_INT_08_MASK;            /* ... Set MSB Divisor Latch                            */
    DEF_BIT_CLR(p_reg->LCR, SERIAL_DRV_LPCXXXX_BIT_LCR_DLAB);   /* ... Disable DLAB bit                                 */    
    p_reg->FDR   = SERIAL_DRV_LPCXXXX_VAL_MULVAL << 4u          /* ... Set the fractional divider                       */
                 | fp_div;

                                                                /* --------------- FIFOs CONFIGURATION  --------------- */
    p_reg->IIR   = SERIAL_DRV_LPCXXXX_BIT_FCR_RX_FIFO_RST       /* Reset the TX and RX FIFOs. FIFO is disabled          */
                 | SERIAL_DRV_LPCXXXX_BIT_FCR_TX_FIFO_RST;
    
    p_reg->IIR   = SERIAL_DRV_LPCXXXX_BIT_FCR_FIFO_EN           /* Enable the FIFO & Set the Rx trigger level to 1      */
                 | SERIAL_DRV_LPCXXXX_BIT_FCR_RX_TRIG_LEVEL_01;      
    
                   
    switch (pcfg->FlowCtrl) {
        case SERIAL_FLOW_CTRL_HARDWARE:
             flow_ctrl  = DEF_ENABLED;
             break;

        case SERIAL_FLOW_CTRL_NONE:
        default:
             flow_ctrl  = DEF_DISABLED;
             break;
    }

    p_cfg->BSP_API->CfgGPIO(flow_ctrl, perr);                   /* Cfg dev-specific GPIO.                               */
    if (*perr != SERIAL_ERR_NONE) {
         return;
    }
    p_cfg->BSP_API->CfgInt(pdev, perr);                         /* Cfg dev-specific int.                                */
}
Exemple #12
0
CPU_BOOLEAN CSP_TmrOutCmpCfg  (CSP_DEV_NBR    tmr_nbr,
                               CSP_DEV_NBR    pin,
                               CSP_OPT        pin_action,
                               CPU_INT32U     freq)

{
    CSP_TMR_REG  *p_tmr_reg;
    CPU_INT08U    match_nbr;
    CPU_INT32U    match_val;
    CPU_INT32U    per_freq;
    CSP_DEV_NBR   per_nbr;
    CPU_SR_ALLOC();
    
                                                                /* ---------------- ARGUMENTS CHECKING -------------- */
#if (CSP_CFG_ARG_CHK_EN == DEF_ENABLED)
    if (tmr_nbr > CSP_TMR_NBR_01) {
        return (DEF_FAIL);
    }
    
    if (pin > CSP_TMR_PIN_OUT_NBR_03) {
        return (DEF_FAIL);
    }

    if (freq == 0u) {
        return (DEF_FAIL);
    }
#endif
    
    p_tmr_reg = (CSP_TMR_REG *)CSP_TmrAddrTbl[tmr_nbr];
    per_nbr   = (CSP_DEV_NBR  )CSP_TmrPerTbl[tmr_nbr];    
    
    match_nbr = pin,
    per_freq  = CSP_PM_PerClkFreqGet(per_nbr);                  /* Get the peripheral clock.                           */

    if (freq > per_freq) {
        return (DEF_FAIL);
    }

    match_val = ((2u * per_freq / freq) + 1u) / 2u;
    if (match_val == 0u) {
        return (DEF_FAIL);
    }
    
    
    CSP_PM_PerClkEn(per_nbr);                                   /* Enable Peripherical clock.                          */                                                               
    CPU_CRITICAL_ENTER();

    DEF_BIT_CLR(p_tmr_reg->EMR, DEF_BIT_MASK(3u, (2u * match_nbr) + 4u));
        
    switch (pin_action) {
        case CSP_TMR_OPT_PIN_OUT_NONE:
             break;
                              
        case CSP_TMR_OPT_PIN_OUT_CLR:
             DEF_BIT_SET(p_tmr_reg->EMR, DEF_BIT_MASK(1u, (2u * match_nbr) + 4u));
             break;
                         
        case CSP_TMR_OPT_PIN_OUT_SET:
             DEF_BIT_SET(p_tmr_reg->EMR, DEF_BIT_MASK(2u, (2u * match_nbr) + 4u));
             break;
        
        case CSP_TMR_OPT_PIN_OUT_TOGGLE:
             DEF_BIT_SET(p_tmr_reg->EMR, DEF_BIT_MASK(3u, (2u * match_nbr) + 4u));
             break;
             
        default:
             CPU_CRITICAL_EXIT();
             return (DEF_FAIL);            
    }
                                                            /* Disable the Interrupt, Reset and Stop features on   */        
                                                            /* ... Match channel 0, 1, 2 or 3.                     */
    DEF_BIT_CLR(p_tmr_reg->MCR, CSP_TMR_MASK_MCR_MRx(match_nbr));
                                
    DEF_BIT_CLR(p_tmr_reg->TCR, CSP_TMR_MASK_TCR_MODE);     /* Clear the Mode                                      */
    DEF_BIT_SET(p_tmr_reg->TCR, CSP_TMR_BIT_TCR_TMR_MODE);  /* Set the Timer Mode                                  */

    p_tmr_reg->PR             = 0u;                         /* Set the prescaler to 0                              */
    p_tmr_reg->MRx[match_nbr] = match_val;
    p_tmr_reg->TCR            = CSP_TMR_BIT_CR_RST;         /* Reset the timer                                     */
                                                            /* Enable Interrupt and Reset when TC matches MR0, ... */
                                                            /* MR1, MR2, etc                                       */
    DEF_BIT_SET(p_tmr_reg->MCR, CSP_TMR_BIT_MCR_MRIx(match_nbr) | 
                                CSP_TMR_BIT_MCR_MRRx(match_nbr));
    CPU_CRITICAL_EXIT();

    return (DEF_OK);
}
Exemple #13
0
CPU_BOOLEAN  CSP_TmrCfg (CSP_DEV_NBR   tmr_nbr,
                         CPU_INT32U    freq)
{
    CSP_TMR_REG  *p_tmr_reg;
    CPU_INT32U    match_val;
    CPU_INT32U    per_freq;
    CSP_DEV_NBR   per_nbr;    
    CPU_SR_ALLOC();
    
#if (CSP_CFG_ARG_CHK_EN == DEF_ENABLED)     
    if (tmr_nbr > CSP_TMR_NBR_03) {
        return (DEF_FAIL);
    }
#endif

    
    p_tmr_reg = (CSP_TMR_REG *)CSP_TmrAddrTbl[tmr_nbr];
    per_nbr   = (CSP_DEV_NBR  )CSP_TmrPerTbl[tmr_nbr];    
    
    if (freq == 0u) {                                           /* -------- FREE RUNNING TIMER CONFIGURATION --------- */
        CSP_PM_PerClkEn(per_nbr);                               /* Enable peripheral clock                             */                                                               
        
        CPU_CRITICAL_ENTER();        
        p_tmr_reg->MCR = DEF_BIT_NONE;                          /* Disable theInterrupt, Reset and Stop feauture on    */
                                                                /* ... Match channels.                                 */
        
        DEF_BIT_CLR(p_tmr_reg->TCR, CSP_TMR_MASK_TCR_MODE);     /* Clear the Mode.                                     */
        DEF_BIT_SET(p_tmr_reg->TCR, CSP_TMR_BIT_TCR_TMR_MODE);  /* Set the Timer Mode.                                 */
        
        p_tmr_reg->PR  = 0u;                                    /* Set the prescaler to 0.                             */
        p_tmr_reg->TCR = CSP_TMR_BIT_CR_RST;                    /* Reset the timer.                                    */
        CPU_CRITICAL_EXIT();

    } else {                                                    /* ---------- PERIODIC TIMER CONFIGURATION ----------- */
        per_freq = CSP_PM_PerClkFreqGet(per_nbr);               /* Get the peripheral clock.                           */

        if (freq > per_freq) {
            return (DEF_FAIL);
        }

        match_val = ((2u * per_freq / freq) + 1u) / 2u;
        if (match_val == 0u) {
            return (DEF_FAIL);
        }
        
        
        CSP_PM_PerClkEn(per_nbr);                               /* Enable peripheral clock.                           */                                                               
        CPU_CRITICAL_ENTER();
        DEF_BIT_CLR(p_tmr_reg->EMR, DEF_BIT_MASK(3u, (2u * 0u) + 4u));
        CPU_CRITICAL_EXIT();

                                                                /* Disable the Interrupt, Reset and Stop features on   */        
                                                                /* ... Match channel 0, 1, 2 or 3.                     */
        DEF_BIT_CLR(p_tmr_reg->MCR, CSP_TMR_MASK_MCR_MRx(0u));
                                    
        DEF_BIT_CLR(p_tmr_reg->TCR, CSP_TMR_MASK_TCR_MODE);     /* Clear the Mode                                      */
        DEF_BIT_SET(p_tmr_reg->TCR, CSP_TMR_BIT_TCR_TMR_MODE);  /* Set the Timer Mode                                  */

        p_tmr_reg->PR     = 0u;                                 /* Set the prescaler to 0                              */
        p_tmr_reg->MRx[0] = match_val;
        p_tmr_reg->TCR    = CSP_TMR_BIT_CR_RST;                 /* Reset the timer                                     */
                                                                /* Enable Interrupt and Reset when TC matches MR0, ... */
                                                                /* MR1, MR2, etc                                       */        
        DEF_BIT_SET(p_tmr_reg->MCR, CSP_TMR_BIT_MCR_MRIx(0u) | 
                                    CSP_TMR_BIT_MCR_MRRx(0u));
        CPU_CRITICAL_EXIT();
    }

    return (DEF_OK);
}
Exemple #14
0
static  CPU_BOOLEAN  BSP_CPU_Init (void)
{
    CPU_INT16U    reg_to;
    CPU_INT32U    reg_val;
    CPU_SR_ALLOC();


    BSP_REG_FLASHCFG = (CPU_INT32U)BSP_MSK_FLASHCFG_CLK_6;      /* Set 6 cycles to acces the Flash memory (Safe setting)*/

                                                                /* ----------- MAIN OSCILLATOR INITIALIZATION --------- */
    DEF_BIT_CLR(BSP_REG_SCS, BSP_BIT_SCS_OSCRANGE);             /* Set the main oscillator range                        */


    reg_to = BSP_VAL_MAX_TO;

    DEF_BIT_SET(BSP_REG_SCS, BSP_BIT_SCS_OSCEN);                /* Enable the Main Oscillator                           */

                                                                /* Wait until the main oscillator is enabled.           */
    while (DEF_BIT_IS_CLR(BSP_REG_SCS, BSP_BIT_SCS_OSCSTAT) &&
          (reg_to > 0u)) {
        reg_to--;
    }

    if (reg_to == 0u) {                                         /* Configuration fail                                   */
        return (DEF_FAIL);
    }

    BSP_REG_PCLKSEL0 = DEF_BIT_NONE;                            /* All peripheral clock runs at CPU_Clk / 4 = 25 Mhz.   */
    BSP_REG_PCLKSEL1 = DEF_BIT_NONE;

                                                                /* ------------------ PLL0 CONFIGURATION -------------- */

    reg_val  = (((25u - 1u) <<  0u) & BSP_MSK_PLLCFG0_MSEL)     /* PLL0 values M = 25 & N = 2 (see note #6)             */
             | ((( 2u - 1u) << 16u) & BSP_MSK_PLLCFG0_NSEL);
                                                                /* 1. Disconnect PLL0 with one feed sequence if PLL ... */
                                                                /* ... already connected.                               */
    if (DEF_BIT_IS_SET(BSP_REG_PLLSTAT(0u), BSP_BIT_PLLSTAT_PLLC0_STAT)) {
        DEF_BIT_CLR(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLC);
        BSP_PLL_FEED_SEQ(0u);
    }

    DEF_BIT_CLR(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLE);     /* 2. Disable PLL0 with one feed sequence               */
    BSP_PLL_FEED_SEQ(0u);

    BSP_REG_CCLKCFG   = (1u - 1u);                              /* 3. Change the CPU clock divider setting to speed ... */
                                                                /* ... operation without PLL0                           */

    BSP_REG_CLKSRCSEL = BSP_BIT_CLKSRCSEL_MAIN;                 /* 4. Select the main osc. as the PLL0 clock source     */

    BSP_REG_PLLCFG(0u) = reg_val;                               /* 5. Write to the PLLCFG and make it effective with... */
    BSP_PLL_FEED_SEQ(0u)                                        /* ... one one feed sequence                            */

    DEF_BIT_SET(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLE);     /* 6. Enable PLL0 with one feed sequence                */
    BSP_PLL_FEED_SEQ(0u);

    BSP_REG_CCLKCFG   = (3u - 1u);                              /* 7. Change the CPU clock divider setting for ...      */
                                                                /* ... operation with PLL0                              */

    reg_to = BSP_VAL_MAX_TO;                                    /* 8. Wait for PLL0 to achieve lock by monitoring ...   */
                                                                /* ... the PLOCK0 bit in the PLL0STAT                   */
    while (DEF_BIT_IS_CLR(BSP_REG_PLLSTAT(0u), BSP_BIT_PLLSTAT_PLOCK0) &&
          (reg_to > 0u)) {
        reg_to--;
    }

    if (reg_to == 0u) {
        return (DEF_FAIL);
    }

    DEF_BIT_SET(BSP_REG_PLLCTRL(0u), BSP_BIT_PLLCTRL_PLLC);     /* 9. Connect PLL0 with one feed sequence.              */
    BSP_PLL_FEED_SEQ(0u);
                                                                /* ------------------ PLL1 CONFIGURATION -------------- */
    reg_val  = (((4u - 1u)  <<  0u) & BSP_MSK_PLLCFG1_MSEL)     /* PLL1 values M = 4; P = 2 coded as '01' (see note #6) */
             | (((0x01u   ) <<  5u) & BSP_MSK_PLLCFG1_NSEL);

    DEF_BIT_CLR(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLC);     /* 1. Disconnect PLL1 with one feed sequence            */
    BSP_PLL_FEED_SEQ(1u);

    DEF_BIT_CLR(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLE);     /* 2. Disable PLL1 with one feed sequence               */
    BSP_PLL_FEED_SEQ(1u);

    BSP_REG_PLLCFG(1u) = reg_val;                               /* 3. Write to the PLLCFG and make it effective with... */
    BSP_PLL_FEED_SEQ(1u);                                       /* ... one one feed sequence                            */

    DEF_BIT_SET(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLE);     /* 4. Enable PLL1 with one feed sequence                */
    BSP_PLL_FEED_SEQ(1u);

    reg_to = BSP_VAL_MAX_TO;                                    /* 5. Wait for PLL1 to achieve lock by monitoring ...   */
                                                                /* ... the PLOCK1 bit in the PLL1STAT                   */
    while (DEF_BIT_IS_CLR(BSP_REG_PLLSTAT(1u), BSP_BIT_PLLSTAT_PLOCK1) &&
          (reg_to > 0u)) {
        reg_to--;
    }

    if (reg_to == 0u) {
        return (DEF_FAIL);
    }


    DEF_BIT_SET(BSP_REG_PLLCTRL(1u), BSP_BIT_PLLCTRL_PLLC);     /* 6. Connect PLL1 with one feed sequence               */
    BSP_PLL_FEED_SEQ(1u);

    BSP_REG_FLASHCFG = BSP_MSK_FLASHCFG_CLK_5                   /* Set 5 cycles to access the Flash memory.             */
                     | BSP_BIT_FLASHCFG_FETCHCFG_ALL
                     | BSP_BIT_FLASHCFG_DATACFG_ALL
                     | BSP_BIT_FLASHCFG_ACCEL_EN
                     | BSP_BIT_FLASHCFG_PREFETCH_ALL;

    return (DEF_OK);
}
Exemple #15
0
void   BSP_GPIO_Cfg (CPU_INT08U   gpio_port,
                     CPU_INT32U   gpio_pins,     
                     CPU_INT16U   gpio_opt)
{
    BSP_GPIO_FAST_REG  *p_gpio_fast_reg;    
    CPU_REG32          *p_gpio_pinsel;
    CPU_REG32          *p_gpio_pinmode;  
    CPU_REG32          *p_gpio_pinmode_od;  
    
    CPU_INT32U          pinsel_opt;
    CPU_INT32U          pinmode_opt;
    CPU_INT32U          pin_nbr;
    
    
    switch (gpio_port) {
        case BSP_GPIO_PORT0_FAST:
             p_gpio_fast_reg   = (BSP_GPIO_FAST_REG *)(BSP_GPIO_REG_PORT0_FAST_BASE_ADDR); 
             p_gpio_pinsel     = (CPU_REG32         *)(BSP_GPIO_REG_PINSEL_BASE_ADDR  + 0x00);
             p_gpio_pinmode    = (CPU_REG32         *)(BSP_GPIO_REG_PINMODE_BASE_ADDR + 0x00);
             p_gpio_pinmode_od = (CPU_REG32         *)(BSP_GPIO_REG_PINMODE_OD0_BASE_ADDR);
             break;

        case BSP_GPIO_PORT1_FAST:
             p_gpio_fast_reg   = (BSP_GPIO_FAST_REG *)(BSP_GPIO_REG_PORT1_FAST_BASE_ADDR); 
             p_gpio_pinsel     = (CPU_REG32         *)(BSP_GPIO_REG_PINSEL_BASE_ADDR  + 0x08);
             p_gpio_pinmode    = (CPU_REG32         *)(BSP_GPIO_REG_PINMODE_BASE_ADDR + 0x08);
             p_gpio_pinmode_od = (CPU_REG32         *)(BSP_GPIO_REG_PINMODE_OD1_BASE_ADDR);
             break;

        case BSP_GPIO_PORT2_FAST:
             p_gpio_fast_reg   = (BSP_GPIO_FAST_REG *)(BSP_GPIO_REG_PORT2_FAST_BASE_ADDR); 
             p_gpio_pinsel     = (CPU_REG32         *)(BSP_GPIO_REG_PINSEL_BASE_ADDR  + 0x10);
             p_gpio_pinmode    = (CPU_REG32         *)(BSP_GPIO_REG_PINMODE_BASE_ADDR + 0x10);
             p_gpio_pinmode_od = (CPU_REG32         *)(BSP_GPIO_REG_PINMODE_OD2_BASE_ADDR);
             
             break;

        case BSP_GPIO_PORT3_FAST:
             p_gpio_fast_reg   = (BSP_GPIO_FAST_REG *)(BSP_GPIO_REG_PORT3_FAST_BASE_ADDR); 
             p_gpio_pinsel     = (CPU_REG32         *)(BSP_GPIO_REG_PINSEL_BASE_ADDR  + 0x18);
             p_gpio_pinmode    = (CPU_REG32         *)(BSP_GPIO_REG_PINMODE_BASE_ADDR + 0x18);
             p_gpio_pinmode_od = (CPU_REG32         *)(BSP_GPIO_REG_PINMODE_OD3_BASE_ADDR);
             
             break;

        case BSP_GPIO_PORT4_FAST:
             p_gpio_fast_reg   = (BSP_GPIO_FAST_REG *)(BSP_GPIO_REG_PORT4_FAST_BASE_ADDR); 
             p_gpio_pinsel     = (CPU_REG32         *)(BSP_GPIO_REG_PINSEL_BASE_ADDR  + 0x20);
             p_gpio_pinmode    = (CPU_REG32         *)(BSP_GPIO_REG_PINMODE_BASE_ADDR + 0x20);
             p_gpio_pinmode_od = (CPU_REG32         *)(BSP_GPIO_REG_PINMODE_OD4_BASE_ADDR);
             break;

        case BSP_GPIO_PORT0:
        case BSP_GPIO_PORT1:             
        default:
             return;
    }

                                                                /* ------------ I/O DIRECTION CONFIGURATION ----------- */
    if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_OUT_EN)) {
        DEF_BIT_SET(p_gpio_fast_reg->FIODIR, gpio_pins);
    }
    
    if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_IN_EN)) {
        DEF_BIT_CLR(p_gpio_fast_reg->FIODIR, gpio_pins);
    }            
        
    if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_RD_WR_EN)) {
        DEF_BIT_CLR(p_gpio_fast_reg->FIOMASK, gpio_pins);
    }            
    
    if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_RD_WR_DIS)) {
        DEF_BIT_SET(p_gpio_fast_reg->FIOMASK, gpio_pins);
    }            

                
                                                                /* ---- I/O MODE/PERIPHERAL FUNCTION CONFIGURATION ---- */
    pinsel_opt  = BSP_GPIO_OPT_FNCT_INVALID;                   
    pinmode_opt = BSP_GPIO_OPT_MODE_INVALID;
                                                                /* Set PINSELxx based on BSP_GPIO_OPT_FNCT_xxx          */
    if (DEF_BIT_IS_SET_ANY(gpio_opt, BSP_GPIO_OPT_FNCT_ANY)) {
        if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_FNCT_1)) {
            pinsel_opt = 0x00;
        } else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_FNCT_2)) {
            pinsel_opt = 0x01;
        } else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_FNCT_3)) {
            pinsel_opt = 0x02;
        } else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_FNCT_4)) {
            pinsel_opt = 0x03;
        } else {
            return;
        }
    }

                                                                /* Set PMODExx based on BSP_GPIO_OPT_MDOE_xxx         */
    if (DEF_BIT_IS_SET_ANY(gpio_opt, BSP_GPIO_OPT_MODE_ANY)) {
        if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_MODE_PULLUP)) {
            pinmode_opt = 0x00;
        } else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_MODE_REPEATER)) {
            pinmode_opt = 0x01;            
        } else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_MODE_NONE)) {
            pinmode_opt = 0x02;
        } else if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_MODE_PULLDOWN)) {
            pinmode_opt = 0x03;
        }
    }
    
    if ((pinsel_opt != BSP_GPIO_OPT_FNCT_INVALID) ||
        (pinmode_opt  != BSP_GPIO_OPT_MODE_INVALID)) {
        for (pin_nbr = 0; pin_nbr < 32; pin_nbr++) {
            if (DEF_BIT_IS_SET(gpio_pins, DEF_BIT(pin_nbr))) {
                
                if (pinsel_opt != BSP_GPIO_OPT_FNCT_INVALID) {
                    if (pin_nbr < 16) {
                        DEF_BIT_CLR(*p_gpio_pinsel, DEF_BIT_FIELD(2, pin_nbr * 2));
                        DEF_BIT_SET(*p_gpio_pinsel, DEF_BIT_MASK(pinsel_opt, pin_nbr * 2));
                    } else {
                        DEF_BIT_CLR(*((CPU_REG32 *)((CPU_INT32U)p_gpio_pinsel + 0x04)), DEF_BIT_FIELD(2, (pin_nbr - 16) * 2));
                        DEF_BIT_SET(*((CPU_REG32 *)((CPU_INT32U)p_gpio_pinsel + 0x04)), DEF_BIT_MASK(pinsel_opt, (pin_nbr - 16) * 2));
                    }
                }
        
                if (DEF_BIT_IS_SET(gpio_pins, DEF_BIT(pin_nbr))) {
                    if (pinmode_opt != BSP_GPIO_OPT_MODE_INVALID) {
                        if (pin_nbr < 16) {                        
                            DEF_BIT_CLR(*p_gpio_pinmode, DEF_BIT_FIELD(2, pin_nbr * 2));
                            DEF_BIT_SET(*p_gpio_pinmode, DEF_BIT_MASK(pinmode_opt, pin_nbr * 2));
                        } else {
                            DEF_BIT_CLR(*((CPU_REG32 *)((CPU_INT32U)p_gpio_pinmode + 0x04)), DEF_BIT_FIELD(2, (pin_nbr - 16) * 2));
                            DEF_BIT_SET(*((CPU_REG32 *)((CPU_INT32U)p_gpio_pinmode + 0x04)), DEF_BIT_MASK(pinmode_opt, (pin_nbr - 16) * 2));
                        }
                    }
                }
            }
        }
    }

    if (DEF_BIT_IS_SET(gpio_opt, BSP_GPIO_OPT_MODE_OPEN_DRAIN)) {
        *p_gpio_pinmode_od = gpio_pins;
    }
}