int main() { uart_config_t uart_conf; DISABLE_IRQ(); hal_clk_init(); sys_tick_init(); I2cInit( &I2c, I2C_SCL, I2C_SDA ); uart_conf.baud = 9600; uart_conf.word_length = 8; uart_conf.parity = NONE; uart_conf.stop_bits = 1; uart_init(&uart_conf); ENABLE_IRQ(); app_init(); DISABLE_IRQ(); led_init(); while(1){ /** polling all events */ app_evt(); led_evt(); } }
int16_t inqueue_get(queue_t *q, int timeout) { StatusType rc; uint64_t deadline = 0; uint8_t value; if (timeout > TIMEOUT_NOBLOCK) { deadline = timeout + CoGetOSTime(); } DISABLE_IRQ(); while (q->count == 0) { ENABLE_IRQ(); if (timeout == TIMEOUT_NOBLOCK) { return EERR_TIMEOUT; } rc = CoWaitForSingleFlag(q->flag, timeout == TIMEOUT_FOREVER ? 0 : (CoGetOSTime() - deadline)); if (rc != E_OK) { return EERR_TIMEOUT; } DISABLE_IRQ(); } q->count--; value = *q->p_read++; if (q->p_read == q->p_top) { q->p_read = q->p_bot; } ENABLE_IRQ(); return value; }
void play_music() { uint32_t counter=0; LV2_Atom_Forge_Frame midi_seq_frame; int buffer_processed = 0; const Lv2Plugin *plugin; plugin = lv2_world->plugin_list; DISABLE_IRQ(); lv2_port *output_left = new_lv2_port(lv2_audio_port, 1); lv2_port *output_right = new_lv2_port(lv2_audio_port, 2); lv2_port *midi_in = new_lv2_port(lv2_atom_port, 3); plugin->descriptor->connect_port(plugin->handle, midi_in->id, midi_in->buffer); plugin->descriptor->connect_port(plugin->handle, output_left->id, output_left->buffer); plugin->descriptor->connect_port(plugin->handle, output_right->id, output_right->buffer); lv2_atom_forge_set_buffer(&forge, midi_in->buffer, LV2_ATOM_BUFFER_SIZE); lv2_atom_forge_sequence_head(&forge, &midi_seq_frame, 0); init_midi_source(&forge); while (1) { DISABLE_IRQ(); if (!buffer_processed) { forge_midi_input(); lv2_atom_forge_pop(&forge, &midi_seq_frame); plugin->descriptor->run(plugin->handle, LV2_AUDIO_BUFFER_SIZE); lv2_atom_forge_set_buffer(&forge, midi_in->buffer, sizeof(uint8_t) * midi_in->buffer_sz); lv2_atom_forge_sequence_head(&forge, &midi_seq_frame, 0); buffer_processed = 1; } if (buffer_processed && audio_buffer_free_space() > LV2_AUDIO_BUFFER_SIZE * 2) { audio_buffer_write(output_left->buffer, output_right->buffer, output_left->buffer_sz); buffer_processed = 0; counter++; } ENABLE_IRQ(); } }
void outqueue_drain(queue_t *q) { DISABLE_IRQ(); while (1) { if (q->count == 0) { break; } ENABLE_IRQ(); __ISB(); DISABLE_IRQ(); } ENABLE_IRQ(); }
void kmain() { init_kernel(); int ret; ret = sys_setscheduler(ROUND_ROBIN_SCHED); // returns 0 create_process(&process1); create_process(&process2); create_process(&process3); start_kernel(); while (current_process != current_process->next || current_process != current_process->previous) ; DISABLE_IRQ(); ret = sys_setscheduler(RANDOM_SCHED); create_process(&process1); create_process(&process2); create_process(&process3); ENABLE_IRQ(); while (current_process != current_process->next || current_process != current_process->previous) ; DISABLE_IRQ(); ret = sys_setscheduler(FIXED_PRIORITY_SCHED); create_process_with_fix_priority(&process1, 5); create_process_with_fix_priority(&process2, 2); create_process_with_fix_priority(&process3, 4); ENABLE_IRQ(); while (current_process != current_process->next || current_process != current_process->previous) ; DISABLE_IRQ(); ret = sys_setscheduler(DYNAMIC_PRIORITY_SCHED); create_process(&process1); create_process(&process2); create_process(&process3); ENABLE_IRQ(); while (current_process != current_process->next || current_process != current_process->previous) ; ret = sys_setscheduler(-50); // fail (returns -1) ret++; }
int lpptest_ioctl(struct inode *inode, struct file *file, unsigned int ioctl_num, unsigned long ioctl_param) { int retval = 0; switch (ioctl_num) { case LPPTEST_DISABLE: DISABLE_IRQ(); break; case LPPTEST_ENABLE: ENABLE_IRQ(); break; case LPPTEST_TEST: { cycles_t diff = test_response(); if (copy_to_user((void *)ioctl_param, (void*) &diff, sizeof(diff))) goto errcpy; break; } default: retval = -EINVAL; } return retval; errcpy: return -EFAULT; }
static int get_status(unsigned char *adr) { int i,c; DISABLE_IRQ(); c = sendcmd(0,0x00,NODE_ADR | C_GETEA); /* CMD: GET ETH ADR*/ if( c < 0 ) goto gsend; /* now read status bytes */ for (i=0; i<6; i++) { dma_wd.fdc_acces_seccount = 0; /* request next byte */ if( !acsi_wait_for_IRQ(HZ/2) ) { /* wait for cmd ack */ c = -1; goto gsend; /* timeout */ } c = dma_wd.fdc_acces_seccount; *adr++ = (unsigned char)c; } c = 1; gsend: dma_wd.dma_mode_status = 0x80; return c; }
void mtx_unlock(struct mtx_s* mutex){ DISABLE_IRQ(); if (current_process == mutex->owner) { sem_up(mutex->sem_mtx); } ENABLE_IRQ(); }
void sem_down(struct sem_s* sem) { DISABLE_IRQ(); if (sem->val <= 0) { // Initializing "wait_proc" struct waiting_process* wait_proc = (struct waiting_process*) malloc_alloc(sizeof(struct waiting_process)); wait_proc->process = current_process; wait_proc->next = 0; // If the waiting queue is empty, we put our process as the first (and only) waiting element if (sem->waiting == 0) { sem->last_process = wait_proc; sem->queue = wait_proc; } // Otherwise we put it at the end of the queue else { sem->last_process->next = wait_proc; sem->last_process = wait_proc; } sem->waiting += 1; current_process->state = WAITING; ENABLE_IRQ(); while(current_process->state== WAITING){ //DO NOTHING } } else { sem->val -= 1; ENABLE_IRQ(); } }
static void __exit lpptest_exit (void) { DISABLE_IRQ(); free_irq(LPPTEST_IRQ, dev_id); unregister_chrdev(LPPTEST_CHAR_MAJOR, LPPTEST_DEVICE_NAME); }
void cli_cmd_profile(char *cmdline) { uint64_t task_counts[CFG_MAX_USER_TASKS+SYS_TASK_NUM]; uint64_t count, pct, total = 0; void *heap; int i; DISABLE_IRQ(); for(i = 0; i < CFG_MAX_USER_TASKS+SYS_TASK_NUM; i++) { task_counts[i] = count = TCBTbl[i].tick_count; total += count; } ENABLE_IRQ(); cli_printf("# Counts %% Name\r\n"); for(i = 0; i < CFG_MAX_USER_TASKS+SYS_TASK_NUM; i++) { count = task_counts[i]; pct = 10000 * count / total; cli_printf("%2d %08x%08x %3u.%02u%% %s\r\n", i, (uint32_t)(count >> 32), (uint32_t)count, (uint32_t)(pct / 100), (uint32_t)(pct % 100), TCBTbl[i].name); } heap = _sbrk(0); if (heap != (void*)-1) { cli_printf("Heap usage: %d bytes\r\n", heap - (void*)&_sheap); } }
void monotonic_sleep_until(uint64_t mono_when) { mono_when -= mono_when % MONO_PERIOD; DISABLE_IRQ(); sleep_epoch = mono_when; ENABLE_IRQ(); xSemaphoreTake(sleep_flag, portMAX_DELAY); }
int16_t outqueue_put(queue_t *q, const uint8_t *value, uint16_t size, int timeout) { StatusType rc; uint64_t deadline = 0; if (timeout > TIMEOUT_NOBLOCK) { deadline = timeout + CoGetOSTime(); } DISABLE_IRQ(); while (size) { while (q->count == q->size) { /* Wake this thread up when the buffer has room for all remaining * bytes, or is empty. */ if (size > q->size) { q->wakeup = 0; } else { q->wakeup = q->size - size; } ENABLE_IRQ(); if (q->cb_func) { q->cb_func(q->cb_arg); } if (timeout == TIMEOUT_NOBLOCK) { return EERR_TIMEOUT; } rc = CoWaitForSingleFlag(q->flag, timeout == TIMEOUT_FOREVER ? 0 : (CoGetOSTime() - deadline)); if (rc != E_OK) { return EERR_TIMEOUT; } DISABLE_IRQ(); } size--; q->count++; *q->p_write++ = *value++; if (q->p_write == q->p_top) { q->p_write = q->p_bot; } } ENABLE_IRQ(); if (q->cb_func) { q->cb_func(q->cb_arg); } return EERR_OK; }
uint64_t monotonic_get_capture(void) { /* Get the previous PPS capture */ uint64_t ret; DISABLE_IRQ(); ret = mono_capture; mono_capture = 0; ENABLE_IRQ(); return ret; }
void main() { uint32_t timestamp; sx1276_config_t sx1276_config; DISABLE_IRQ(); hal_clk_init(); sys_tick_init(); ENABLE_IRQ(); led_init(); sx1276_init(LORA, NULL); sx1276_config.frequency = 433400000; sx1276_config.spread_factor = SX1276_SF7; sx1276_config.bandwidth = SX1276_BW_125K; sx1276_config.coding_rate = SX1276_CR1; sx1276_config.crc_mode = SX1276_CRC_ON; sx1276_config.header_mode = SX1276_HEADER_ENABLE; sx1276_config.payload_len = 0; // Set in HEADER disable mode sx1276_config.tx_power = 20; sx1276_config.tx_preamble_len = 12; sx1276_config.rx_preamble_len = 12; sx1276_set_config(&sx1276_config); /** Enter HF/LF test mode */ if(sx1276_config.frequency < SX1276_LF_FREQ_MAX){ sx1276_write( 0x01, 0x88 ); }else{ sx1276_write( 0x01, 0x80 ); } sx1276_write( 0x3D, 0xA1 ); sx1276_write( 0x36, 0x01 ); sx1276_write( 0x1e, 0x08 ); /** Enable TX to enter continuous wave transmitting mode */ sx1276_send(NULL, 0, 0); /** Get system tick */ timestamp = millis(); while(1){ /** Blink LED every 1s*/ if( millis() - timestamp > 1000){ timestamp = millis(); led_blink(LED0, 100); } /** LED event polling */ led_evt(); } }
FUNC(void, OS_CODE) tpl_shutdown(void) { /* FIXME: this is does not conform to AUTOSAR OS specifications, * should return to main with initial context */ DISABLE_FIQ (); DISABLE_IRQ (); /* TODO : fall into very low consumption mode : all * internal CPU clocks are disabled. */ while (1); }
static void start_print( int device ) { struct slm *sip = &slm_info[device]; unsigned char *cmd; unsigned long paddr; int i; stdma_lock( slm_interrupt, NULL ); CMDSET_TARG_LUN( slmprint_cmd, sip->target, sip->lun ); cmd = slmprint_cmd; paddr = virt_to_phys( SLMBuffer ); dma_cache_maintenance( paddr, virt_to_phys(BufferP)-paddr, 1 ); DISABLE_IRQ(); /* Low on A1 */ dma_wd.dma_mode_status = 0x88; MFPDELAY(); /* send the command bytes except the last */ for( i = 0; i < 5; ++i ) { DMA_LONG_WRITE( *cmd++, 0x8a ); udelay(20); if (!acsi_wait_for_IRQ( HZ/2 )) { SLMError = 1; return; /* timeout */ } } /* last command byte */ DMA_LONG_WRITE( *cmd++, 0x82 ); MFPDELAY(); /* set DMA address */ set_dma_addr( paddr ); /* program DMA for write and select sector counter reg */ dma_wd.dma_mode_status = 0x192; MFPDELAY(); /* program for 255*512 bytes and start DMA */ DMA_LONG_WRITE( SLM_DMA_AMOUNT, 0x112 ); #ifndef SLM_CONT_CNT_REPROG SLMCurAddr = paddr; SLMEndAddr = paddr + SLMSliceSize + SLM_DMA_INT_OFFSET; #endif START_TIMER( DMA_STARTUP_TIME + DMA_TIME_FOR( SLMSliceSize )); #if !defined(SLM_CONT_CNT_REPROG) && defined(DEBUG) printk( "SLM: CurAddr=%#lx EndAddr=%#lx timer=%ld\n", SLMCurAddr, SLMEndAddr, DMA_TIME_FOR( SLMSliceSize ) ); #endif ENABLE_IRQ(); }
static int get_frame(unsigned long paddr, int odd) { int c; unsigned long flags; DISABLE_IRQ(); local_irq_save(flags); dma_wd.dma_mode_status = 0x9a; dma_wd.dma_mode_status = 0x19a; dma_wd.dma_mode_status = 0x9a; dma_wd.fdc_acces_seccount = 0x04; /* sector count (was 5) */ dma_wd.dma_lo = (unsigned char)paddr; paddr >>= 8; dma_wd.dma_md = (unsigned char)paddr; paddr >>= 8; dma_wd.dma_hi = (unsigned char)paddr; local_irq_restore(flags); c = sendcmd(0,0x00,NODE_ADR | C_READ); /* CMD: READ */ if( c < 128 ) goto rend; /* now read block */ c = sendcmd(1,0x00,odd); /* odd flag for address shift */ dma_wd.dma_mode_status = 0x0a; if( !acsi_wait_for_IRQ(100) ) { /* wait for DMA to complete */ c = -1; goto rend; } dma_wd.dma_mode_status = 0x8a; dma_wd.dma_mode_status = 0x18a; dma_wd.dma_mode_status = 0x8a; c = dma_wd.fdc_acces_seccount; dma_wd.dma_mode_status = 0x88; c = dma_wd.fdc_acces_seccount; c = 1; rend: dma_wd.dma_mode_status = 0x80; udelay(40); acsi_wait_for_noIRQ(20); return c; }
void hal_sx1276_init(void) { uint32_t Exit_Line_Sum = 0; /** SPI 10MHz, SCK Low when IDlE, sample on rising edge */ Spi1 = sx1276.Spi; hal_spi_init(10000000, SPI_SCK_POLARITY_LOW, SPI_SAMPLE_ON_RISING_EDGE); HAL_SX1276_SW_LF_INPUT(); HAL_SX1276_SW_HF_INPUT(); HAL_SX1276_SW_PWR_INPUT(); HAL_SX1276_DIO0_INPUT(); HAL_SX1276_DIO1_INPUT(); HAL_SX1276_DIO2_INPUT(); HAL_SX1276_DIO3_INPUT(); HAL_SX1276_DIO4_INPUT(); HAL_SX1276_DIO5_INPUT(); // //sys_tick_init(); // //for debugger // //to be confirmed // RxChainCalibration(); /*debugger end*/ DISABLE_IRQ(); SX1276IoIrqInit( hal_sx1276_irq_callback, &Exit_Line_Sum ); //EXTI->CR2 = 0x55; // Px4~7 rising edge interrupt ENABLE_IRQ(); /** Clear interrupt flag */ EXTI_ClearFlag( Exit_Line_Sum ); /*EXTI->SR1 |= (HAL_SX1276_DIO0_BIT | HAL_SX1276_DIO1_BIT | \ HAL_SX1276_DIO2_BIT | HAL_SX1276_DIO3_BIT);*/ HAL_SX1276_NSS_OUTPUT(); HAL_SX1276_NSS_H(); //HAL_SX1276_RST_INPUT(); }
static int hardware_send_packet(unsigned long paddr, int cnt) { unsigned int c; unsigned long flags; DISABLE_IRQ(); local_irq_save(flags); dma_wd.dma_mode_status = 0x19a; dma_wd.dma_mode_status = 0x9a; dma_wd.dma_mode_status = 0x19a; dma_wd.dma_lo = (unsigned char)paddr; paddr >>= 8; dma_wd.dma_md = (unsigned char)paddr; paddr >>= 8; dma_wd.dma_hi = (unsigned char)paddr; dma_wd.fdc_acces_seccount = 0x4; /* sector count */ local_irq_restore(flags); c = sendcmd(0,0x100,NODE_ADR | C_WRITE); /* CMD: WRITE */ c = sendcmd(1,0x100,cnt&0xff); c = sendcmd(1,0x100,cnt>>8); /* now write block */ dma_wd.dma_mode_status = 0x10a; /* DMA enable */ if( !acsi_wait_for_IRQ(100) ) /* wait for DMA to complete */ goto end; dma_wd.dma_mode_status = 0x19a; /* DMA disable ! */ c = dma_wd.fdc_acces_seccount; end: c = sendcmd(1,0x100,0); c = sendcmd(1,0x100,0); dma_wd.dma_mode_status = 0x180; udelay(40); acsi_wait_for_noIRQ(20); return( c & 0x02); }
//------------------------------------------------------------------------ int notmain ( void ) { DISABLE_IRQ(); init_hw(); malloc_init( (void*)0x50000); //On cree les deux processus create_process(STACK_SIZE,funcA, NULL,2); create_process(STACK_SIZE,funcB, NULL,2); create_process(STACK_SIZE,funcC, NULL,1); //On lance l'ordonnanceur start_sched(); /* Pas atteignable vues nos 2 fonctions */ return(0); }
uint64_t monotonic_now(void) { /* Get value of monotonic clock */ uint64_t ret; uint16_t tmr1, tmr2; DISABLE_IRQ(); while (1) { tmr1 = TIM3->CNT; ret = mono_epoch; tmr2 = TIM3->CNT; if (tmr2 > tmr1) { break; } /* Timer rolled over while we were sampling. Process the update event * now */ TIM3_IRQHandler(); } ENABLE_IRQ(); return ret + tmr2; }
FUNC(void, OS_CODE) tpl_shutdown () { DISABLE_FIQ (); DISABLE_IRQ (); #if WITH_MEMORY_PROTECTION == YES /* disable the MMU, useful for debugging sessions */ MMU_disable (); #endif /* WITH_MEMORY_PROTECTION */ #if WITH_CPU_CACHE == YES arm926_cache_off (); arm926_cache_invalidate (); #endif /* WITH_CPU_CACHE */ /* fall into very low consumption mode : all * internal CPU clocks are disabled. */ __asm__ ("mcr p15,0,r0,c7,c0,4\n"); while (1); }
int_least8_t enc_getdelta(void) { int_least8_t val; DISABLE_IRQ(); val = enc_delta; //read single step encoders // enc_delta = 0; //read two step encoders // enc_delta = val & 1; // val >>= 1; //read four step encoders enc_delta = val & 3; val >>= 2; ENABLE_IRQ(); return val; }
void sem_up(struct sem_s* sem) { DISABLE_IRQ(); if (sem->waiting > 0) { // We take the first waiting process struct waiting_process* first_process = sem->queue; // Remove it from the top of the waiting list sem->queue = first_process->next; sem->waiting -= 1; // Put the process back in the active list put_back(first_process->process); // And free the allocated memory to its position in the queue malloc_free((uint32_t*) first_process); } else { sem->val += 1; } ENABLE_IRQ(); }
void main() { uint32_t timestamp; DISABLE_IRQ(); hal_clk_init(); sys_tick_init(); ENABLE_IRQ(); sx1276_init(FSK, NULL); //Frequency 433.4MHz sx1276_fsk_set_frf(433400000); //Fdev 25KHz sx1276_fsk_set_fdev(25000); //Bitrate 10KHz sx1276_fsk_set_bitrate(10000); //Set RxBw depends on bitrate and fdev sx1276_set_rxbw(25000, 10000); sx1276_write(0x10,0xFF); //Disable AGC, set G1 sx1276_write(0x0C,0x20); sx1276_write(0x0D,0x00); sx1276_fsk_rx_test_mode(); timestamp = millis(); while(1){ if( millis() - timestamp > 1000){ timestamp = millis(); led_blink(LED0,100); } led_evt(); } }
void sem_down(struct sem_s* sem) { DISABLE_IRQ(); if (sem->val <= 0) { // Initializing "wait_proc" struct waiting_process* wait_proc = (struct waiting_process*) malloc_alloc(sizeof(struct waiting_process)); wait_proc->process = current_process; wait_proc->next = 0; // If the waiting queue is empty, we put our process as the first (and only) waiting element if (sem->waiting == 0) { sem->last_process = wait_proc; sem->queue = wait_proc; } // Otherwise we put it at the end of the queue else { sem->last_process->next = wait_proc; sem->last_process = wait_proc; } sem->waiting += 1; // TODO : Marche pas si c'est le dernier process de sa queue // ... 'va juste changer la valeur de current_process->schedule_queue move_process(current_process, ¤t_process->schedule_queue, waiting) current_process->state = WAITING; ENABLE_IRQ(); // TODO : Schedule instead of doing a while while(current_process->state== WAITING){ //DO NOTHING } } else { sem->val -= 1; ENABLE_IRQ(); } }
void TimerStart( TimerEvent_t *obj ) { uint32_t elapsedTime = 0; BACKUP_PRIMASK(); DISABLE_IRQ( ); if( ( obj == NULL ) || ( TimerExists( obj ) == true ) ) { RESTORE_PRIMASK( ); return; } obj->Timestamp = obj->ReloadValue; obj->IsRunning = false; if( TimerListHead == NULL ) { HW_RTC_SetTimerContext( ); TimerInsertNewHeadTimer( obj ); // insert a timeout at now+obj->Timestamp } else { elapsedTime = HW_RTC_GetTimerElapsedTime( ); obj->Timestamp += elapsedTime; if( obj->Timestamp < TimerListHead->Timestamp ) { TimerInsertNewHeadTimer( obj); } else { TimerInsertTimer( obj); } } RESTORE_PRIMASK( ); }
/* We have a good packet(s), get it/them out of the buffers. */ static void bionet_poll_rx(struct net_device *dev) { struct net_local *lp = netdev_priv(dev); int boguscount = 10; int pkt_len, status; unsigned long flags; local_irq_save(flags); /* ++roman: Take care at locking the ST-DMA... This must be done with ints * off, since otherwise an int could slip in between the question and the * locking itself, and then we'd go to sleep... And locking itself is * necessary to keep the floppy_change timer from working with ST-DMA * registers. */ if (stdma_islocked()) { local_irq_restore(flags); return; } stdma_lock(bionet_intr, NULL); DISABLE_IRQ(); local_irq_restore(flags); if( lp->poll_time < MAX_POLL_TIME ) lp->poll_time++; while(boguscount--) { status = get_frame((unsigned long)phys_nic_packet, 0); if( status == 0 ) break; /* Good packet... */ dma_cache_maintenance((unsigned long)phys_nic_packet, 1520, 0); pkt_len = (nic_packet->l_hi << 8) | nic_packet->l_lo; lp->poll_time = bionet_min_poll_time; /* fast poll */ if( pkt_len >= 60 && pkt_len <= 1520 ) { /* ^^^^ war 1514 KHL */ /* Malloc up new buffer. */ struct sk_buff *skb = dev_alloc_skb( pkt_len + 2 ); if (skb == NULL) { printk("%s: Memory squeeze, dropping packet.\n", dev->name); lp->stats.rx_dropped++; break; } skb->dev = dev; skb_reserve( skb, 2 ); /* 16 Byte align */ skb_put( skb, pkt_len ); /* make room */ /* 'skb->data' points to the start of sk_buff data area. */ memcpy(skb->data, nic_packet->buffer, pkt_len); skb->protocol = eth_type_trans( skb, dev ); netif_rx(skb); dev->last_rx = jiffies; lp->stats.rx_packets++; lp->stats.rx_bytes+=pkt_len; /* If any worth-while packets have been received, dev_rint() has done a mark_bh(INET_BH) for us and will work on them when we get to the bottom-half routine. */ if (bionet_debug >1) { u_char *data = nic_packet->buffer, *p; int i; printk( "%s: RX pkt type 0x%4x from ", dev->name, ((u_short *)data)[6]); for( p = &data[6], i = 0; i < 6; i++ ) printk("%02x%s", *p++,i != 5 ? ":" : "" ); printk(" to "); for( p = data, i = 0; i < 6; i++ ) printk("%02x%s", *p++,i != 5 ? ":" : "" "\n" ); printk( "%s: ", dev->name ); printk(" data %02x%02x %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x" " %02x%02x%02x%02x len %d\n", data[12], data[13], data[14], data[15], data[16], data[17], data[18], data[19], data[20], data[21], data[22], data[23], data[24], data[25], data[26], data[27], data[28], data[29], data[30], data[31], data[32], data[33], pkt_len ); } } else { printk(" Packet has wrong length: %04d bytes\n", pkt_len); lp->stats.rx_errors++; } } stdma_release(); ENABLE_IRQ(); return; }
void init(void) { //disable interrupts DISABLE_IRQ(); //init BOD LPC_SYSCON->BODCTRL = (2<<0)|(1<<4); //2.35V - 2.43V //set power down config LPC_SYSCON->PDRUNCFG &= ~(1<<4); //enable ADC //init system AHB LPC_SYSCON->SYSAHBCLKDIV = 0x00000001; //clock divider #define AHB_WDT (1<<15) #define AHB_CT16B0 (1<< 7) #define AHB_CT16B1 (1<< 8) #define AHB_CT32B0 (1<< 9) #define AHB_CT32B1 (1<<10) #define AHB_GPIO (1<< 6) #define AHB_IOCON (1<<16) #define AHB_SSP0 (1<<11) #define AHB_SSP1 (1<<18) #define AHB_I2C (1<< 5) #define AHB_UART (1<<12) #define AHB_ADC (1<<13) LPC_SYSCON->SYSAHBCLKCTRL = 0x1F | AHB_CT16B1 | AHB_GPIO | AHB_IOCON | AHB_ADC; //CT16 = PWM for backlight //init pins GPIO_PORT(SS_PORT)->DIR &= (1<<SS_PIN); IOCON_SETPIN(SS_PORT, SS_PIN, IOCON_PULLUP); IOCON_SETPIN(UART_PORT, RX_PIN, IOCON_PULLUP); IOCON_SETPIN(SPI_PORT, MOSI_PIN, IOCON_PULLUP); GPIO_PORT(IO_PORT)->DIR &= (1<<IO_PIN); IOCON_SETPIN(IO_PORT, IO_PIN, IOCON_PULLUP); GPIO_PORT(LED_PORT)->DIR |= (1<<LED_PIN); GPIO_CLRPIN(LED_PORT, LED_PIN); GPIO_PORT(PWM_PORT)->DIR |= (1<<PWM_PIN); GPIO_CLRPIN(PWM_PORT, PWM_PIN); //init PWM for backlight // LPC_IOCON->PIO1_9 = (0x1<<0); //PIO1_9/CT16B1MAT0 -> PWM (set in set_pwm()) LPC_TMR16B1->TC = 0; LPC_TMR16B1->PR = 0; //no prescale LPC_TMR16B1->PC = 0; LPC_TMR16B1->CTCR = 0; LPC_TMR16B1->MCR = 0; LPC_TMR16B1->MR0 = ~((0xFFFF*0)/100); //0% LPC_TMR16B1->PWMC = (1<<0); //PWM chn 0 on LPC_TMR16B1->EMR = (1<<0)|(2<<4); //enable PIO1_9/CT16B1MAT0 LPC_TMR16B1->TCR = (1<<0); //enable timer //init adc LPC_ADC->CR = (((sysclock(0)/4000000UL)-1)<< 8) | //4MHz (0<<16) | //burst off (0x0<<17) | //10bit (0x0<<24); //stop //init systick timer ms_ticks = 0; SysTick_Config(sysclock(0) / 1000); //1000 Hz //enable interrupts ENABLE_IRQ(); return; }