void spi_dma_setclock(uint32_t rate)
{
SPI0_CSR0 &= ~SPI_SCBR;
ASSERT((uint8_t)DIV_ROUND(CPU_FREQ, rate));
SPI0_CSR0 |= DIV_ROUND(CPU_FREQ, rate) << SPI_SCBR_SHIFT;
}
static void abb_setup_timings(u32 setup)
{
u32 sys_rate, sr2_cnt, clk_cycles;
/*
* SR2_WTCNT_VALUE is the settling time for the ABB ldo after a
* transition and must be programmed with the correct time at boot.
* The value programmed into the register is the number of SYS_CLK
* clock cycles that match a given wall time profiled for the ldo.
* This value depends on:
* settling time of ldo in micro-seconds (varies per OMAP family),
* of clock cycles per SYS_CLK period (varies per OMAP family),
* the SYS_CLK frequency in MHz (varies per board)
* The formula is:
*
* ldo settling time (in micro-seconds)
* SR2_WTCNT_VALUE = ------------------------------------------
* (# system clock cycles) * (sys_clk period)
*
* Put another way:
*
* SR2_WTCNT_VALUE = settling time / (# SYS_CLK cycles / SYS_CLK rate))
*
* To avoid dividing by zero multiply both "# clock cycles" and
* "settling time" by 10 such that the final result is the one we want.
*/
/* calculate SR2_WTCNT_VALUE */
sys_rate = DIV_ROUND(V_OSCK, 1000000);
clk_cycles = DIV_ROUND(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
sr2_cnt = DIV_ROUND(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
setbits_le32(setup,
sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1));
}
void init_timer(int res_hz)
{
_disable();
if(res_hz > 0) {
int reload_val = DIV_ROUND(OSC_FREQ_HZ, res_hz);
set_timer_reload(reload_val);
tick_interval = DIV_ROUND(1000, res_hz);
ticks_per_dos_intr = DIV_ROUND(65535L, reload_val);
inum = PIT_TIMER_INTR;
prev_timer_intr = _dos_getvect(inum);
_dos_setvect(inum, timer_irq);
} else {
tick_interval = 55;
inum = DOS_TIMER_INTR;
prev_timer_intr = _dos_getvect(inum);
_dos_setvect(inum, dos_timer_intr);
}
_enable();
atexit(cleanup);
}
static int menu_select(struct acpi_processor_power *power)
{
struct menu_device *data = &__get_cpu_var(menu_devices);
int i;
s_time_t io_interval;
/* TBD: Change to 0 if C0(polling mode) support is added later*/
data->last_state_idx = CPUIDLE_DRIVER_STATE_START;
data->exit_us = 0;
/* determine the expected residency time, round up */
data->expected_us = get_sleep_length_us();
data->bucket = which_bucket(data->expected_us);
io_interval = avg_intr_interval_us();
data->latency_factor = DIV_ROUND(
data->latency_factor * (DECAY - 1) + data->measured_us,
DECAY);
/*
* if the correction factor is 0 (eg first time init or cpu hotplug
* etc), we actually want to start out with a unity factor.
*/
if (data->correction_factor[data->bucket] == 0)
data->correction_factor[data->bucket] = RESOLUTION * DECAY;
/* Make sure to round up for half microseconds */
data->predicted_us = DIV_ROUND(
data->expected_us * data->correction_factor[data->bucket],
RESOLUTION * DECAY);
/* find the deepest idle state that satisfies our constraints */
for ( i = CPUIDLE_DRIVER_STATE_START + 1; i < power->count; i++ )
{
struct acpi_processor_cx *s = &power->states[i];
if (s->target_residency > data->predicted_us)
break;
if (s->latency * IO_MULTIPLIER > io_interval)
break;
if (s->latency * LATENCY_MULTIPLIER > data->latency_factor)
break;
/* TBD: we need to check the QoS requirment in future */
data->exit_us = s->latency;
data->last_state_idx = i;
}
return data->last_state_idx;
}
INLINE void tc_setup(uint32_t freq, size_t n_sample)
{
/*
* Compute the sample frequency
* the RC counter will update every MCK/2 (see above)
* so to convert one sample at the user freq we generate
* the trigger every TC_CLK / (numer_of_sample * user_freq)
* where TC_CLK = MCK / 2.
*/
uint32_t rc = DIV_ROUND((CPU_FREQ / 2), n_sample * freq);
DAC_TC_RC = rc;
/* generate the square wave with duty = 50% */
DAC_TC_RA = DIV_ROUND(50 * rc, 100);
}
INLINE void kdbg_hw_init(void)
{
#if CONFIG_KDEBUG_PORT == KDEBUG_PORT_DBGU
/* Disable all DBGU interrupts. */
DBGU_IDR = 0xFFFFFFFF;
/* Reset DBGU */
DBGU_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS);
/* Set baudrate */
DBGU_BRGR = DIV_ROUND(CPU_FREQ, 16 * CONFIG_KDEBUG_BAUDRATE);
/* Set DBGU mode to 8 data bits, no parity and 1 stop bit. */
DBGU_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1;
/* Enable DBGU transmitter. */
DBGU_CR = BV(US_TXEN);
/* Disable PIO on DGBU tx pin. */
PIOA_PDR = BV(DTXD);
PIOA_ASR = BV(DTXD);
#if 0 /* Disable Rx for now */
/* Enable DBGU receiver. */
DBGU_CR = BV(US_RXEN);
/* Disable PIO on DGBU rx pin. */
PIOA_PDR = BV(DRXD);
PIOA_ASR = BV(DRXD);
#endif
#else
#error CONFIG_KDEBUG_PORT should be KDEBUG_PORT_DBGU
#endif /* CONFIG_KDEBUG_PORT == KDEBUG_PORT_DBGU */
}
/**
* Set the baudrate.
*/
void _ser_setbaudrate(unsigned long rate)
{
/* Compute baud-rate period */
uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
UBRR0H = (period) >> 8;
UBRR0L = (period);
}
static void uart3_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
{
/* Compute baud-rate period */
uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
UBRR3H = (period) >> 8;
UBRR3L = (period);
//DB(kprintf("uart3_setbaudrate(rate=%ld): period=%d\n", rate, period);)
}
void cow_sizes(int version, __u64 size, int sectorsize, int align,
int bitmap_offset, unsigned long *bitmap_len_out,
int *data_offset_out)
{
if (version < 3) {
*bitmap_len_out = (size + sectorsize - 1) / (8 * sectorsize);
*data_offset_out = bitmap_offset + *bitmap_len_out;
*data_offset_out = (*data_offset_out + sectorsize - 1) /
sectorsize;
*data_offset_out *= sectorsize;
}
else {
*bitmap_len_out = DIV_ROUND(size, sectorsize);
*bitmap_len_out = DIV_ROUND(*bitmap_len_out, 8);
*data_offset_out = bitmap_offset + *bitmap_len_out;
*data_offset_out = ROUND_UP(*data_offset_out, align);
}
}
static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
{
/* Compute baud-rate period */
uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
#if !CPU_AVR_ATMEGA103
UBRR0H = (period) >> 8;
#endif
UBRR0L = (period);
//DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
}
static void Set_image_quality(MESSAGE *msg_in, MESSAGE *msg_out)
{
APP_INFO("==========RECEIVE IMAGE QUALITY GETTING REQUEST!==========");
IMG_QUALITY* pimg = (IMG_QUALITY *)(msg_in->data);
iq_map.mctf_strength = pimg->denoise_filter;
iq_map.local_exposure_mode = pimg->exposure_mode;
iq_map.ae.shutter_time_min = DIV_ROUND(512000000, pimg->shutter_min);
/******29.97 correction*******/
if(iq_map.ae.shutter_time_min == 17655172) {
iq_map.ae.shutter_time_min = 17083750;
}
iq_map.ae.shutter_time_max = DIV_ROUND(512000000, pimg->shutter_max);
/******29.97 correction*******/
if(iq_map.ae.shutter_time_max == 17655172) {
iq_map.ae.shutter_time_max = 17083750;
}
iq_map.ae.anti_flicker_mode = pimg->antiflicker;
iq_map.ae.sensor_gain_max = pimg->max_gain;
iq_map.ae_target_ratio = pimg->exposure_target_factor;
awb_map.wb_mode = pimg->wbc;
image_map.saturation = pimg->saturation;
image_map.brightness = pimg->brightness;
image_map.contrast = pimg->contrast;
image_map.sharpness = pimg->shapenness;
iq_map.dc_iris_enable = pimg->dc_iris_mode;
iq_map.back_light_comp_enable = pimg->backlight_comp;
iq_map.day_night_mode = pimg->dn_mode;
if(set_image_param("IMAGE") < 0) {
msg_out->cmd_id = SET_IQ;
msg_out->status = STATUS_FAILURE;
} else {
msg_out->cmd_id = SET_IQ;
msg_out->status = STATUS_SUCCESS;
}
}
static uint16_t uart_period(unsigned long bps)
{
uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, bps) - 1;
#ifdef _DEBUG
long skew = bps - (long)(period + 1) * (CPU_FREQ / 16);
/* 8N1 is reliable within 3% skew */
if ((unsigned long)ABS(skew) > bps / (100 / 3))
kprintf("Baudrate off by %ldbps\n", skew);
#endif
//DB(kprintf("uart_period(bps=%lu): period=%u\n", bps, period);)
return period;
}
/* Enable/configure/disable the periodic timer based on the RTC_PIE and
* RTC_RATE_SELECT settings */
static void rtc_timer_update(RTCState *s)
{
int period_code, period, delta;
struct vcpu *v = vrtc_vcpu(s);
ASSERT(spin_is_locked(&s->lock));
s->pt_dead_ticks = 0;
period_code = s->hw.cmos_data[RTC_REG_A] & RTC_RATE_SELECT;
switch ( s->hw.cmos_data[RTC_REG_A] & RTC_DIV_CTL )
{
case RTC_REF_CLCK_32KHZ:
if ( (period_code != 0) && (period_code <= 2) )
period_code += 7;
/* fall through */
case RTC_REF_CLCK_1MHZ:
case RTC_REF_CLCK_4MHZ:
if ( period_code != 0 )
{
period = 1 << (period_code - 1); /* period in 32 Khz cycles */
period = DIV_ROUND(period * 1000000000ULL, 32768); /* in ns */
if ( period != s->period )
{
s_time_t now = NOW();
s->period = period;
if ( v->domain->arch.hvm_domain.params[HVM_PARAM_VPT_ALIGN] )
delta = 0;
else
delta = period - ((now - s->start_time) % period);
if ( s->hw.cmos_data[RTC_REG_B] & RTC_PIE )
{
TRACE_2D(TRC_HVM_EMUL_RTC_START_TIMER, delta, period);
create_periodic_time(v, &s->pt, delta, period,
RTC_IRQ, rtc_pf_callback, s);
}
else
s->check_ticks_since = now;
}
break;
}
/* fall through */
default:
TRACE_0D(TRC_HVM_EMUL_RTC_STOP_TIMER);
destroy_periodic_time(&s->pt);
s->period = 0;
break;
}
}
INLINE void kdbg_hw_init(void)
{
#if CONFIG_KDEBUG_PORT == 666
SER_BITBANG_INIT;
#else /* CONFIG_KDEBUG_PORT != 666 */
/* Compute the baud rate */
uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, CONFIG_KDEBUG_BAUDRATE) - 1;
#if (CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281)
#if CONFIG_KDEBUG_PORT == 0
UBRR0H = (uint8_t)(period>>8);
UBRR0L = (uint8_t)period;
KDBG_UART0_BUS_INIT;
#elif CONFIG_KDEBUG_PORT == 1
UBRR1H = (uint8_t)(period>>8);
UBRR1L = (uint8_t)period;
KDBG_UART1_BUS_INIT;
#else
#error CONFIG_KDEBUG_PORT must be either 0 or 1
#endif
#elif CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
#if CONFIG_KDEBUG_PORT == 0
UBRR0H = (uint8_t)(period>>8);
UBRR0L = (uint8_t)period;
KDBG_UART0_BUS_INIT;
#else
#error Only CONFIG_KDEBUG_PORT 0 is supported for this cpu
#endif
#elif CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA32
#if CONFIG_KDEBUG_PORT == 0
UBRRH = (uint8_t)(period>>8);
UBRRL = (uint8_t)period;
KDBG_UART0_BUS_INIT;
#else
#error Only CONFIG_KDEBUG_PORT 0 is supported for this cpu
#endif
#elif CPU_AVR_ATMEGA103
#if CONFIG_KDEBUG_PORT == 0
UBRR = (uint8_t)period;
KDBG_UART0_BUS_INIT;
#else
#error Only CONFIG_KDEBUG_PORT 0 is supported for this cpu
#endif
#else
#error Unknown CPU
#endif
#endif /* CONFIG_KDEBUG_PORT == 666 */
}
/* Enable/configure/disable the periodic timer based on the RTC_PIE and
* RTC_RATE_SELECT settings */
static void rtc_timer_update(RTCState *s)
{
int period_code, period, delta;
struct vcpu *v = vrtc_vcpu(s);
ASSERT(spin_is_locked(&s->lock));
s->pt_dead_ticks = 0;
period_code = s->hw.cmos_data[RTC_REG_A] & RTC_RATE_SELECT;
switch ( s->hw.cmos_data[RTC_REG_A] & RTC_DIV_CTL )
{
case RTC_REF_CLCK_32KHZ:
if ( (period_code != 0) && (period_code <= 2) )
period_code += 7;
/* fall through */
case RTC_REF_CLCK_1MHZ:
case RTC_REF_CLCK_4MHZ:
if ( period_code != 0 )
{
if ( period_code != s->pt_code )
{
s->pt_code = period_code;
period = 1 << (period_code - 1); /* period in 32 Khz cycles */
period = DIV_ROUND(period * 1000000000ULL, 32768); /* in ns */
if ( v->domain->arch.hvm_domain.params[HVM_PARAM_VPT_ALIGN] )
delta = 0;
else
delta = period - ((NOW() - s->start_time) % period);
create_periodic_time(v, &s->pt, delta, period,
RTC_IRQ, NULL, s);
}
break;
}
/* fall through */
default:
destroy_periodic_time(&s->pt);
s->pt_code = 0;
break;
}
}
/* Enable/configure/disable the periodic timer based on the RTC_PIE and
* RTC_RATE_SELECT settings */
static void rtc_timer_update(RTCState *s)
{
int period_code, period;
struct vcpu *v = vrtc_vcpu(s);
ASSERT(spin_is_locked(&s->lock));
period_code = s->hw.cmos_data[RTC_REG_A] & RTC_RATE_SELECT;
if ( (period_code != 0) && (s->hw.cmos_data[RTC_REG_B] & RTC_PIE) )
{
if ( period_code <= 2 )
period_code += 7;
period = 1 << (period_code - 1); /* period in 32 Khz cycles */
period = DIV_ROUND((period * 1000000000ULL), 32768); /* period in ns */
create_periodic_time(v, &s->pt, period, period, RTC_IRQ,
rtc_periodic_cb, s);
}
else
{
destroy_periodic_time(&s->pt);
}
}
err = -EINVAL;
kfree(clock);
goto failed_clock;
}
clock_divider = (u32 *) of_get_property(dev->of_node, \
"fsl,flexcan-clock-divider", NULL);
if (clock_divider == NULL) {
dev_err(dev, "Cannot find fsl,flexcan-clock-divider \
property\n");
err = -EINVAL;
kfree(clock);
goto failed_clock;
}
clock->rate = DIV_ROUND(*clock_freq / *clock_divider, 1000) * 1000;
DBG(KERN_INFO "clock-frequency is %lu in line %d in function %s \r\n",
clock->rate, __LINE__, __func__);
return clock;
failed_clock:
return ERR_PTR(err);
}
static void flexcan_of_resource_init(struct flexcan_interface *flexcan_cb)
{
flexcan_cb->read = flexcan_read;
flexcan_cb->write = flexcan_write;
flexcan_cb->clk_enable = NULL;
flexcan_cb->clk_disable = NULL;
flexcan_cb->clk_get_rate = flexcan_get_clk_rate;
PJ_DEF(pj_status_t) pjmedia_aud_test( const pjmedia_aud_param *param,
pjmedia_aud_test_results *result)
{
pj_status_t status = PJ_SUCCESS;
pjmedia_aud_stream *strm;
struct test_data test_data;
unsigned ptime, tmp;
/*
* Init test parameters
*/
pj_bzero(&test_data, sizeof(test_data));
test_data.param = param;
test_data.result = result;
test_data.pool = pj_pool_create(pjmedia_aud_subsys_get_pool_factory(),
"audtest", 1000, 1000, NULL);
pj_mutex_create_simple(test_data.pool, "sndtest", &test_data.mutex);
/*
* Open device.
*/
status = pjmedia_aud_stream_create(test_data.param, &rec_cb, &play_cb,
&test_data, &strm);
if (status != PJ_SUCCESS) {
app_perror("Unable to open device", status);
pj_pool_release(test_data.pool);
return status;
}
/* Sleep for a while to let sound device "settles" */
pj_thread_sleep(200);
/*
* Start the stream.
*/
status = pjmedia_aud_stream_start(strm);
if (status != PJ_SUCCESS) {
app_perror("Unable to start capture stream", status);
pjmedia_aud_stream_destroy(strm);
pj_pool_release(test_data.pool);
return status;
}
PJ_LOG(3,(THIS_FILE,
" Please wait while test is in progress (~%d secs)..",
(DURATION+SKIP_DURATION)/1000));
/* Let the stream runs for few msec/sec to get stable result.
* (capture normally begins with frames available simultaneously).
*/
pj_thread_sleep(SKIP_DURATION);
/* Begin gather data */
test_data.running = 1;
/*
* Let the test runs for a while.
*/
pj_thread_sleep(DURATION);
/*
* Close stream.
*/
test_data.running = 0;
pjmedia_aud_stream_destroy(strm);
pj_pool_release(test_data.pool);
/*
* Gather results
*/
ptime = param->samples_per_frame * 1000 / param->clock_rate;
tmp = pj_math_stat_get_stddev(&test_data.capture_data.delay);
result->rec.frame_cnt = test_data.capture_data.delay.n;
result->rec.min_interval = DIV_ROUND(test_data.capture_data.delay.min, 1000);
result->rec.max_interval = DIV_ROUND(test_data.capture_data.delay.max, 1000);
result->rec.avg_interval = DIV_ROUND(test_data.capture_data.delay.mean, 1000);
result->rec.dev_interval = DIV_ROUND(tmp, 1000);
result->rec.max_burst = DIV_ROUND_UP(result->rec.max_interval, ptime);
tmp = pj_math_stat_get_stddev(&test_data.playback_data.delay);
result->play.frame_cnt = test_data.playback_data.delay.n;
result->play.min_interval = DIV_ROUND(test_data.playback_data.delay.min, 1000);
result->play.max_interval = DIV_ROUND(test_data.playback_data.delay.max, 1000);
result->play.avg_interval = DIV_ROUND(test_data.capture_data.delay.mean, 1000);
result->play.dev_interval = DIV_ROUND(tmp, 1000);
result->play.max_burst = DIV_ROUND_UP(result->play.max_interval, ptime);
/* Check drifting */
if (param->dir == PJMEDIA_DIR_CAPTURE_PLAYBACK) {
int end_diff, start_diff, drift;
end_diff = test_data.capture_data.last_timestamp -
test_data.playback_data.last_timestamp;
start_diff = test_data.capture_data.first_timestamp-
test_data.playback_data.first_timestamp;
drift = end_diff > start_diff? end_diff - start_diff :
start_diff - end_diff;
/* Allow one frame tolerance for clock drift detection */
if (drift < (int)param->samples_per_frame) {
result->rec_drift_per_sec = 0;
} else {
unsigned msec_dur;
msec_dur = (test_data.capture_data.last_timestamp -
test_data.capture_data.first_timestamp) * 1000 /
test_data.param->clock_rate;
result->rec_drift_per_sec = drift * 1000 / msec_dur;
}
}
return test_data.has_error? PJ_EUNKNOWN : PJ_SUCCESS;
}
int init_param(int argc, char **argv)
{
int ch;
int option_index = 0;
u16 width =0;
u16 height = 0;
int mode = 0;
while ((ch = getopt_long(argc, argv, short_options, long_options, &option_index)) != -1)
{
switch (ch) {
case 't':
if (strcmp(optarg,"es") == 0){
recordType = 0;
}else if (strcmp(optarg,"ts") == 0){
recordType = 1;
}else if (strcmp(optarg,"mp4") == 0){
recordType = 2;
} else{
return -1;
}
break;
case 'A':
current_stream =0;
break;
case 'B':
current_stream = 1;
break;
case 'C':
current_stream = 2;
break;
case 'D':
current_stream = 3;
break;
case 'h':
if (get_encode_resolution(optarg, &width, &height) < 0)
return -1;
if (current_stream == -1) {
return -1;
}
specify_enc_format_flag[current_stream] = 1;
encode_format[current_stream]->type = IAV_ENCODE_H264;
encode_format[current_stream]->width = width;
encode_format[current_stream]->height = height;
break;
case 'e':
if (current_stream == -1) {
return -1;
}
encode_stream |= 1<<current_stream;
break;
case 'M':
if (current_stream == -1) {
return -1;
}
specify_h264_config_flag[current_stream] = 1;
h264_config[current_stream]->M = atoi(optarg);
break;
case 'N':
if (current_stream == -1) {
return -1;
}
specify_h264_config_flag[current_stream] = 1;
h264_config[current_stream]->N = atoi(optarg);
break;
case SPECIFY_GOP_IDR:
if (current_stream == -1) {
return -1;
}
specify_h264_config_flag[current_stream] = 1;
h264_config[current_stream]->idr_interval = atoi(optarg);
break;
case SPECIFY_CAVLC:
if (current_stream == -1) {
return -1;
}
h264_config[current_stream]->profile = atoi(optarg);
if (h264_config[current_stream]->profile != 0 &&
h264_config[current_stream]->profile != 1) {
return -1;
}
break;
case SPECIFY_CBR_BITRATE:
specify_h264_config_flag[current_stream] = 1;
h264_config[current_stream]->brc_mode = 0;
h264_config[current_stream]->cbr_avg_bps = atoi(optarg);
break;
case 'V':
if (get_vout_mode(optarg, &mode) < 0)
return -1;
specify_vout_mode_flag = 1;
vout_mode = mode;
break;
case SPECIFY_CVBS_VOUT:
specify_vout_type_flag = 1;
vout_type = AMBA_VOUT_SINK_TYPE_CVBS;
break;
case SPECIFY_HDMI_VOUT:
specify_vout_type_flag = 1;
vout_type = AMBA_VOUT_SINK_TYPE_HDMI;
break;
case 'i':
if (get_vout_mode(optarg, &mode) < 0)
return -1;
specify_vin_mode_flag = 1;
vin_mode = mode;
break;
case 'S':
specify_source_flag = 1;
source = atoi(optarg);
break;
case 'F':
specify_framerate_flag = 1;
framerate = atoi(optarg);
switch (framerate) {
case 0:
framerate = AMBA_VIDEO_FPS_AUTO;
break;
case 0x10000:
framerate = AMBA_VIDEO_FPS_29_97;
break;
case 0x10001:
framerate = AMBA_VIDEO_FPS_59_94;
break;
case 0x10003:
framerate = AMBA_VIDEO_FPS_12_5;
break;
case 0x10006:
framerate = AMBA_VIDEO_FPS_7_5;
break;
default:
framerate = DIV_ROUND(512000000, framerate);
break;
}
break;
case 'f':
specify_filename = 1;
strcpy(filename,optarg);
break;
case 'a':
if(strcmp(optarg,"aac") == 0)
audioType = 1;
else if(strcmp(optarg, "bpcm") == 0)
audioType = 2;
else if(strcmp(optarg,"no") == 0)
audioType =0; //no audio
break;
case SPECIFY_FILE_SIZE:
max_file_size = atoi(optarg);
if (max_file_size > 2048 || max_file_size < 1) {
return -1;
}
break;
case SPECIFY_FRAME_CNT:
max_frame_cnt = atoi(optarg);
break;
case SPECIFY_SAMPLE_FREQ:
change_sample_freq_flag = 1;
audio_sample_freq = atoi(optarg);
break;
case SPECIFY_CHANNEL_NUM:
audio_channel_num = atoi(optarg);
break;
case SPECIFY_AAC_BITRATE:
aac_bitrate = atoi(optarg);
if (aac_bitrate <= 0)
return -1;
break;
case 'l':
low_delay_flag = true;
break;
default:
return -1;
}
}
if ((specify_vin_mode_flag == 0) &&
(specify_vout_mode_flag == 0) &&
(specify_vout_type_flag == 0) &&
(current_stream == -1)){
specify_vout_mode_flag = 1;
vout_mode = default_vout_mode;
specify_vout_type_flag = 1;
vout_type = default_vout_type;
specify_vin_mode_flag = 1;
encode_stream = 0x1;
specify_enc_format_flag[0] = 1;
encode_format[0]->type = IAV_ENCODE_H264;
}
if (!specify_filename) {
strcpy(filename,default_filename);
}
return 0;
}
