Exemple #1
0
int a3000_detect(Scsi_Host_Template *tpnt)
{
    static unsigned char called = 0;

    if (called)
	return 0;

    if  (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(A3000_SCSI))
	return 0;

    tpnt->proc_dir = &proc_scsi_a3000;
    tpnt->proc_info = &wd33c93_proc_info;

    a3000_host = scsi_register (tpnt, sizeof(struct WD33C93_hostdata));
    a3000_host->base = (unsigned char *)ZTWO_VADDR(0xDD0000);
    a3000_host->irq = IRQ_AMIGA_PORTS & ~IRQ_MACHSPEC;
    DMA(a3000_host)->DAWR = DAWR_A3000;
    wd33c93_init(a3000_host, (wd33c93_regs *)&(DMA(a3000_host)->SASR),
		 dma_setup, dma_stop, WD33C93_FS_12_15);
    request_irq(IRQ_AMIGA_PORTS, a3000_intr, 0, "A3000 SCSI", a3000_intr);
    DMA(a3000_host)->CNTR = CNTR_PDMD | CNTR_INTEN;
    called = 1;

    return 1;
}
Exemple #2
0
static int dma_setup(struct scsi_cmnd *cmd, int dir_in)
{
    unsigned short cntr = CNTR_PDMD | CNTR_INTEN;
    unsigned long addr = virt_to_bus(cmd->SCp.ptr);

    /*
     * if the physical address has the wrong alignment, or if
     * physical address is bad, or if it is a write and at the
     * end of a physical memory chunk, then allocate a bounce
     * buffer
     */
    if (addr & A3000_XFER_MASK)
    {
	HDATA(a3000_host)->dma_bounce_len = (cmd->SCp.this_residual + 511)
	    & ~0x1ff;
	HDATA(a3000_host)->dma_bounce_buffer =
	    kmalloc (HDATA(a3000_host)->dma_bounce_len, GFP_KERNEL);
	
	/* can't allocate memory; use PIO */
	if (!HDATA(a3000_host)->dma_bounce_buffer) {
	    HDATA(a3000_host)->dma_bounce_len = 0;
	    return 1;
	}

	if (!dir_in) {
	    /* copy to bounce buffer for a write */
	    memcpy (HDATA(a3000_host)->dma_bounce_buffer,
		cmd->SCp.ptr, cmd->SCp.this_residual);
	}

	addr = virt_to_bus(HDATA(a3000_host)->dma_bounce_buffer);
    }

    /* setup dma direction */
    if (!dir_in)
	cntr |= CNTR_DDIR;

    /* remember direction */
    HDATA(a3000_host)->dma_dir = dir_in;

    DMA(a3000_host)->CNTR = cntr;

    /* setup DMA *physical* address */
    DMA(a3000_host)->ACR = addr;

    if (dir_in)
  	/* invalidate any cache */
	cache_clear (addr, cmd->SCp.this_residual);
    else
	/* push any dirty cache */
	cache_push (addr, cmd->SCp.this_residual);

    /* start DMA */
    mb();			/* make sure setup is completed */
    DMA(a3000_host)->ST_DMA = 1;
    mb();			/* make sure DMA has started before next IO */

    /* return success */
    return 0;
}
static int __init a2091_detect(struct scsi_host_template *tpnt)
{
    static unsigned char called = 0;
    struct Scsi_Host *instance;
    unsigned long address;
    struct zorro_dev *z = NULL;
    wd33c93_regs regs;
    int num_a2091 = 0;

    if (!MACH_IS_AMIGA || called)
	return 0;
    called = 1;

    tpnt->proc_name = "A2091";
    tpnt->proc_info = &wd33c93_proc_info;

    while ((z = zorro_find_device(ZORRO_WILDCARD, z))) {
	if (z->id != ZORRO_PROD_CBM_A590_A2091_1 &&
	    z->id != ZORRO_PROD_CBM_A590_A2091_2)
	    continue;
	address = z->resource.start;
	if (!request_mem_region(address, 256, "wd33c93"))
	    continue;

	instance = scsi_register (tpnt, sizeof (struct WD33C93_hostdata));
	if (instance == NULL)
	    goto release;
	instance->base = ZTWO_VADDR(address);
	instance->irq = IRQ_AMIGA_PORTS;
	instance->unique_id = z->slotaddr;
	DMA(instance)->DAWR = DAWR_A2091;
	regs.SASR = &(DMA(instance)->SASR);
	regs.SCMD = &(DMA(instance)->SCMD);
	HDATA(instance)->no_sync = 0xff;
	HDATA(instance)->fast = 0;
	HDATA(instance)->dma_mode = CTRL_DMA;
	wd33c93_init(instance, regs, dma_setup, dma_stop, WD33C93_FS_8_10);
	if (request_irq(IRQ_AMIGA_PORTS, a2091_intr, IRQF_SHARED, "A2091 SCSI",
			instance))
	    goto unregister;
	DMA(instance)->CNTR = CNTR_PDMD | CNTR_INTEN;
	num_a2091++;
	continue;

unregister:
	scsi_unregister(instance);
	wd33c93_release();
release:
	release_mem_region(address, 256);
    }

    return num_a2091;
}
Exemple #4
0
/* this avoids blocking without using non-blocking i/o */
static int wait_for_it(int sd, int timeoutseconds)
{
	fd_set readfds;
	struct timeval tv;
	int ready_descriptors;
    int maxfd;
    int xfd;
    struct timeval time_now;
    struct timeval time_out;

    gettimeofday(&time_now, NULL);
    memcpy(&time_out, &time_now, sizeof(struct timeval));
    time_out.tv_sec += timeoutseconds;

    xfd = x_socket();
    maxfd = max(sd, xfd);

	do {
        do {
            ProcessPendingEvents();

            gettimeofday(&time_now, NULL);
            tv.tv_sec = max(time_out.tv_sec - time_now.tv_sec + 1, (time_t) 0); /* sloppy, but bfd */
            tv.tv_usec = 0;
            /* select will return if we have X stuff or we have comm stuff on sd */
            FD_ZERO(&readfds);
            FD_SET(sd, &readfds);
            // FD_SET(xfd, &readfds);
            ready_descriptors = select(maxfd + 1, &readfds, NULL, NULL, &tv);
            // DMA(DEBUG_INFO,
            //    "select %d/%d returned %d descriptor, %d\n",
            //    sd, timeoutseconds, ready_descriptors, FD_ISSET(sd, &readfds));

        } while(tv.tv_sec > 0 && (!FD_ISSET(sd, &readfds) || (errno == EINTR && ready_descriptors == -1)));

        FD_ZERO(&readfds);
        FD_SET(sd, &readfds);
        tv.tv_sec = 0; tv.tv_usec = 0;
        ready_descriptors = select(sd + 1, &readfds, NULL, NULL, &tv);
	}
	while (ready_descriptors == -1 && errno == EINTR);
	if (ready_descriptors == 0) {
		DMA(DEBUG_INFO,
			"select timed out after %d seconds on socket: %d\n",
			timeoutseconds, sd);
		return (0);
	} else if (ready_descriptors == -1) {
		DMA(DEBUG_ERROR,
			"select failed on socket %d: %s\n", sd, strerror(errno));
		return (0);
	}
	return (FD_ISSET(sd, &readfds));
}
Exemple #5
0
void UART_send_msg_to_host(unsigned descriptor, unsigned payload_len, uint8_t *buf)
{
    unsigned len;

    while (host_uart_status & UART_STATUS_TX_BUSY);
    host_uart_status |= UART_STATUS_TX_BUSY;

    DMA(DMA_HOST_UART_TX, CTL) &= ~DMAEN; // should already be disabled, but just in case

    len = write_header(buf, UART_IDENTIFIER_USB, descriptor, payload_len);

    DMA(DMA_HOST_UART_TX, SA) = (__DMA_ACCESS_REG__)buf;
    DMA(DMA_HOST_UART_TX, SZ) = len;

    DMA(DMA_HOST_UART_TX, CTL) |= DMAEN;
}
Exemple #6
0
static void ask_user_for_password( /*@notnull@ */ Pop3 pc, int bFlushCache)
{
	/* see if we already have a password, as provided in the config file, or
	   already requested from the user. */
	if (PCU.interactive_password) {
		if (strlen(PCU.password) == 0) {
			/* we need to grab the password from the user. */
			char *password;
			IMAP_DM(pc, DEBUG_INFO, "asking for password %d\n",
					bFlushCache);
			password =
				passwordFor(PCU.userName, PCU.serverName, pc, bFlushCache);
			if (password != NULL) {
				if (strlen(password) + 1 > BUF_SMALL) {
					DMA(DEBUG_ERROR, "Password is too long.\n");
					memset(PCU.password, 0, BUF_SMALL - 1);
				} else {
					strncpy(PCU.password, password, BUF_SMALL - 1);
					PCU.password_len = strlen(PCU.password);
				}
				free(password);
				ENFROB(PCU.password);
			}
		}
	}
}
Exemple #7
0
static void slave(void) {
  int slave_id = core_id-1;

  while (slave_mpb[slave_id]->packet.cmd != CMD_START) {
    /* spin until start packet arrives */
  }
  /* respond to start packet */
  slave_mpb[slave_id]->row.cmd = CMD_START;
  DMA(0, &(master_mpb->slave[slave_id].row),
      &(slave_mpb[slave_id]->row),
      sizeof(struct rowbuf_t));

  /* loop while new packets arrive */
  for (;;) {
    while (slave_mpb[slave_id]->packet.cmd <= CMD_NULL
           && slave_mpb[slave_id]->packet.cmd != CMD_STOP) {
      /* spin until packet arrives */
    }
    /* terminate if stop packet arrives */
    if (slave_mpb[slave_id]->packet.cmd == CMD_STOP) {
      break;
    }

    /* copy packet to local memory */
	struct packet_t _SPM *ptr = &(slave_mpb[slave_id]->packet);
    struct packet_t p __attribute__ ((aligned (4)));
	p.yval = ptr->yval;
	p.xstart = ptr->xstart;
	p.xend = ptr->xend;
	p.xstep = ptr->xstep;
	p.cmd = ptr->cmd;
    /* clear command */
    slave_mpb[slave_id]->packet.cmd = CMD_NULL;
    /* compute pixels for one row */
    int x, idx;
    for (idx = 0, x = p.xstart; x < p.xend; idx++, x += p.xstep) {
      int val = do_iter(x, p.yval, MAX_SQUARE, MAX_ITER);
      slave_mpb[slave_id]->row.data[idx] = map[val & 0x3f];
    }
    /* send row */
    slave_mpb[slave_id]->row.cmd = p.cmd;
    DMA(0, &(master_mpb->slave[slave_id].row),
        &(slave_mpb[slave_id]->row),
        sizeof(struct rowbuf_t));
  }
}
Exemple #8
0
int a3000_release(struct Scsi_Host *instance)
{
    wd33c93_release();
    DMA(instance)->CNTR = 0;
    release_mem_region(0xDD0000, 256);
    free_irq(IRQ_AMIGA_PORTS, a3000_intr);
    return 1;
}
Exemple #9
0
int a3000_release(struct Scsi_Host *instance)
{
#ifdef MODULE
	DMA(instance)->CNTR = 0;
	free_irq(IRQ_AMIGA_PORTS, a3000_intr);
#endif
	return 1;
}
static int a2091_release(struct Scsi_Host *instance)
{
#ifdef MODULE
	DMA(instance)->CNTR = 0;
	release_mem_region(ZTWO_PADDR(instance->base), 256);
	free_irq(IRQ_AMIGA_PORTS, instance);
	wd33c93_release();
#endif
	return 1;
}
Exemple #11
0
int __init a3000_detect(struct scsi_host_template *tpnt)
{
    wd33c93_regs regs;

    if  (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(A3000_SCSI))
	return 0;
    if (!request_mem_region(0xDD0000, 256, "wd33c93"))
	return 0;

    tpnt->proc_name = "A3000";
    tpnt->proc_info = &wd33c93_proc_info;

    a3000_host = scsi_register (tpnt, sizeof(struct WD33C93_hostdata));
    if (a3000_host == NULL)
	goto fail_register;

    a3000_host->base = ZTWO_VADDR(0xDD0000);
    a3000_host->irq = IRQ_AMIGA_PORTS;
    DMA(a3000_host)->DAWR = DAWR_A3000;
    regs.SASR = &(DMA(a3000_host)->SASR);
    regs.SCMD = &(DMA(a3000_host)->SCMD);
    HDATA(a3000_host)->no_sync = 0xff;
    HDATA(a3000_host)->fast = 0;
    HDATA(a3000_host)->dma_mode = CTRL_DMA;
    wd33c93_init(a3000_host, regs, dma_setup, dma_stop, WD33C93_FS_12_15);
    if (request_irq(IRQ_AMIGA_PORTS, a3000_intr, IRQF_SHARED, "A3000 SCSI",
		    a3000_intr))
        goto fail_irq;
    DMA(a3000_host)->CNTR = CNTR_PDMD | CNTR_INTEN;

    return 1;

fail_irq:
    wd33c93_release();
    scsi_unregister(a3000_host);
fail_register:
    release_mem_region(0xDD0000, 256);
    return 0;
}
Exemple #12
0
static void dma_stop (struct Scsi_Host *instance, Scsi_Cmnd *SCpnt,
		      int status)
{
    /* disable SCSI interrupts */
    unsigned short cntr = CNTR_PDMD;

    if (!HDATA(instance)->dma_dir)
	cntr |= CNTR_DDIR;

    DMA(instance)->CNTR = cntr;
    mb();			/* make sure CNTR is updated before next IO */

    /* flush if we were reading */
    if (HDATA(instance)->dma_dir) {
	DMA(instance)->FLUSH = 1;
	mb();			/* don't allow prefetch */
	while (!(DMA(instance)->ISTR & ISTR_FE_FLG))
	    barrier();
	mb();			/* no IO until FLUSH is done */
    }

    /* clear a possible interrupt */
    /* I think that this CINT is only necessary if you are
     * using the terminal count features.   HM 7 Mar 1994
     */
    DMA(instance)->CINT = 1;

    /* stop DMA */
    DMA(instance)->SP_DMA = 1;
    mb();			/* make sure DMA is stopped before next IO */

    /* restore the CONTROL bits (minus the direction flag) */
    DMA(instance)->CNTR = CNTR_PDMD | CNTR_INTEN;
    mb();			/* make sure CNTR is updated before next IO */

    /* copy from a bounce buffer, if necessary */
    if (status && HDATA(instance)->dma_bounce_buffer) {
	if (SCpnt && SCpnt->use_sg) {
	    if (HDATA(instance)->dma_dir && SCpnt)
		memcpy (SCpnt->SCp.ptr,
			HDATA(instance)->dma_bounce_buffer,
			SCpnt->SCp.this_residual);
	    kfree (HDATA(instance)->dma_bounce_buffer);
	    HDATA(instance)->dma_bounce_buffer = NULL;
	    HDATA(instance)->dma_bounce_len = 0;
	} else {
	    if (HDATA(instance)->dma_dir && SCpnt)
		memcpy (SCpnt->request_buffer,
			HDATA(instance)->dma_bounce_buffer,
			SCpnt->request_bufflen);

	    kfree (HDATA(instance)->dma_bounce_buffer);
	    HDATA(instance)->dma_bounce_buffer = NULL;
	    HDATA(instance)->dma_bounce_len = 0;
	}
    }
}
Exemple #13
0
/* check file status; hold on to file information used
   to restore access time */
int
fileHasChanged(const char *mbox_filename, time_t * atime,
			   time_t * mtime, off_t * size)
{
	struct stat st;

	/* mbox file */
	if (stat(mbox_filename, &st)) {
		DMA(DEBUG_ERROR, "Can't stat '%s': %s\n",
			mbox_filename, strerror(errno));
	} else if (st.st_mtime != *mtime || st.st_size != *size) {
		/* file was changed OR initially read */
		DMA(DEBUG_INFO, " %s was changed,"
			" mTIME: %lu -> %lu; SIZE: %lu -> %lu\n",
			mbox_filename, *mtime, st.st_mtime,
			(unsigned long) *size, (unsigned long) st.st_size);

		*atime = st.st_atime;
		*mtime = st.st_mtime;
		*size = st.st_size;
		return 1;
	}
	return 0;
}
Exemple #14
0
/*@null@*/
FILE *kind_popen(const char *command, const char *type)
{
	FILE *ret;
	assert(strcmp(type, "r") == 0);
	assert(old_signal_handler == NULL);
	old_signal_handler = signal(SIGCHLD, SIG_DFL);
	ret = popen(command, type);
	if (ret == NULL) {
		DMA(DEBUG_ERROR, "popen: error while reading '%s': %s\n",
			command, strerror(errno));
		(void) signal(SIGCHLD, old_signal_handler);
		old_signal_handler = NULL;
	}
	return (ret);
}
static irqreturn_t a2091_intr (int irq, void *_instance)
{
    unsigned long flags;
    unsigned int status;
    struct Scsi_Host *instance = (struct Scsi_Host *)_instance;

    status = DMA(instance)->ISTR;
    if (!(status & (ISTR_INT_F|ISTR_INT_P)) || !(status & ISTR_INTS))
	return IRQ_NONE;

    spin_lock_irqsave(instance->host_lock, flags);
    wd33c93_intr(instance);
    spin_unlock_irqrestore(instance->host_lock, flags);
    return IRQ_HANDLED;
}
Exemple #16
0
static irqreturn_t a3000_intr (int irq, void *dummy, struct pt_regs *fp)
{
	unsigned long flags;
	unsigned int status = DMA(a3000_host)->ISTR;

	if (!(status & ISTR_INT_P))
		return IRQ_NONE;
	if (status & ISTR_INTS)
	{
		spin_lock_irqsave(a3000_host->host_lock, flags);
		wd33c93_intr (a3000_host);
		spin_unlock_irqrestore(a3000_host->host_lock, flags);
		return IRQ_HANDLED;
	}
	printk("Non-serviced A3000 SCSI-interrupt? ISTR = %02x\n", status);
	return IRQ_NONE;
}
Exemple #17
0
/* exported for testing */
extern int
getline_from_buffer(char *readbuffer, char *linebuffer, int linebuflen)
{
	char *p, *q;
	int i;
	/* find end of line (stopping if linebuflen is too small. */
	for (p = readbuffer, i = 0;
		 *p != '\n' && *p != '\0' && i < linebuflen - 1; p++, i++);

	/* gobble \n if it starts the line. */
	if (*p == '\n') {
		/* grab the end of line too! and then advance past
		   the newline */
		i++;
		p++;
	} else {
		/* TODO -- perhaps we should return no line at all
		   here, as it might be incomplete.  don't want to
		   break anything though. */
		DMA(DEBUG_INFO, "expected line doesn't end on its own.\n");
	}

	if (i != 0) {
		/* copy a line into the linebuffer */
		strncpy(linebuffer, readbuffer, (size_t) i);
		/* sigh, null terminate */
		linebuffer[i] = '\0';
		/* shift the rest over; this could be done
		   instead with strcpy... I think. */
		q = readbuffer;
		if (*p != '\0') {
			while (*p != '\0') {
				*(q++) = *(p++);
			}
		}
		/* null terminate */
		*(q++) = *(p++);
		/* return the length of the line */
	}
	if (i < 0 || i > linebuflen) {
		DM((Pop3) NULL, DEBUG_ERROR, "bork bork bork!: %d %d\n", i,
		   linebuflen);
	}
	return i;
}
Exemple #18
0
static void a3000_intr (int irq, void *dummy, struct pt_regs *fp)
{
    unsigned int status = DMA(a3000_host)->ISTR;

    if (!(status & ISTR_INT_P))
	return;

    if (status & ISTR_INTS)
    {
	/* disable PORTS interrupt */
	custom.intena = IF_PORTS;
	wd33c93_intr (a3000_host);
	/* enable PORTS interrupt */
	custom.intena = IF_SETCLR | IF_PORTS;
    } else {
      printk("Non-serviced A3000 SCSI-interrupt? ISTR = %02x\n", status);
    }
}
Exemple #19
0
static int count_msgs(char *path)
{
	DIR *D;
	struct dirent *de;
	int count = 0;

	D = opendir(path);
	if (D == NULL) {
		DMA(DEBUG_ERROR,
			"Error opening directory '%s': %s\n", path, strerror(errno));
		return -1;
	}

	while ((de = readdir(D)) != NULL) {
		if ((strcmp(de->d_name, ".") & strcmp(de->d_name, "..")) != 0) {
			count++;
		}
	}
	closedir(D);

	return count;
}
Exemple #20
0
void tlscomm_printf(struct connection_state *scs, const char *format, ...)
{
	va_list args;
	char buf[1024];
	int bytes;
	ssize_t unused __attribute__((unused));

	if (scs == NULL) {
		DMA(DEBUG_ERROR, "null connection to tlscomm_printf\n");
		abort();
	}
	va_start(args, format);
	bytes = vsnprintf(buf, 1024, format, args);
	va_end(args);

	if (scs->sd != -1) {
#ifdef USE_GNUTLS
		if (scs->tls_state) {
			int written = gnutls_write(scs->tls_state, buf, bytes);
			if (written < bytes) {
				TDM(DEBUG_ERROR,
					"Error %s prevented writing: %*s\n",
					gnutls_strerror(written), bytes, buf);
				return;
			}
		} else
#endif
			/* Why???? */
			unused = write(scs->sd, buf, bytes);
	} else {
		printf
			("warning: tlscomm_printf called with an invalid socket descriptor\n");
		return;
	}
	TDM(DEBUG_INFO, "wrote %*s", bytes, buf);
}
static void dma_stop(struct Scsi_Host *instance, struct scsi_cmnd *SCpnt,
		      int status)
{
    /* disable SCSI interrupts */
    unsigned short cntr = CNTR_PDMD;

    if (!HDATA(instance)->dma_dir)
	    cntr |= CNTR_DDIR;

    /* disable SCSI interrupts */
    DMA(instance)->CNTR = cntr;

    /* flush if we were reading */
    if (HDATA(instance)->dma_dir) {
	DMA(instance)->FLUSH = 1;
	while (!(DMA(instance)->ISTR & ISTR_FE_FLG))
	    ;
    }

    /* clear a possible interrupt */
    DMA(instance)->CINT = 1;

    /* stop DMA */
    DMA(instance)->SP_DMA = 1;

    /* restore the CONTROL bits (minus the direction flag) */
    DMA(instance)->CNTR = CNTR_PDMD | CNTR_INTEN;

    /* copy from a bounce buffer, if necessary */
    if (status && HDATA(instance)->dma_bounce_buffer) {
	if( HDATA(instance)->dma_dir )
		memcpy (SCpnt->SCp.ptr, 
			HDATA(instance)->dma_bounce_buffer,
			SCpnt->SCp.this_residual);
	kfree (HDATA(instance)->dma_bounce_buffer);
	HDATA(instance)->dma_bounce_buffer = NULL;
	HDATA(instance)->dma_bounce_len = 0;
    }
}
Exemple #22
0
static void master(void) {
  unsigned i;

  write_xpm_header();

  /* clear response fields */
  for (i = 0; i < SLAVES; i++) {
    master_mpb->slave[i].row.cmd = CMD_STOP;
  }
  /* send start packets */
  for (i = 0; i < SLAVES; i++) {
    master_mpb->slave[i].packet.cmd = CMD_START;
    DMA(i+1, &(slave_mpb[i]->packet),
        &(master_mpb->slave[i].packet),
        sizeof(struct packet_t));
  }
  /* wait for acknowledgement */
  for (i = 0; i < SLAVES; i++) {
    while (master_mpb->slave[i].row.cmd != CMD_START) {
      /* spin until start reponse */
    }
  }
  /* clear response fields */
  for (i = 0; i < SLAVES; i++) {
    master_mpb->slave[i].row.cmd = CMD_NULL;
  }

  int row[SLAVES];
  int received_row;

  /* send first packets to slaves */
  for (i = 0; i < SLAVES && i < ROWS; i++) {
    row[i] = i*(ROWS/SLAVES);
    master_mpb->slave[i].packet.cmd    = row[i];
    master_mpb->slave[i].packet.yval   = YSTART + row[i]*YSTEP_SIZE;
    master_mpb->slave[i].packet.xstart = XSTART;
    master_mpb->slave[i].packet.xend   = XEND;
    master_mpb->slave[i].packet.xstep  = XSTEP_SIZE;
    DMA(i+1, &(slave_mpb[i]->packet),
        &(master_mpb->slave[i].packet),
        sizeof(struct packet_t));

    row[i]++;
  }
  /* receive rows and send next packets */
  for (received_row = 0; received_row < ROWS; ) {
    for (i = 0; i < SLAVES; i++) {
      if (master_mpb->slave[i].row.cmd != CMD_NULL) {
        received_row++;

		unsigned k;
        static char buf[COLS];

        /* write out position */
        itoa(buf, master_mpb->slave[i].row.cmd);
        WRITE(buf, 10);

        /* write out data */
        WRITE(" 68c\n\"", 6);
		for (k = 0; k < COLS; k++) {
		  buf[k] = master_mpb->slave[i].row.data[k];
		}
        WRITE(buf, COLS);
        WRITE("\",\n.\nw\n", 7);

        /* clear response field */
        master_mpb->slave[i].row.cmd = CMD_NULL;

        /* send next packet */
        if (row[i] < (i+1)*(ROWS/SLAVES)) {
          master_mpb->slave[i].packet.cmd    = row[i];
          master_mpb->slave[i].packet.yval   = YSTART + row[i]*YSTEP_SIZE;
          master_mpb->slave[i].packet.xstart = XSTART;
          master_mpb->slave[i].packet.xend   = XEND;
          master_mpb->slave[i].packet.xstep  = XSTEP_SIZE;
          DMA(i+1, &(slave_mpb[i]->packet),
              &(master_mpb->slave[i].packet),
              sizeof(struct packet_t));

          row[i]++;
        }
      }
    }
  }

  /* send stop packets */
  for (i = 0; i < SLAVES; i++) {
    master_mpb->slave[i].packet.cmd = CMD_STOP;
    DMA(i+1, &(slave_mpb[i]->packet),
        &(master_mpb->slave[i].packet),
        sizeof(struct packet_t));
  }
}
Exemple #23
0
static int dma_setup (Scsi_Cmnd *cmd, int dir_in)
{
    unsigned short cntr = CNTR_PDMD | CNTR_INTEN;
    unsigned long addr = VTOP(cmd->SCp.ptr);

    /*
     * if the physical address has the wrong alignment, or if
     * physical address is bad, or if it is a write and at the
     * end of a physical memory chunk, then allocate a bounce
     * buffer
     */
    if (addr & A3000_XFER_MASK ||
	(!dir_in && mm_end_of_chunk (addr, cmd->SCp.this_residual)))
    {
	HDATA(a3000_host)->dma_bounce_len = (cmd->SCp.this_residual + 511)
	    & ~0x1ff;
	HDATA(a3000_host)->dma_bounce_buffer =
	    scsi_malloc (HDATA(a3000_host)->dma_bounce_len);
	
	/* can't allocate memory; use PIO */
	if (!HDATA(a3000_host)->dma_bounce_buffer) {
	    HDATA(a3000_host)->dma_bounce_len = 0;
	    return 1;
	}

	if (!dir_in) {
	    /* copy to bounce buffer for a write */
	    if (cmd->use_sg) {
		memcpy (HDATA(a3000_host)->dma_bounce_buffer,
			cmd->SCp.ptr, cmd->SCp.this_residual);
	    } else
		memcpy (HDATA(a3000_host)->dma_bounce_buffer,
			cmd->request_buffer, cmd->request_bufflen);
	}

	addr = VTOP(HDATA(a3000_host)->dma_bounce_buffer);
    }

    /* setup dma direction */
    if (!dir_in)
	cntr |= CNTR_DDIR;

    /* remember direction */
    HDATA(a3000_host)->dma_dir = dir_in;

    DMA(a3000_host)->CNTR = cntr;

    /* setup DMA *physical* address */
    DMA(a3000_host)->ACR = addr;

    if (dir_in)
  	/* invalidate any cache */
	cache_clear (addr, cmd->SCp.this_residual);
    else
	/* push any dirty cache */
	cache_push (addr, cmd->SCp.this_residual);

    /* start DMA */
    DMA(a3000_host)->ST_DMA = 1;

    /* return success */
    return 0;
}
Exemple #24
0
    uint8_t channel;
    dmaChannelSpec_t channelSpec[MAX_TIMER_DMA_OPTIONS];
} dmaTimerMapping_t;

#if defined(STM32F4) || defined(STM32F7)

#if defined(STM32F4)
#define DMA(d, s, c) { DMA_CODE(d, s, c), DMA ## d ## _Stream ## s, DMA_Channel_ ## c }
#elif defined(STM32F7)
#define DMA(d, s, c) { DMA_CODE(d, s, c), DMA ## d ## _Stream ## s, DMA_CHANNEL_ ## c }
#endif

static const dmaPeripheralMapping_t dmaPeripheralMapping[] = {
#ifdef USE_SPI
    // Everything including F405 and F446
    { DMA_PERIPH_SPI_TX,  SPIDEV_1,  { DMA(2, 3, 3), DMA(2, 5, 3) } },
    { DMA_PERIPH_SPI_RX,  SPIDEV_1,  { DMA(2, 0, 3), DMA(2, 2, 3) } },
    { DMA_PERIPH_SPI_TX,  SPIDEV_2,  { DMA(1, 4, 0) } },
    { DMA_PERIPH_SPI_RX,  SPIDEV_2,  { DMA(1, 3, 0) } },
    { DMA_PERIPH_SPI_TX,  SPIDEV_3,  { DMA(1, 5, 0), DMA(1, 7, 0) } },
    { DMA_PERIPH_SPI_RX,  SPIDEV_3,  { DMA(1, 0, 0), DMA(1, 2, 0) } },

#if defined(STM32F411xE) || defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F765xx) || defined(STM32F722xx)
    { DMA_PERIPH_SPI_TX,  SPIDEV_4,  { DMA(2, 1, 4) } },
    { DMA_PERIPH_SPI_RX,  SPIDEV_4,  { DMA(2, 0, 4) } },

#ifdef USE_EXTENDED_SPI_DEVICE
    { DMA_PERIPH_SPI_TX,  SPIDEV_5,  { DMA(2, 6, 7) } },
    { DMA_PERIPH_SPI_RX,  SPIDEV_5,  { DMA(2, 5, 7) } },

#if !defined(STM32F722xx)
Exemple #25
0
void UART_setup(unsigned interface)
{
    switch(interface)
    {
#ifdef UART_HOST
    case UART_INTERFACE_USB:
        GPIO(PORT_UART_USB, SEL) |= BIT(PIN_UART_USB_TX) | BIT(PIN_UART_USB_RX);

        UART(UART_HOST, CTL1) |= UCSWRST; // put state machine in reset
        UART(UART_HOST, CTL1) |= UCSSEL__SMCLK;
#ifdef CONFIG_ABORT_ON_HOST_UART_ERROR
        UART(UART_HOST, CTL1) |= UCRXEIE;
#endif

        UART(UART_HOST, BR0) = CONFIG_USB_UART_BAUDRATE_BR0;
        UART(UART_HOST, BR1) = CONFIG_USB_UART_BAUDRATE_BR1;
        UART(UART_HOST, MCTL) |= 0
#ifdef CONFIG_USB_UART_BAUDRATE_UCOS16
            | UCOS16
#endif
#ifdef CONFIG_USB_UART_BAUDRATE_BRS
            | BRS_BITS(CONFIG_USB_UART_BAUDRATE_BRS)
#endif
#ifdef CONFIG_USB_UART_BAUDRATE_BRF
            | BRF_BITS(CONFIG_USB_UART_BAUDRATE_BRF)
#endif
       ;

        // TX DMA

        DMA(DMA_HOST_UART_TX, CTL) &= ~DMAEN;

        DMA_CTL(DMA_HOST_UART_TX_CTL) =
            DMA_TRIG(DMA_HOST_UART_TX, DMA_TRIG_UART(UART_HOST, TX));

        DMACTL4 = DMARMWDIS;

        DMA(DMA_HOST_UART_TX, CTL) =
              DMADT_0 /* single */ |
              DMADSTINCR_0 /* dest no inc */ | DMASRCINCR_3 /* src inc */ |
              DMADSTBYTE | DMASRCBYTE | DMALEVEL | DMAIE;

        // DMA(DMA_HOST_UART_TX, SA) = set on each transfer
        DMA(DMA_HOST_UART_TX, DA) = (__DMA_ACCESS_REG__)(&UART(UART_HOST, TXBUF));
        // DMA(DMA_HOST_UART_TX, SZ) = set on each transfer

        UART(UART_HOST, CTL1) &= ~UCSWRST; // initialize USCI state machine
        UART(UART_HOST, IE) |= UCRXIE;     // enable Tx + Rx interrupts
        break;
#endif // PORT_PORT_UART_USB

#ifdef UART_TARGET
    case UART_INTERFACE_WISP:
        GPIO(PORT_UART_TARGET, SEL) |=
            BIT(PIN_UART_TARGET_TX) | BIT(PIN_UART_TARGET_RX);

        UART(UART_TARGET, CTL1) |= UCSWRST; // put state machine in reset
        UART(UART_TARGET, CTL1) |= UCSSEL__SMCLK;

        UART(UART_TARGET, BR0) = CONFIG_TARGET_UART_BAUDRATE_BR0;
        UART(UART_TARGET, BR1) = CONFIG_TARGET_UART_BAUDRATE_BR1;
        UART(UART_TARGET, MCTL) |= 0
#ifdef CONFIG_TARGET_UART_BAUDRATE_UCOS16
            | UCOS16
#endif
#ifdef CONFIG_TARGET_UART_BAUDRATE_BRS
            | BRS_BITS(CONFIG_TARGET_UART_BAUDRATE_BRS)
#endif
#ifdef CONFIG_TARGET_UART_BAUDRATE_BRF
            | BRF_BITS(CONFIG_TARGET_UART_BAUDRATE_BRF)
#endif
       ;

        UART(UART_TARGET, CTL1) &= ~UCSWRST; // initialize USCI state machine
        UART(UART_TARGET, IE) |= UCRXIE;     // enable Tx + Rx interrupts
        break;

    default:
        break;
    }
#endif // PORT_UART_TARGET
} // UART_setup
Exemple #26
0
struct connection_state *initialize_gnutls(intptr_t sd, char *name, Pop3 pc,
										   const char *remote_hostname)
{
	static int gnutls_initialized;
	int zok;
	struct connection_state *scs = malloc(sizeof(struct connection_state));
	memset(scs, 0, sizeof(struct connection_state));	/* clears the unprocessed buffer */

	scs->pc = pc;

	assert(sd >= 0);

	if (gnutls_initialized == 0) {
		assert(gnutls_global_init() == 0);
		gnutls_initialized = 1;
	}

	assert(gnutls_init(&scs->tls_state, GNUTLS_CLIENT) == 0);
	{
		const char *err_pos;
		if (GNUTLS_E_SUCCESS != gnutls_priority_set_direct(scs->tls_state, tls, &err_pos)) {
			DMA(DEBUG_ERROR,
				"Unable to set the priorities to use on the ciphers, "
				"key exchange methods, macs and/or compression methods.\n"
				"See 'tls' parameter in config file: '%s'.\n",
				err_pos);
			exit(1);
		}

		/* no client private key */
		if (gnutls_certificate_allocate_credentials(&scs->xcred) < 0) {
			DMA(DEBUG_ERROR, "gnutls memory error\n");
			exit(1);
		}

		/* certfile seems to work. */
		if (certificate_filename != NULL) {
			if (!exists(certificate_filename)) {
				DMA(DEBUG_ERROR,
					"Certificate file (certfile=) %s not found.\n",
					certificate_filename);
				exit(1);
			}
			zok = gnutls_certificate_set_x509_trust_file(scs->xcred,
					(char *)
					certificate_filename,
					GNUTLS_X509_FMT_PEM);
			if (zok < 0) {
				DMA(DEBUG_ERROR,
					"GNUTLS did not like your certificate file %s (%d).\n",
					certificate_filename, zok);
				gnutls_perror(zok);
				exit(1);
			}
		}

		gnutls_cred_set(scs->tls_state, GNUTLS_CRD_CERTIFICATE,
						scs->xcred);
		gnutls_transport_set_ptr(scs->tls_state,
								 (gnutls_transport_ptr_t) sd);
		do {
			zok = gnutls_handshake(scs->tls_state);
		}
		while (zok == GNUTLS_E_INTERRUPTED || zok == GNUTLS_E_AGAIN);

		tls_check_certificate(scs, remote_hostname);
	}

	if (zok < 0) {
		TDM(DEBUG_ERROR, "%s: Handshake failed\n", name);
		TDM(DEBUG_ERROR, "%s: This may be a problem in gnutls, "
			"which is under development\n", name);
		TDM(DEBUG_ERROR,
			"%s: This copy of wmbiff was compiled with \n"
			"  gnutls version %s.\n", name, LIBGNUTLS_VERSION);
		gnutls_perror(zok);
		if (scs->pc->u.pop_imap.serverPort != 143 /* starttls */ ) {
			TDM(DEBUG_ERROR,
				"%s: Please run 'gnutls-cli-debug -p %d %s' to test ssl directly.\n"
				"  That tool provides a lower-level test of gnutls with your server.\n",
				name, scs->pc->u.pop_imap.serverPort, remote_hostname);
		}
		gnutls_deinit(scs->tls_state);
		free(scs);
		return (NULL);
	} else {
		TDM(DEBUG_INFO, "%s: Handshake was completed\n", name);
		if (scs->pc->debug >= DEBUG_INFO)
			print_info(scs->tls_state, remote_hostname);
		scs->sd = sd;
		scs->name = name;
	}
	return (scs);
}
Exemple #27
0
static int __init bfin_debug_mmrs_init(void)
{
	struct dentry *top, *parent;

	pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");

	top = debugfs_create_dir("blackfin", NULL);
	if (top == NULL)
		return -1;

	parent = debugfs_create_dir("core_regs", top);
	debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
	debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
	debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
	D_SYSREG(cycles);
	D_SYSREG(cycles2);
	D_SYSREG(emudat);
	D_SYSREG(seqstat);
	D_SYSREG(syscfg);

	
	parent = debugfs_create_dir("ctimer", top);
	D32(TCNTL);
	D32(TCOUNT);
	D32(TPERIOD);
	D32(TSCALE);

	parent = debugfs_create_dir("cec", top);
	D32(EVT0);
	D32(EVT1);
	D32(EVT2);
	D32(EVT3);
	D32(EVT4);
	D32(EVT5);
	D32(EVT6);
	D32(EVT7);
	D32(EVT8);
	D32(EVT9);
	D32(EVT10);
	D32(EVT11);
	D32(EVT12);
	D32(EVT13);
	D32(EVT14);
	D32(EVT15);
	D32(EVT_OVERRIDE);
	D32(IMASK);
	D32(IPEND);
	D32(ILAT);
	D32(IPRIO);

	parent = debugfs_create_dir("debug", top);
	D32(DBGSTAT);
	D32(DSPID);

	parent = debugfs_create_dir("mmu", top);
	D32(SRAM_BASE_ADDRESS);
	D32(DCPLB_ADDR0);
	D32(DCPLB_ADDR10);
	D32(DCPLB_ADDR11);
	D32(DCPLB_ADDR12);
	D32(DCPLB_ADDR13);
	D32(DCPLB_ADDR14);
	D32(DCPLB_ADDR15);
	D32(DCPLB_ADDR1);
	D32(DCPLB_ADDR2);
	D32(DCPLB_ADDR3);
	D32(DCPLB_ADDR4);
	D32(DCPLB_ADDR5);
	D32(DCPLB_ADDR6);
	D32(DCPLB_ADDR7);
	D32(DCPLB_ADDR8);
	D32(DCPLB_ADDR9);
	D32(DCPLB_DATA0);
	D32(DCPLB_DATA10);
	D32(DCPLB_DATA11);
	D32(DCPLB_DATA12);
	D32(DCPLB_DATA13);
	D32(DCPLB_DATA14);
	D32(DCPLB_DATA15);
	D32(DCPLB_DATA1);
	D32(DCPLB_DATA2);
	D32(DCPLB_DATA3);
	D32(DCPLB_DATA4);
	D32(DCPLB_DATA5);
	D32(DCPLB_DATA6);
	D32(DCPLB_DATA7);
	D32(DCPLB_DATA8);
	D32(DCPLB_DATA9);
	D32(DCPLB_FAULT_ADDR);
	D32(DCPLB_STATUS);
	D32(DMEM_CONTROL);
	D32(DTEST_COMMAND);
	D32(DTEST_DATA0);
	D32(DTEST_DATA1);

	D32(ICPLB_ADDR0);
	D32(ICPLB_ADDR1);
	D32(ICPLB_ADDR2);
	D32(ICPLB_ADDR3);
	D32(ICPLB_ADDR4);
	D32(ICPLB_ADDR5);
	D32(ICPLB_ADDR6);
	D32(ICPLB_ADDR7);
	D32(ICPLB_ADDR8);
	D32(ICPLB_ADDR9);
	D32(ICPLB_ADDR10);
	D32(ICPLB_ADDR11);
	D32(ICPLB_ADDR12);
	D32(ICPLB_ADDR13);
	D32(ICPLB_ADDR14);
	D32(ICPLB_ADDR15);
	D32(ICPLB_DATA0);
	D32(ICPLB_DATA1);
	D32(ICPLB_DATA2);
	D32(ICPLB_DATA3);
	D32(ICPLB_DATA4);
	D32(ICPLB_DATA5);
	D32(ICPLB_DATA6);
	D32(ICPLB_DATA7);
	D32(ICPLB_DATA8);
	D32(ICPLB_DATA9);
	D32(ICPLB_DATA10);
	D32(ICPLB_DATA11);
	D32(ICPLB_DATA12);
	D32(ICPLB_DATA13);
	D32(ICPLB_DATA14);
	D32(ICPLB_DATA15);
	D32(ICPLB_FAULT_ADDR);
	D32(ICPLB_STATUS);
	D32(IMEM_CONTROL);
	if (!ANOMALY_05000481) {
		D32(ITEST_COMMAND);
		D32(ITEST_DATA0);
		D32(ITEST_DATA1);
	}

	parent = debugfs_create_dir("perf", top);
	D32(PFCNTR0);
	D32(PFCNTR1);
	D32(PFCTL);

	parent = debugfs_create_dir("trace", top);
	D32(TBUF);
	D32(TBUFCTL);
	D32(TBUFSTAT);

	parent = debugfs_create_dir("watchpoint", top);
	D32(WPIACTL);
	D32(WPIA0);
	D32(WPIA1);
	D32(WPIA2);
	D32(WPIA3);
	D32(WPIA4);
	D32(WPIA5);
	D32(WPIACNT0);
	D32(WPIACNT1);
	D32(WPIACNT2);
	D32(WPIACNT3);
	D32(WPIACNT4);
	D32(WPIACNT5);
	D32(WPDACTL);
	D32(WPDA0);
	D32(WPDA1);
	D32(WPDACNT0);
	D32(WPDACNT1);
	D32(WPSTAT);

	
#ifdef ATAPI_CONTROL
	parent = debugfs_create_dir("atapi", top);
	D16(ATAPI_CONTROL);
	D16(ATAPI_DEV_ADDR);
	D16(ATAPI_DEV_RXBUF);
	D16(ATAPI_DEV_TXBUF);
	D16(ATAPI_DMA_TFRCNT);
	D16(ATAPI_INT_MASK);
	D16(ATAPI_INT_STATUS);
	D16(ATAPI_LINE_STATUS);
	D16(ATAPI_MULTI_TIM_0);
	D16(ATAPI_MULTI_TIM_1);
	D16(ATAPI_MULTI_TIM_2);
	D16(ATAPI_PIO_TFRCNT);
	D16(ATAPI_PIO_TIM_0);
	D16(ATAPI_PIO_TIM_1);
	D16(ATAPI_REG_TIM_0);
	D16(ATAPI_SM_STATE);
	D16(ATAPI_STATUS);
	D16(ATAPI_TERMINATE);
	D16(ATAPI_UDMAOUT_TFRCNT);
	D16(ATAPI_ULTRA_TIM_0);
	D16(ATAPI_ULTRA_TIM_1);
	D16(ATAPI_ULTRA_TIM_2);
	D16(ATAPI_ULTRA_TIM_3);
	D16(ATAPI_UMAIN_TFRCNT);
	D16(ATAPI_XFER_LEN);
#endif

#if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
	parent = debugfs_create_dir("can", top);
# ifdef CAN_MC1
	bfin_debug_mmrs_can(parent, CAN_MC1, -1);
# endif
# ifdef CAN0_MC1
	CAN(0);
# endif
# ifdef CAN1_MC1
	CAN(1);
# endif
#endif

#ifdef CNT_COMMAND
	parent = debugfs_create_dir("counter", top);
	D16(CNT_COMMAND);
	D16(CNT_CONFIG);
	D32(CNT_COUNTER);
	D16(CNT_DEBOUNCE);
	D16(CNT_IMASK);
	D32(CNT_MAX);
	D32(CNT_MIN);
	D16(CNT_STATUS);
#endif

	parent = debugfs_create_dir("dmac", top);
#ifdef DMAC_TC_CNT
	D16(DMAC_TC_CNT);
	D16(DMAC_TC_PER);
#endif
#ifdef DMAC0_TC_CNT
	D16(DMAC0_TC_CNT);
	D16(DMAC0_TC_PER);
#endif
#ifdef DMAC1_TC_CNT
	D16(DMAC1_TC_CNT);
	D16(DMAC1_TC_PER);
#endif
#ifdef DMAC1_PERIMUX
	D16(DMAC1_PERIMUX);
#endif

#ifdef __ADSPBF561__
	
# define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
# define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
# define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
# define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
# define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
# define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
# define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
# define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
# define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
# define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
# define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
# define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
# define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
# define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
# define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
# define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
# define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
# define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
# define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
# define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
# define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
# define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
# define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
# define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
#endif
	parent = debugfs_create_dir("dma", top);
	DMA(0);
	DMA(1);
	DMA(1);
	DMA(2);
	DMA(3);
	DMA(4);
	DMA(5);
	DMA(6);
	DMA(7);
#ifdef DMA8_NEXT_DESC_PTR
	DMA(8);
	DMA(9);
	DMA(10);
	DMA(11);
#endif
#ifdef DMA12_NEXT_DESC_PTR
	DMA(12);
	DMA(13);
	DMA(14);
	DMA(15);
	DMA(16);
	DMA(17);
	DMA(18);
	DMA(19);
#endif
#ifdef DMA20_NEXT_DESC_PTR
	DMA(20);
	DMA(21);
	DMA(22);
	DMA(23);
#endif

	parent = debugfs_create_dir("ebiu_amc", top);
	D32(EBIU_AMBCTL0);
	D32(EBIU_AMBCTL1);
	D16(EBIU_AMGCTL);
#ifdef EBIU_MBSCTL
	D16(EBIU_MBSCTL);
	D32(EBIU_ARBSTAT);
	D32(EBIU_MODE);
	D16(EBIU_FCTL);
#endif

#ifdef EBIU_SDGCTL
	parent = debugfs_create_dir("ebiu_sdram", top);
# ifdef __ADSPBF561__
	D32(EBIU_SDBCTL);
# else
	D16(EBIU_SDBCTL);
# endif
	D32(EBIU_SDGCTL);
	D16(EBIU_SDRRC);
	D16(EBIU_SDSTAT);
#endif

#ifdef EBIU_DDRACCT
	parent = debugfs_create_dir("ebiu_ddr", top);
	D32(EBIU_DDRACCT);
	D32(EBIU_DDRARCT);
	D32(EBIU_DDRBRC0);
	D32(EBIU_DDRBRC1);
	D32(EBIU_DDRBRC2);
	D32(EBIU_DDRBRC3);
	D32(EBIU_DDRBRC4);
	D32(EBIU_DDRBRC5);
	D32(EBIU_DDRBRC6);
	D32(EBIU_DDRBRC7);
	D32(EBIU_DDRBWC0);
	D32(EBIU_DDRBWC1);
	D32(EBIU_DDRBWC2);
	D32(EBIU_DDRBWC3);
	D32(EBIU_DDRBWC4);
	D32(EBIU_DDRBWC5);
	D32(EBIU_DDRBWC6);
	D32(EBIU_DDRBWC7);
	D32(EBIU_DDRCTL0);
	D32(EBIU_DDRCTL1);
	D32(EBIU_DDRCTL2);
	D32(EBIU_DDRCTL3);
	D32(EBIU_DDRGC0);
	D32(EBIU_DDRGC1);
	D32(EBIU_DDRGC2);
	D32(EBIU_DDRGC3);
	D32(EBIU_DDRMCCL);
	D32(EBIU_DDRMCEN);
	D32(EBIU_DDRQUE);
	D32(EBIU_DDRTACT);
	D32(EBIU_ERRADD);
	D16(EBIU_ERRMST);
	D16(EBIU_RSTCTL);
#endif

#ifdef EMAC_ADDRHI
	parent = debugfs_create_dir("emac", top);
	D32(EMAC_ADDRHI);
	D32(EMAC_ADDRLO);
	D32(EMAC_FLC);
	D32(EMAC_HASHHI);
	D32(EMAC_HASHLO);
	D32(EMAC_MMC_CTL);
	D32(EMAC_MMC_RIRQE);
	D32(EMAC_MMC_RIRQS);
	D32(EMAC_MMC_TIRQE);
	D32(EMAC_MMC_TIRQS);
	D32(EMAC_OPMODE);
	D32(EMAC_RXC_ALIGN);
	D32(EMAC_RXC_ALLFRM);
	D32(EMAC_RXC_ALLOCT);
	D32(EMAC_RXC_BROAD);
	D32(EMAC_RXC_DMAOVF);
	D32(EMAC_RXC_EQ64);
	D32(EMAC_RXC_FCS);
	D32(EMAC_RXC_GE1024);
	D32(EMAC_RXC_LNERRI);
	D32(EMAC_RXC_LNERRO);
	D32(EMAC_RXC_LONG);
	D32(EMAC_RXC_LT1024);
	D32(EMAC_RXC_LT128);
	D32(EMAC_RXC_LT256);
	D32(EMAC_RXC_LT512);
	D32(EMAC_RXC_MACCTL);
	D32(EMAC_RXC_MULTI);
	D32(EMAC_RXC_OCTET);
	D32(EMAC_RXC_OK);
	D32(EMAC_RXC_OPCODE);
	D32(EMAC_RXC_PAUSE);
	D32(EMAC_RXC_SHORT);
	D32(EMAC_RXC_TYPED);
	D32(EMAC_RXC_UNICST);
	D32(EMAC_RX_IRQE);
	D32(EMAC_RX_STAT);
	D32(EMAC_RX_STKY);
	D32(EMAC_STAADD);
	D32(EMAC_STADAT);
	D32(EMAC_SYSCTL);
	D32(EMAC_SYSTAT);
	D32(EMAC_TXC_1COL);
	D32(EMAC_TXC_ABORT);
	D32(EMAC_TXC_ALLFRM);
	D32(EMAC_TXC_ALLOCT);
	D32(EMAC_TXC_BROAD);
	D32(EMAC_TXC_CRSERR);
	D32(EMAC_TXC_DEFER);
	D32(EMAC_TXC_DMAUND);
	D32(EMAC_TXC_EQ64);
	D32(EMAC_TXC_GE1024);
	D32(EMAC_TXC_GT1COL);
	D32(EMAC_TXC_LATECL);
	D32(EMAC_TXC_LT1024);
	D32(EMAC_TXC_LT128);
	D32(EMAC_TXC_LT256);
	D32(EMAC_TXC_LT512);
	D32(EMAC_TXC_MACCTL);
	D32(EMAC_TXC_MULTI);
	D32(EMAC_TXC_OCTET);
	D32(EMAC_TXC_OK);
	D32(EMAC_TXC_UNICST);
	D32(EMAC_TXC_XS_COL);
	D32(EMAC_TXC_XS_DFR);
	D32(EMAC_TX_IRQE);
	D32(EMAC_TX_STAT);
	D32(EMAC_TX_STKY);
	D32(EMAC_VLAN1);
	D32(EMAC_VLAN2);
	D32(EMAC_WKUP_CTL);
	D32(EMAC_WKUP_FFCMD);
	D32(EMAC_WKUP_FFCRC0);
	D32(EMAC_WKUP_FFCRC1);
	D32(EMAC_WKUP_FFMSK0);
	D32(EMAC_WKUP_FFMSK1);
	D32(EMAC_WKUP_FFMSK2);
	D32(EMAC_WKUP_FFMSK3);
	D32(EMAC_WKUP_FFOFF);
# ifdef EMAC_PTP_ACCR
	D32(EMAC_PTP_ACCR);
	D32(EMAC_PTP_ADDEND);
	D32(EMAC_PTP_ALARMHI);
	D32(EMAC_PTP_ALARMLO);
	D16(EMAC_PTP_CTL);
	D32(EMAC_PTP_FOFF);
	D32(EMAC_PTP_FV1);
	D32(EMAC_PTP_FV2);
	D32(EMAC_PTP_FV3);
	D16(EMAC_PTP_ID_OFF);
	D32(EMAC_PTP_ID_SNAP);
	D16(EMAC_PTP_IE);
	D16(EMAC_PTP_ISTAT);
	D32(EMAC_PTP_OFFSET);
	D32(EMAC_PTP_PPS_PERIOD);
	D32(EMAC_PTP_PPS_STARTHI);
	D32(EMAC_PTP_PPS_STARTLO);
	D32(EMAC_PTP_RXSNAPHI);
	D32(EMAC_PTP_RXSNAPLO);
	D32(EMAC_PTP_TIMEHI);
	D32(EMAC_PTP_TIMELO);
	D32(EMAC_PTP_TXSNAPHI);
	D32(EMAC_PTP_TXSNAPLO);
# endif
#endif

#if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
	parent = debugfs_create_dir("eppi", top);
# ifdef EPPI0_STATUS
	EPPI(0);
# endif
# ifdef EPPI1_STATUS
	EPPI(1);
# endif
# ifdef EPPI2_STATUS
	EPPI(2);
# endif
#endif

	parent = debugfs_create_dir("gptimer", top);
#ifdef TIMER_ENABLE
	GPTIMER_GROUP(TIMER_ENABLE, -1);
#endif
#ifdef TIMER_ENABLE0
	GPTIMER_GROUP(TIMER_ENABLE0, 0);
#endif
#ifdef TIMER_ENABLE1
	GPTIMER_GROUP(TIMER_ENABLE1, 1);
#endif
	
#ifdef TMRS4_DISABLE
	GPTIMER_GROUP(TMRS4_ENABLE, 0);
	GPTIMER_GROUP(TMRS8_ENABLE, 1);
#endif
	GPTIMER(0);
	GPTIMER(1);
	GPTIMER(2);
#ifdef TIMER3_CONFIG
	GPTIMER(3);
	GPTIMER(4);
	GPTIMER(5);
	GPTIMER(6);
	GPTIMER(7);
#endif
#ifdef TIMER8_CONFIG
	GPTIMER(8);
	GPTIMER(9);
	GPTIMER(10);
#endif
#ifdef TIMER11_CONFIG
	GPTIMER(11);
#endif

#ifdef HMDMA0_CONTROL
	parent = debugfs_create_dir("hmdma", top);
	HMDMA(0);
	HMDMA(1);
#endif

#ifdef HOST_CONTROL
	parent = debugfs_create_dir("hostdp", top);
	D16(HOST_CONTROL);
	D16(HOST_STATUS);
	D16(HOST_TIMEOUT);
#endif

#ifdef IMDMA_S0_CONFIG
	parent = debugfs_create_dir("imdma", top);
	IMDMA(0);
	IMDMA(1);
#endif

#ifdef KPAD_CTL
	parent = debugfs_create_dir("keypad", top);
	D16(KPAD_CTL);
	D16(KPAD_PRESCALE);
	D16(KPAD_MSEL);
	D16(KPAD_ROWCOL);
	D16(KPAD_STAT);
	D16(KPAD_SOFTEVAL);
#endif

	parent = debugfs_create_dir("mdma", top);
	MDMA(0);
	MDMA(1);
#ifdef MDMA_D2_CONFIG
	MDMA(2);
	MDMA(3);
#endif

#ifdef MXVR_CONFIG
	parent = debugfs_create_dir("mxvr", top);
	D16(MXVR_CONFIG);
# ifdef MXVR_PLL_CTL_0
	D32(MXVR_PLL_CTL_0);
# endif
	D32(MXVR_STATE_0);
	D32(MXVR_STATE_1);
	D32(MXVR_INT_STAT_0);
	D32(MXVR_INT_STAT_1);
	D32(MXVR_INT_EN_0);
	D32(MXVR_INT_EN_1);
	D16(MXVR_POSITION);
	D16(MXVR_MAX_POSITION);
	D16(MXVR_DELAY);
	D16(MXVR_MAX_DELAY);
	D32(MXVR_LADDR);
	D16(MXVR_GADDR);
	D32(MXVR_AADDR);
	D32(MXVR_ALLOC_0);
	D32(MXVR_ALLOC_1);
	D32(MXVR_ALLOC_2);
	D32(MXVR_ALLOC_3);
	D32(MXVR_ALLOC_4);
	D32(MXVR_ALLOC_5);
	D32(MXVR_ALLOC_6);
	D32(MXVR_ALLOC_7);
	D32(MXVR_ALLOC_8);
	D32(MXVR_ALLOC_9);
	D32(MXVR_ALLOC_10);
	D32(MXVR_ALLOC_11);
	D32(MXVR_ALLOC_12);
	D32(MXVR_ALLOC_13);
	D32(MXVR_ALLOC_14);
	D32(MXVR_SYNC_LCHAN_0);
	D32(MXVR_SYNC_LCHAN_1);
	D32(MXVR_SYNC_LCHAN_2);
	D32(MXVR_SYNC_LCHAN_3);
	D32(MXVR_SYNC_LCHAN_4);
	D32(MXVR_SYNC_LCHAN_5);
	D32(MXVR_SYNC_LCHAN_6);
	D32(MXVR_SYNC_LCHAN_7);
	D32(MXVR_DMA0_CONFIG);
	D32(MXVR_DMA0_START_ADDR);
	D16(MXVR_DMA0_COUNT);
	D32(MXVR_DMA0_CURR_ADDR);
	D16(MXVR_DMA0_CURR_COUNT);
	D32(MXVR_DMA1_CONFIG);
	D32(MXVR_DMA1_START_ADDR);
	D16(MXVR_DMA1_COUNT);
	D32(MXVR_DMA1_CURR_ADDR);
	D16(MXVR_DMA1_CURR_COUNT);
	D32(MXVR_DMA2_CONFIG);
	D32(MXVR_DMA2_START_ADDR);
	D16(MXVR_DMA2_COUNT);
	D32(MXVR_DMA2_CURR_ADDR);
	D16(MXVR_DMA2_CURR_COUNT);
	D32(MXVR_DMA3_CONFIG);
	D32(MXVR_DMA3_START_ADDR);
	D16(MXVR_DMA3_COUNT);
	D32(MXVR_DMA3_CURR_ADDR);
	D16(MXVR_DMA3_CURR_COUNT);
	D32(MXVR_DMA4_CONFIG);
	D32(MXVR_DMA4_START_ADDR);
	D16(MXVR_DMA4_COUNT);
	D32(MXVR_DMA4_CURR_ADDR);
	D16(MXVR_DMA4_CURR_COUNT);
	D32(MXVR_DMA5_CONFIG);
	D32(MXVR_DMA5_START_ADDR);
	D16(MXVR_DMA5_COUNT);
	D32(MXVR_DMA5_CURR_ADDR);
	D16(MXVR_DMA5_CURR_COUNT);
	D32(MXVR_DMA6_CONFIG);
	D32(MXVR_DMA6_START_ADDR);
	D16(MXVR_DMA6_COUNT);
	D32(MXVR_DMA6_CURR_ADDR);
	D16(MXVR_DMA6_CURR_COUNT);
	D32(MXVR_DMA7_CONFIG);
	D32(MXVR_DMA7_START_ADDR);
	D16(MXVR_DMA7_COUNT);
	D32(MXVR_DMA7_CURR_ADDR);
	D16(MXVR_DMA7_CURR_COUNT);
	D16(MXVR_AP_CTL);
	D32(MXVR_APRB_START_ADDR);
	D32(MXVR_APRB_CURR_ADDR);
	D32(MXVR_APTB_START_ADDR);
	D32(MXVR_APTB_CURR_ADDR);
	D32(MXVR_CM_CTL);
	D32(MXVR_CMRB_START_ADDR);
	D32(MXVR_CMRB_CURR_ADDR);
	D32(MXVR_CMTB_START_ADDR);
	D32(MXVR_CMTB_CURR_ADDR);
	D32(MXVR_RRDB_START_ADDR);
	D32(MXVR_RRDB_CURR_ADDR);
	D32(MXVR_PAT_DATA_0);
	D32(MXVR_PAT_EN_0);
	D32(MXVR_PAT_DATA_1);
	D32(MXVR_PAT_EN_1);
	D16(MXVR_FRAME_CNT_0);
	D16(MXVR_FRAME_CNT_1);
	D32(MXVR_ROUTING_0);
	D32(MXVR_ROUTING_1);
	D32(MXVR_ROUTING_2);
	D32(MXVR_ROUTING_3);
	D32(MXVR_ROUTING_4);
	D32(MXVR_ROUTING_5);
	D32(MXVR_ROUTING_6);
	D32(MXVR_ROUTING_7);
	D32(MXVR_ROUTING_8);
	D32(MXVR_ROUTING_9);
	D32(MXVR_ROUTING_10);
	D32(MXVR_ROUTING_11);
	D32(MXVR_ROUTING_12);
	D32(MXVR_ROUTING_13);
	D32(MXVR_ROUTING_14);
# ifdef MXVR_PLL_CTL_1
	D32(MXVR_PLL_CTL_1);
# endif
	D16(MXVR_BLOCK_CNT);
# ifdef MXVR_CLK_CTL
	D32(MXVR_CLK_CTL);
# endif
# ifdef MXVR_CDRPLL_CTL
	D32(MXVR_CDRPLL_CTL);
# endif
# ifdef MXVR_FMPLL_CTL
	D32(MXVR_FMPLL_CTL);
# endif
# ifdef MXVR_PIN_CTL
	D16(MXVR_PIN_CTL);
# endif
# ifdef MXVR_SCLK_CNT
	D16(MXVR_SCLK_CNT);
# endif
#endif

#ifdef NFC_ADDR
	parent = debugfs_create_dir("nfc", top);
	D_WO(NFC_ADDR, 16);
	D_WO(NFC_CMD, 16);
	D_RO(NFC_COUNT, 16);
	D16(NFC_CTL);
	D_WO(NFC_DATA_RD, 16);
	D_WO(NFC_DATA_WR, 16);
	D_RO(NFC_ECC0, 16);
	D_RO(NFC_ECC1, 16);
	D_RO(NFC_ECC2, 16);
	D_RO(NFC_ECC3, 16);
	D16(NFC_IRQMASK);
	D16(NFC_IRQSTAT);
	D_WO(NFC_PGCTL, 16);
	D_RO(NFC_READ, 16);
	D16(NFC_RST);
	D_RO(NFC_STAT, 16);
#endif

#ifdef OTP_CONTROL
	parent = debugfs_create_dir("otp", top);
	D16(OTP_CONTROL);
	D16(OTP_BEN);
	D16(OTP_STATUS);
	D32(OTP_TIMING);
	D32(OTP_DATA0);
	D32(OTP_DATA1);
	D32(OTP_DATA2);
	D32(OTP_DATA3);
#endif

#ifdef PINT0_MASK_SET
	parent = debugfs_create_dir("pint", top);
	PINT(0);
	PINT(1);
	PINT(2);
	PINT(3);
#endif

#ifdef PIXC_CTL
	parent = debugfs_create_dir("pixc", top);
	D16(PIXC_CTL);
	D16(PIXC_PPL);
	D16(PIXC_LPF);
	D16(PIXC_AHSTART);
	D16(PIXC_AHEND);
	D16(PIXC_AVSTART);
	D16(PIXC_AVEND);
	D16(PIXC_ATRANSP);
	D16(PIXC_BHSTART);
	D16(PIXC_BHEND);
	D16(PIXC_BVSTART);
	D16(PIXC_BVEND);
	D16(PIXC_BTRANSP);
	D16(PIXC_INTRSTAT);
	D32(PIXC_RYCON);
	D32(PIXC_GUCON);
	D32(PIXC_BVCON);
	D32(PIXC_CCBIAS);
	D32(PIXC_TC);
#endif

	parent = debugfs_create_dir("pll", top);
	D16(PLL_CTL);
	D16(PLL_DIV);
	D16(PLL_LOCKCNT);
	D16(PLL_STAT);
	D16(VR_CTL);
	D32(CHIPID);	

#if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL)
	parent = debugfs_create_dir("ppi", top);
# ifdef PPI_CONTROL
	bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1);
# endif
# ifdef PPI0_CONTROL
	PPI(0);
# endif
# ifdef PPI1_CONTROL
	PPI(1);
# endif
#endif

#ifdef PWM_CTRL
	parent = debugfs_create_dir("pwm", top);
	D16(PWM_CTRL);
	D16(PWM_STAT);
	D16(PWM_TM);
	D16(PWM_DT);
	D16(PWM_GATE);
	D16(PWM_CHA);
	D16(PWM_CHB);
	D16(PWM_CHC);
	D16(PWM_SEG);
	D16(PWM_SYNCWT);
	D16(PWM_CHAL);
	D16(PWM_CHBL);
	D16(PWM_CHCL);
	D16(PWM_LSI);
	D16(PWM_STAT2);
#endif

#ifdef RSI_CONFIG
	parent = debugfs_create_dir("rsi", top);
	D32(RSI_ARGUMENT);
	D16(RSI_CEATA_CONTROL);
	D16(RSI_CLK_CONTROL);
	D16(RSI_COMMAND);
	D16(RSI_CONFIG);
	D16(RSI_DATA_CNT);
	D16(RSI_DATA_CONTROL);
	D16(RSI_DATA_LGTH);
	D32(RSI_DATA_TIMER);
	D16(RSI_EMASK);
	D16(RSI_ESTAT);
	D32(RSI_FIFO);
	D16(RSI_FIFO_CNT);
	D32(RSI_MASK0);
	D32(RSI_MASK1);
	D16(RSI_PID0);
	D16(RSI_PID1);
	D16(RSI_PID2);
	D16(RSI_PID3);
	D16(RSI_PID4);
	D16(RSI_PID5);
	D16(RSI_PID6);
	D16(RSI_PID7);
	D16(RSI_PWR_CONTROL);
	D16(RSI_RD_WAIT_EN);
	D32(RSI_RESPONSE0);
	D32(RSI_RESPONSE1);
	D32(RSI_RESPONSE2);
	D32(RSI_RESPONSE3);
	D16(RSI_RESP_CMD);
	D32(RSI_STATUS);
	D_WO(RSI_STATUSCL, 16);
#endif

#ifdef RTC_ALARM
	parent = debugfs_create_dir("rtc", top);
	D32(RTC_ALARM);
	D16(RTC_ICTL);
	D16(RTC_ISTAT);
	D16(RTC_PREN);
	D32(RTC_STAT);
	D16(RTC_SWCNT);
#endif

#ifdef SDH_CFG
	parent = debugfs_create_dir("sdh", top);
	D32(SDH_ARGUMENT);
	D16(SDH_CFG);
	D16(SDH_CLK_CTL);
	D16(SDH_COMMAND);
	D_RO(SDH_DATA_CNT, 16);
	D16(SDH_DATA_CTL);
	D16(SDH_DATA_LGTH);
	D32(SDH_DATA_TIMER);
	D16(SDH_E_MASK);
	D16(SDH_E_STATUS);
	D32(SDH_FIFO);
	D_RO(SDH_FIFO_CNT, 16);
	D32(SDH_MASK0);
	D32(SDH_MASK1);
	D_RO(SDH_PID0, 16);
	D_RO(SDH_PID1, 16);
	D_RO(SDH_PID2, 16);
	D_RO(SDH_PID3, 16);
	D_RO(SDH_PID4, 16);
	D_RO(SDH_PID5, 16);
	D_RO(SDH_PID6, 16);
	D_RO(SDH_PID7, 16);
	D16(SDH_PWR_CTL);
	D16(SDH_RD_WAIT_EN);
	D_RO(SDH_RESPONSE0, 32);
	D_RO(SDH_RESPONSE1, 32);
	D_RO(SDH_RESPONSE2, 32);
	D_RO(SDH_RESPONSE3, 32);
	D_RO(SDH_RESP_CMD, 16);
	D_RO(SDH_STATUS, 32);
	D_WO(SDH_STATUS_CLR, 16);
#endif

#ifdef SECURE_CONTROL
	parent = debugfs_create_dir("security", top);
	D16(SECURE_CONTROL);
	D16(SECURE_STATUS);
	D32(SECURE_SYSSWT);
#endif

	parent = debugfs_create_dir("sic", top);
	D16(SWRST);
	D16(SYSCR);
	D16(SIC_RVECT);
	D32(SIC_IAR0);
	D32(SIC_IAR1);
	D32(SIC_IAR2);
#ifdef SIC_IAR3
	D32(SIC_IAR3);
#endif
#ifdef SIC_IAR4
	D32(SIC_IAR4);
	D32(SIC_IAR5);
	D32(SIC_IAR6);
#endif
#ifdef SIC_IAR7
	D32(SIC_IAR7);
#endif
#ifdef SIC_IAR8
	D32(SIC_IAR8);
	D32(SIC_IAR9);
	D32(SIC_IAR10);
	D32(SIC_IAR11);
#endif
#ifdef SIC_IMASK
	D32(SIC_IMASK);
	D32(SIC_ISR);
	D32(SIC_IWR);
#endif
#ifdef SIC_IMASK0
	D32(SIC_IMASK0);
	D32(SIC_IMASK1);
	D32(SIC_ISR0);
	D32(SIC_ISR1);
	D32(SIC_IWR0);
	D32(SIC_IWR1);
#endif
#ifdef SIC_IMASK2
	D32(SIC_IMASK2);
	D32(SIC_ISR2);
	D32(SIC_IWR2);
#endif
#ifdef SICB_RVECT
	D16(SICB_SWRST);
	D16(SICB_SYSCR);
	D16(SICB_RVECT);
	D32(SICB_IAR0);
	D32(SICB_IAR1);
	D32(SICB_IAR2);
	D32(SICB_IAR3);
	D32(SICB_IAR4);
	D32(SICB_IAR5);
	D32(SICB_IAR6);
	D32(SICB_IAR7);
	D32(SICB_IMASK0);
	D32(SICB_IMASK1);
	D32(SICB_ISR0);
	D32(SICB_ISR1);
	D32(SICB_IWR0);
	D32(SICB_IWR1);
#endif

	parent = debugfs_create_dir("spi", top);
#ifdef SPI0_REGBASE
	SPI(0);
#endif
#ifdef SPI1_REGBASE
	SPI(1);
#endif
#ifdef SPI2_REGBASE
	SPI(2);
#endif

	parent = debugfs_create_dir("sport", top);
#ifdef SPORT0_STAT
	SPORT(0);
#endif
#ifdef SPORT1_STAT
	SPORT(1);
#endif
#ifdef SPORT2_STAT
	SPORT(2);
#endif
#ifdef SPORT3_STAT
	SPORT(3);
#endif

#if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
	parent = debugfs_create_dir("twi", top);
# ifdef TWI_CLKDIV
	bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
# endif
# ifdef TWI0_CLKDIV
	TWI(0);
# endif
# ifdef TWI1_CLKDIV
	TWI(1);
# endif
#endif

	parent = debugfs_create_dir("uart", top);
#ifdef BFIN_UART_DLL
	bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
#endif
#ifdef UART0_DLL
	UART(0);
#endif
#ifdef UART1_DLL
	UART(1);
#endif
#ifdef UART2_DLL
	UART(2);
#endif
#ifdef UART3_DLL
	UART(3);
#endif

#ifdef USB_FADDR
	parent = debugfs_create_dir("usb", top);
	D16(USB_FADDR);
	D16(USB_POWER);
	D16(USB_INTRTX);
	D16(USB_INTRRX);
	D16(USB_INTRTXE);
	D16(USB_INTRRXE);
	D16(USB_INTRUSB);
	D16(USB_INTRUSBE);
	D16(USB_FRAME);
	D16(USB_INDEX);
	D16(USB_TESTMODE);
	D16(USB_GLOBINTR);
	D16(USB_GLOBAL_CTL);
	D16(USB_TX_MAX_PACKET);
	D16(USB_CSR0);
	D16(USB_TXCSR);
	D16(USB_RX_MAX_PACKET);
	D16(USB_RXCSR);
	D16(USB_COUNT0);
	D16(USB_RXCOUNT);
	D16(USB_TXTYPE);
	D16(USB_NAKLIMIT0);
	D16(USB_TXINTERVAL);
	D16(USB_RXTYPE);
	D16(USB_RXINTERVAL);
	D16(USB_TXCOUNT);
	D16(USB_EP0_FIFO);
	D16(USB_EP1_FIFO);
	D16(USB_EP2_FIFO);
	D16(USB_EP3_FIFO);
	D16(USB_EP4_FIFO);
	D16(USB_EP5_FIFO);
	D16(USB_EP6_FIFO);
	D16(USB_EP7_FIFO);
	D16(USB_OTG_DEV_CTL);
	D16(USB_OTG_VBUS_IRQ);
	D16(USB_OTG_VBUS_MASK);
	D16(USB_LINKINFO);
	D16(USB_VPLEN);
	D16(USB_HS_EOF1);
	D16(USB_FS_EOF1);
	D16(USB_LS_EOF1);
	D16(USB_APHY_CNTRL);
	D16(USB_APHY_CALIB);
	D16(USB_APHY_CNTRL2);
	D16(USB_PHY_TEST);
	D16(USB_PLLOSC_CTRL);
	D16(USB_SRP_CLKDIV);
	D16(USB_EP_NI0_TXMAXP);
	D16(USB_EP_NI0_TXCSR);
	D16(USB_EP_NI0_RXMAXP);
	D16(USB_EP_NI0_RXCSR);
	D16(USB_EP_NI0_RXCOUNT);
	D16(USB_EP_NI0_TXTYPE);
	D16(USB_EP_NI0_TXINTERVAL);
	D16(USB_EP_NI0_RXTYPE);
	D16(USB_EP_NI0_RXINTERVAL);
	D16(USB_EP_NI0_TXCOUNT);
	D16(USB_EP_NI1_TXMAXP);
	D16(USB_EP_NI1_TXCSR);
	D16(USB_EP_NI1_RXMAXP);
	D16(USB_EP_NI1_RXCSR);
	D16(USB_EP_NI1_RXCOUNT);
	D16(USB_EP_NI1_TXTYPE);
	D16(USB_EP_NI1_TXINTERVAL);
	D16(USB_EP_NI1_RXTYPE);
	D16(USB_EP_NI1_RXINTERVAL);
	D16(USB_EP_NI1_TXCOUNT);
	D16(USB_EP_NI2_TXMAXP);
	D16(USB_EP_NI2_TXCSR);
	D16(USB_EP_NI2_RXMAXP);
	D16(USB_EP_NI2_RXCSR);
	D16(USB_EP_NI2_RXCOUNT);
	D16(USB_EP_NI2_TXTYPE);
	D16(USB_EP_NI2_TXINTERVAL);
	D16(USB_EP_NI2_RXTYPE);
	D16(USB_EP_NI2_RXINTERVAL);
	D16(USB_EP_NI2_TXCOUNT);
	D16(USB_EP_NI3_TXMAXP);
	D16(USB_EP_NI3_TXCSR);
	D16(USB_EP_NI3_RXMAXP);
	D16(USB_EP_NI3_RXCSR);
	D16(USB_EP_NI3_RXCOUNT);
	D16(USB_EP_NI3_TXTYPE);
	D16(USB_EP_NI3_TXINTERVAL);
	D16(USB_EP_NI3_RXTYPE);
	D16(USB_EP_NI3_RXINTERVAL);
	D16(USB_EP_NI3_TXCOUNT);
	D16(USB_EP_NI4_TXMAXP);
	D16(USB_EP_NI4_TXCSR);
	D16(USB_EP_NI4_RXMAXP);
	D16(USB_EP_NI4_RXCSR);
	D16(USB_EP_NI4_RXCOUNT);
	D16(USB_EP_NI4_TXTYPE);
	D16(USB_EP_NI4_TXINTERVAL);
	D16(USB_EP_NI4_RXTYPE);
	D16(USB_EP_NI4_RXINTERVAL);
	D16(USB_EP_NI4_TXCOUNT);
	D16(USB_EP_NI5_TXMAXP);
	D16(USB_EP_NI5_TXCSR);
	D16(USB_EP_NI5_RXMAXP);
	D16(USB_EP_NI5_RXCSR);
	D16(USB_EP_NI5_RXCOUNT);
	D16(USB_EP_NI5_TXTYPE);
	D16(USB_EP_NI5_TXINTERVAL);
	D16(USB_EP_NI5_RXTYPE);
	D16(USB_EP_NI5_RXINTERVAL);
	D16(USB_EP_NI5_TXCOUNT);
	D16(USB_EP_NI6_TXMAXP);
	D16(USB_EP_NI6_TXCSR);
	D16(USB_EP_NI6_RXMAXP);
	D16(USB_EP_NI6_RXCSR);
	D16(USB_EP_NI6_RXCOUNT);
	D16(USB_EP_NI6_TXTYPE);
	D16(USB_EP_NI6_TXINTERVAL);
	D16(USB_EP_NI6_RXTYPE);
	D16(USB_EP_NI6_RXINTERVAL);
	D16(USB_EP_NI6_TXCOUNT);
	D16(USB_EP_NI7_TXMAXP);
	D16(USB_EP_NI7_TXCSR);
	D16(USB_EP_NI7_RXMAXP);
	D16(USB_EP_NI7_RXCSR);
	D16(USB_EP_NI7_RXCOUNT);
	D16(USB_EP_NI7_TXTYPE);
	D16(USB_EP_NI7_TXINTERVAL);
	D16(USB_EP_NI7_RXTYPE);
	D16(USB_EP_NI7_RXINTERVAL);
	D16(USB_EP_NI7_TXCOUNT);
	D16(USB_DMA_INTERRUPT);
	D16(USB_DMA0CONTROL);
	D16(USB_DMA0ADDRLOW);
	D16(USB_DMA0ADDRHIGH);
	D16(USB_DMA0COUNTLOW);
	D16(USB_DMA0COUNTHIGH);
	D16(USB_DMA1CONTROL);
	D16(USB_DMA1ADDRLOW);
	D16(USB_DMA1ADDRHIGH);
	D16(USB_DMA1COUNTLOW);
	D16(USB_DMA1COUNTHIGH);
	D16(USB_DMA2CONTROL);
	D16(USB_DMA2ADDRLOW);
	D16(USB_DMA2ADDRHIGH);
	D16(USB_DMA2COUNTLOW);
	D16(USB_DMA2COUNTHIGH);
	D16(USB_DMA3CONTROL);
	D16(USB_DMA3ADDRLOW);
	D16(USB_DMA3ADDRHIGH);
	D16(USB_DMA3COUNTLOW);
	D16(USB_DMA3COUNTHIGH);
	D16(USB_DMA4CONTROL);
	D16(USB_DMA4ADDRLOW);
	D16(USB_DMA4ADDRHIGH);
	D16(USB_DMA4COUNTLOW);
	D16(USB_DMA4COUNTHIGH);
	D16(USB_DMA5CONTROL);
	D16(USB_DMA5ADDRLOW);
	D16(USB_DMA5ADDRHIGH);
	D16(USB_DMA5COUNTLOW);
	D16(USB_DMA5COUNTHIGH);
	D16(USB_DMA6CONTROL);
	D16(USB_DMA6ADDRLOW);
	D16(USB_DMA6ADDRHIGH);
	D16(USB_DMA6COUNTLOW);
	D16(USB_DMA6COUNTHIGH);
	D16(USB_DMA7CONTROL);
	D16(USB_DMA7ADDRLOW);
	D16(USB_DMA7ADDRHIGH);
	D16(USB_DMA7COUNTLOW);
	D16(USB_DMA7COUNTHIGH);
#endif

#ifdef WDOG_CNT
	parent = debugfs_create_dir("watchdog", top);
	D32(WDOG_CNT);
	D16(WDOG_CTL);
	D32(WDOG_STAT);
#endif
#ifdef WDOGA_CNT
	parent = debugfs_create_dir("watchdog", top);
	D32(WDOGA_CNT);
	D16(WDOGA_CTL);
	D32(WDOGA_STAT);
	D32(WDOGB_CNT);
	D16(WDOGB_CTL);
	D32(WDOGB_STAT);
#endif

	
#ifdef FIO_FLAG_D
#define PORTFIO FIO_FLAG_D
#endif
	
#ifdef FIO0_FLAG_D
#define PORTFIO FIO0_FLAG_D
#endif
#ifdef FIO1_FLAG_D
#define PORTGIO FIO1_FLAG_D
#endif
#ifdef FIO2_FLAG_D
#define PORTHIO FIO2_FLAG_D
#endif
	parent = debugfs_create_dir("port", top);
#ifdef PORTFIO
	PORT(PORTFIO, 'F');
#endif
#ifdef PORTGIO
	PORT(PORTGIO, 'G');
#endif
#ifdef PORTHIO
	PORT(PORTHIO, 'H');
#endif

#ifdef __ADSPBF51x__
	D16(PORTF_FER);
	D16(PORTF_DRIVE);
	D16(PORTF_HYSTERESIS);
	D16(PORTF_MUX);

	D16(PORTG_FER);
	D16(PORTG_DRIVE);
	D16(PORTG_HYSTERESIS);
	D16(PORTG_MUX);

	D16(PORTH_FER);
	D16(PORTH_DRIVE);
	D16(PORTH_HYSTERESIS);
	D16(PORTH_MUX);

	D16(MISCPORT_DRIVE);
	D16(MISCPORT_HYSTERESIS);
#endif	

#ifdef __ADSPBF52x__
	D16(PORTF_FER);
	D16(PORTF_DRIVE);
	D16(PORTF_HYSTERESIS);
	D16(PORTF_MUX);
	D16(PORTF_SLEW);

	D16(PORTG_FER);
	D16(PORTG_DRIVE);
	D16(PORTG_HYSTERESIS);
	D16(PORTG_MUX);
	D16(PORTG_SLEW);

	D16(PORTH_FER);
	D16(PORTH_DRIVE);
	D16(PORTH_HYSTERESIS);
	D16(PORTH_MUX);
	D16(PORTH_SLEW);

	D16(MISCPORT_DRIVE);
	D16(MISCPORT_HYSTERESIS);
	D16(MISCPORT_SLEW);
#endif	

#ifdef BF537_FAMILY
	D16(PORTF_FER);
	D16(PORTG_FER);
	D16(PORTH_FER);
	D16(PORT_MUX);
#endif	

#ifdef BF538_FAMILY
	D16(PORTCIO_FER);
	D16(PORTCIO);
	D16(PORTCIO_CLEAR);
	D16(PORTCIO_SET);
	D16(PORTCIO_TOGGLE);
	D16(PORTCIO_DIR);
	D16(PORTCIO_INEN);

	D16(PORTDIO);
	D16(PORTDIO_CLEAR);
	D16(PORTDIO_DIR);
	D16(PORTDIO_FER);
	D16(PORTDIO_INEN);
	D16(PORTDIO_SET);
	D16(PORTDIO_TOGGLE);

	D16(PORTEIO);
	D16(PORTEIO_CLEAR);
	D16(PORTEIO_DIR);
	D16(PORTEIO_FER);
	D16(PORTEIO_INEN);
	D16(PORTEIO_SET);
	D16(PORTEIO_TOGGLE);
#endif	

#ifdef __ADSPBF54x__
	{
		int num;
		unsigned long base;

		base = PORTA_FER;
		for (num = 0; num < 10; ++num) {
			PORT(base, num);
			base += sizeof(struct bfin_gpio_regs);
		}

	}
#endif	

	debug_mmrs_dentry = top;

	return 0;
}
static int dma_setup(struct scsi_cmnd *cmd, int dir_in)
{
    unsigned short cntr = CNTR_PDMD | CNTR_INTEN;
    unsigned long addr = virt_to_bus(cmd->SCp.ptr);
    struct Scsi_Host *instance = cmd->device->host;

    /* don't allow DMA if the physical address is bad */
    if (addr & A2091_XFER_MASK)
    {
	HDATA(instance)->dma_bounce_len = (cmd->SCp.this_residual + 511)
	    & ~0x1ff;
	HDATA(instance)->dma_bounce_buffer =
	    kmalloc (HDATA(instance)->dma_bounce_len, GFP_KERNEL);
	
	/* can't allocate memory; use PIO */
	if (!HDATA(instance)->dma_bounce_buffer) {
	    HDATA(instance)->dma_bounce_len = 0;
	    return 1;
	}

	/* get the physical address of the bounce buffer */
	addr = virt_to_bus(HDATA(instance)->dma_bounce_buffer);

	/* the bounce buffer may not be in the first 16M of physmem */
	if (addr & A2091_XFER_MASK) {
	    /* we could use chipmem... maybe later */
	    kfree (HDATA(instance)->dma_bounce_buffer);
	    HDATA(instance)->dma_bounce_buffer = NULL;
	    HDATA(instance)->dma_bounce_len = 0;
	    return 1;
	}

	if (!dir_in) {
		/* copy to bounce buffer for a write */
		memcpy (HDATA(instance)->dma_bounce_buffer,
			cmd->SCp.ptr, cmd->SCp.this_residual);
	}
    }

    /* setup dma direction */
    if (!dir_in)
	cntr |= CNTR_DDIR;

    /* remember direction */
    HDATA(cmd->device->host)->dma_dir = dir_in;

    DMA(cmd->device->host)->CNTR = cntr;

    /* setup DMA *physical* address */
    DMA(cmd->device->host)->ACR = addr;

    if (dir_in){
	/* invalidate any cache */
	cache_clear (addr, cmd->SCp.this_residual);
    }else{
	/* push any dirty cache */
	cache_push (addr, cmd->SCp.this_residual);
      }
    /* start DMA */
    DMA(cmd->device->host)->ST_DMA = 1;

    /* return success */
    return 0;
}