void edma_dspi_rx_setup(uint32_t dmaChl, uint32_t destAddr)
{
// Configure the DMAMUX for eDMA channel
DMAMUX_HAL_SetChannelCmd(DMAMUX_BASE, dmaChl, false);
DMAMUX_HAL_SetTriggerSource(DMAMUX_BASE, dmaChl, kDmaRequestMux0SPI0Rx & 0xFF);
DMAMUX_HAL_SetChannelCmd(DMAMUX_BASE, dmaChl, true);
// Configure TCD
EDMA_HAL_HTCDClearReg(DMA_BASE, dmaChl);
edma_software_tcd_t stcd;
edma_transfer_config_t config;
config.destAddr = destAddr;
config.destLastAddrAdjust = 0;
config.destModulo = kEDMAModuloDisable;
config.destOffset = 4;
config.destTransferSize = kEDMATransferSize_4Bytes;
config.srcAddr = (uint32_t)&SPI0->POPR;
config.srcLastAddrAdjust = 0;
config.srcModulo = kEDMAModuloDisable;
config.srcOffset = 0;
config.srcTransferSize = kEDMATransferSize_4Bytes;
config.majorLoopCount = TEST_DATA_LEN;
config.minorLoopCount = 4;
EDMA_HAL_STCDSetBasicTransfer(DMA_BASE, &stcd, &config, true, true);
EDMA_HAL_PushSTCDToHTCD(DMA_BASE, dmaChl, &stcd);
// Configure interrupt
IRQn_Type irqNumber;
irqNumber = g_edmaIrqId[0][dmaChl];
INT_SYS_EnableIRQ(irqNumber);
}
/*FUNCTION**********************************************************************
*
* Function Name : DSPI_DRV_DmaTxCallback
* Description : Callback function, this called when DMA transmitting data
* completed
*
*END**************************************************************************/
static void DSPI_DRV_DmaTxCallback(void *param, dma_channel_status_t status)
{
uint32_t instance = (uint32_t)param;
SPI_Type *base = g_dspiBase[instance];
dspi_dma_master_state_t * dspiDmaState = (dspi_dma_master_state_t *)g_dspiStatePtr[instance];
uint32_t dmaChannel;
DMAMUX_Type *dmamuxbase;
dmaChannel = dspiDmaState->dmaTxDataChannel.channel;
dmamuxbase = g_dmamuxBase[dmaChannel/FSL_FEATURE_DMAMUX_MODULE_CHANNEL];
// DMA_DRV_ClearStatus(&dspiDmaState->dmaTxDataChannel);
DMAMUX_HAL_SetChannelCmd(dmamuxbase, dmaChannel, false);
DMAMUX_HAL_SetChannelCmd(dmamuxbase, dmaChannel, true);
/* Stop DMA Tx channel */
DMA_DRV_StopChannel(&dspiDmaState->dmaTxDataChannel);
/* Setup DMA to transmit the last frame */
/* Have one more byte, config DMA Rx channel to receive this byte */
DMA_DRV_ConfigTransfer(&dspiDmaState->dmaTxDataChannel,
kDmaPeripheralToPeripheral,
4u, (uint32_t)(&s_lastCmdData), /* src is data register */
DSPI_HAL_GetMasterPushrRegAddr(base), /* dest is temporary location */
4u);
/* Register callback */
DMA_DRV_RegisterCallback(&dspiDmaState->dmaTxDataChannel, DSPI_DRV_DmaTxLastCallback, (void *)instance);
/* Enable the DMA peripheral request */
DMA_DRV_StartChannel(&dspiDmaState->dmaTxDataChannel);
}
/*!
* @brief Initiate (start) a transfer using DMA. This is not a public API as it is called from
* other driver functions
*/
spi_status_t SPI_DRV_DmaMasterStartTransfer(uint32_t instance,
const spi_dma_master_user_config_t * device)
{
/* instantiate local variable of type spi_dma_master_state_t and point to global state */
spi_dma_master_state_t * spiDmaState = (spi_dma_master_state_t *)g_spiStatePtr[instance];
/* For temporarily storing DMA register channel */
uint8_t txChannel, rxChannel;
void * param;
uint32_t calculatedBaudRate;
SPI_Type *base = g_spiBase[instance];
uint32_t transferSizeInBytes; /* DMA transfer size in bytes */
/* Initialize s_byteToSend */
s_byteToSend = 0;
/* If the transfer count is zero, then return immediately.*/
if (spiDmaState->remainingSendByteCount == 0)
{
/* Signal the synchronous completion object if the transfer wasn't async.
* Otherwise, when we return the the sync function we'll get stuck in the sync wait loop.
*/
if (spiDmaState->isTransferBlocking)
{
OSA_SemaPost(&spiDmaState->irqSync);
}
return kStatus_SPI_Success;
}
/* Configure bus for this device. If NULL is passed, we assume the caller has
* preconfigured the bus using SPI_DRV_DmaMasterConfigureBus().
* Do nothing for calculatedBaudRate. If the user wants to know the calculatedBaudRate
* then they can call this function separately.
*/
if (device)
{
SPI_DRV_DmaMasterConfigureBus(instance, device, &calculatedBaudRate);
}
/* In order to flush any remaining data in the shift register, disable then enable the SPI */
SPI_HAL_Disable(base);
SPI_HAL_Enable(base);
#if FSL_FEATURE_SPI_16BIT_TRANSFERS
/* Check the transfer byte count. If bits/frame > 8, meaning 2 bytes, and if
* the transfer byte count is an odd count we'll have to round down the RX transfer byte count
* to the next lowest even number by one and assert a flag to indicate in the interrupt handler
* that we take care of sending and receiving this last byte. We'll round up TX byte count.
*/
if (SPI_HAL_Get8or16BitMode(base) == kSpi16BitMode) /* Applies to 16-bit transfers */
{
/* Odd byte count for 16-bit transfers, set the extraByte flag */
if (spiDmaState->remainingSendByteCount & 1UL) /* If odd byte count */
{
transferSizeInBytes = 2; /* Set transfer size to two bytes for the DMA operation */
spiDmaState->extraByte = true; /* Set the extraByte flag */
/* Round up TX byte count so when DMA completes, all data would've been sent */
spiDmaState->remainingSendByteCount += 1U;
// spiDmaState->remainingSendByteCount &= ~1U;
/* Round down RX byte count which means at the end of the RX DMA transfer, we'll need
* to set up an interrupt to get the last byte.
*/
spiDmaState->remainingReceiveByteCount &= ~1U;
/* Store the transfer byte count to the run-time state struct
* for later use in the interrupt handler.
*/
spiDmaState->transferByteCnt = spiDmaState->remainingSendByteCount;
}
/* Even byte count for 16-bit transfers, clear the extraByte flag */
else
{
transferSizeInBytes = 2; /* Set transfer size to two bytes for the DMA operation */
spiDmaState->extraByte = false; /* Clear the extraByte flag */
}
}
else /* For 8-bit transfers */
{
transferSizeInBytes = 1;
spiDmaState->extraByte = false;
}
#else
transferSizeInBytes = 1;
#endif
param = (void *)(instance); /* For DMA callback, set "param" as the SPI instance number */
rxChannel = spiDmaState->dmaReceive.channel;
txChannel = spiDmaState->dmaTransmit.channel;
/* Only need to set the DMA reg base addr once since it should be the same for all code */
DMA_Type *dmabase = g_dmaBase[rxChannel/FSL_FEATURE_DMA_DMAMUX_CHANNELS];
DMAMUX_Type *dmamuxbase = g_dmamuxBase[txChannel/FSL_FEATURE_DMAMUX_MODULE_CHANNEL];
/* Check that we're not busy.*/
if (spiDmaState->isTransferInProgress)
{
return kStatus_SPI_Busy;
}
/* Save information about the transfer for use by the ISR.*/
spiDmaState->isTransferInProgress = true;
/* The DONE needs to be cleared before programming the channel's TCDs for the next
* transfer.
*/
DMA_HAL_ClearStatus(dmabase, rxChannel);
DMA_HAL_ClearStatus(dmabase, txChannel);
/* Disable and enable the TX and RX DMA channel at the DMA mux. Doing so will prevent an
* inadvertent DMA transfer when the TX and RX DMA channel ERQ bit is set after having been
* cleared from a previous DMA transfer (clearing of the ERQ bit is automatically performed
* at the end of a transfer when D_REQ is set).
*/
DMAMUX_HAL_SetChannelCmd(dmamuxbase, txChannel, false);
DMAMUX_HAL_SetChannelCmd(dmamuxbase, txChannel, true);
DMAMUX_HAL_SetChannelCmd(dmamuxbase, rxChannel, false);
DMAMUX_HAL_SetChannelCmd(dmamuxbase, rxChannel, true);
/************************************************************************************
* Set up the RX DMA channel Transfer Control Descriptor (TCD)
* Note, if there is no receive byte count, then bypass RX DMA set up.
***********************************************************************************/
if (spiDmaState->remainingReceiveByteCount)
{
/* If no receive buffer then disable incrementing the destination and set the destination
* to a temporary location
*/
if (!spiDmaState->receiveBuffer)
{
/* Set up this channel's control which includes enabling the DMA interrupt */
DMA_DRV_ConfigTransfer(&spiDmaState->dmaReceive,
kDmaPeripheralToMemory,
transferSizeInBytes,
SPI_HAL_GetDataRegAddr(base), /* src is data register */
(uint32_t)(&s_rxBuffIfNull), /* dest is temporary location */
(uint32_t)(spiDmaState->remainingReceiveByteCount));
/* Do not increment the destination address */
DMA_HAL_SetDestIncrementCmd(dmabase, rxChannel, false);
}
else
{
/* Set up this channel's control which includes enabling the DMA interrupt */
DMA_DRV_ConfigTransfer(&spiDmaState->dmaReceive,
kDmaPeripheralToMemory,
transferSizeInBytes,
SPI_HAL_GetDataRegAddr(base), /* src is data register */
(uint32_t)(spiDmaState->receiveBuffer),/* dest is rx buffer */
(uint32_t)(spiDmaState->remainingReceiveByteCount));
}
/* For SPI16 modules, if the bits/frame is 16, then we need to adjust the destination
* size to still be 8-bits since the DMA_DRV_ConfigTransfer sets this to 16-bits, but
* we always provide a 8-bit buffer.
*/
if (transferSizeInBytes == 2)
{
DMA_HAL_SetDestTransferSize(dmabase, rxChannel, kDmaTransfersize8bits);
}
/* Enable the cycle steal mode which forces a single read/write transfer per request */
DMA_HAL_SetCycleStealCmd(dmabase, rxChannel, true);
/* Enable the DMA peripheral request */
DMA_DRV_StartChannel(&spiDmaState->dmaReceive);
/* Register callback for DMA interrupt */
DMA_DRV_RegisterCallback(&spiDmaState->dmaReceive, SPI_DRV_DmaMasterCallback, param);
/* Enable the SPI RX DMA Request after the TX DMA request is enabled. This is done to
* make sure that the RX DMA channel does not end prematurely before we've completely set
* up the TX DMA channel since part of the TX DMA set up involves placing 1 or 2 bytes of
* data into the send data register which causes an immediate transfer.
*/
}
/************************************************************************************
* Set up the TX DMA channel Transfer Control Descriptor (TCD)
* Note, if there is no source buffer (if user passes in NULL), then send zeros
***********************************************************************************/
/* Per the reference manual, before enabling the SPI transmit DMA request, we first need
* to read the status register and then write to the SPI data register. Afterwards, we need
* to decrement the sendByteCount and perform other driver maintenance functions.
*/
/* Read the SPI Status register */
SPI_HAL_IsTxBuffEmptyPending(base);
/* Start the transfer by writing the first byte/word to the SPI data register.
* If a send buffer was provided, the byte/word comes from there. Otherwise we just send zeros.
* This will cause an immeidate transfer which in some cases may cause the RX DMA channel to
* complete before having the chance to completely set up the TX DMA channel. As such, we'll
* enable the RX DMA channel last.
*/
#if FSL_FEATURE_SPI_16BIT_TRANSFERS
if (transferSizeInBytes == 2) /* 16-bit transfers for SPI16 module */
{
if (spiDmaState->sendBuffer)
{
s_byteToSend = *(spiDmaState->sendBuffer);
SPI_HAL_WriteDataLow(base, s_byteToSend);
++spiDmaState->sendBuffer;
s_byteToSend = *(spiDmaState->sendBuffer);
SPI_HAL_WriteDataHigh(base, s_byteToSend);
++spiDmaState->sendBuffer;
}
else /* Else, if no send buffer, write zeros */
{
SPI_HAL_WriteDataLow(base, s_byteToSend);
SPI_HAL_WriteDataHigh(base, s_byteToSend);
}
spiDmaState->remainingSendByteCount -= 2; /* Decrement the send byte count by 2 */
}
else /* 8-bit transfers for SPI16 module */
{
if (spiDmaState->sendBuffer)
{
s_byteToSend = *(spiDmaState->sendBuffer);
++spiDmaState->sendBuffer;
}
SPI_HAL_WriteDataLow(base, s_byteToSend); /* If no send buffer, s_byteToSend=0 */
--spiDmaState->remainingSendByteCount; /* Decrement the send byte count */
}
#else
/* For SPI modules that do not support 16-bit transfers */
if (spiDmaState->sendBuffer)
{
s_byteToSend = *(spiDmaState->sendBuffer);
++spiDmaState->sendBuffer;
}
SPI_HAL_WriteData(base, s_byteToSend); /* If no send buffer, s_byteToSend=0 */
--spiDmaState->remainingSendByteCount; /* Decrement the send byte count */
#endif
/* If there are no more bytes to send then return without setting up the TX DMA channel
* and let the receive DMA channel complete the transfer if the RX DMA channel was setup.
* If the RX DMA channel was not set up (due to odd byte count of 1 in 16-bit mode), enable
* the interrupt to get the received byte.
*/
if (!spiDmaState->remainingSendByteCount) /* No more bytes to send */
{
if (spiDmaState->remainingReceiveByteCount)
{
/* Enable the RX DMA channel request now */
SPI_HAL_SetRxDmaCmd(base, true);
return kStatus_SPI_Success;
}
else /* If RX DMA chan not setup then enable the interrupt to get the received byte */
{
SPI_HAL_SetIntMode(base, kSpiTxEmptyInt, true);
return kStatus_SPI_Success;
}
}
/* Else, since there are more bytes to send, go ahead and set up the TX DMA channel */
else
{
/* If there is a send buffer, data comes from there, else send 0 */
if (spiDmaState->sendBuffer)
{
/* Set up this channel's control which includes enabling the DMA interrupt */
DMA_DRV_ConfigTransfer(&spiDmaState->dmaTransmit, kDmaMemoryToPeripheral,
transferSizeInBytes,
(uint32_t)(spiDmaState->sendBuffer),
SPI_HAL_GetDataRegAddr(base),
(uint32_t)(spiDmaState->remainingSendByteCount));
}
else /* Configure TX DMA channel to send zeros */
{
/* Set up this channel's control which includes enabling the DMA interrupt */
DMA_DRV_ConfigTransfer(&spiDmaState->dmaTransmit, kDmaMemoryToPeripheral,
transferSizeInBytes,
(uint32_t)(&s_byteToSend),
SPI_HAL_GetDataRegAddr(base),
(uint32_t)(spiDmaState->remainingSendByteCount));
/* Now clear SINC since we are only sending zeroes, don't increment source */
DMA_HAL_SetSourceIncrementCmd(dmabase, txChannel, false);
}
/* For SPI16 modules, if the bits/frame is 16, then we need to adjust the source
* size to still be 8-bits since the DMA_DRV_ConfigTransfer sets this to 16-bits, but
* we always provide a 8-bit buffer.
*/
if (transferSizeInBytes == 2)
{
DMA_HAL_SetSourceTransferSize(dmabase, txChannel, kDmaTransfersize8bits);
}
/* Enable the cycle steal mode which forces a single read/write transfer per request */
DMA_HAL_SetCycleStealCmd(dmabase, txChannel, true);
/* Now, disable the TX chan interrupt since we'll use the RX chan interrupt */
DMA_HAL_SetIntCmd(dmabase, txChannel, false);
/* Enable the DMA peripheral request */
DMA_DRV_StartChannel(&spiDmaState->dmaTransmit);
/* Enable the SPI TX DMA Request */
SPI_HAL_SetTxDmaCmd(base, true);
/* Enable the SPI RX DMA Request after the TX DMA request is enabled. This is done to
* make sure that the RX DMA channel does not end prematurely before we've completely set
* up the TX DMA channel since part of the TX DMA set up involves placing 1 or 2 bytes of
* data into the send data register which causes an immediate transfer.
*/
SPI_HAL_SetRxDmaCmd(base, true);
}
return kStatus_SPI_Success;
}