static __inline__ void mga_g400_emit_context(drm_mga_private_t *dev_priv)
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
DMA_LOCALS;
BEGIN_DMA(4);
DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
MGA_MACCESS, ctx->maccess,
MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
MGA_FOGCOL, ctx->fogcolor,
MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset);
DMA_BLOCK(MGA_WFLAG1, ctx->wflag,
MGA_TDUALSTAGE0, ctx->tdualstage0,
MGA_TDUALSTAGE1, ctx->tdualstage1, MGA_FCOL, ctx->fcol);
DMA_BLOCK(MGA_STENCIL, ctx->stencil,
MGA_STENCILCTL, ctx->stencilctl,
MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
ADVANCE_DMA();
}
static void mga_dma_dispatch_blit(struct drm_device * dev, drm_mga_blit_t * blit)
{
drm_mga_private_t *dev_priv = dev->dev_private;
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
struct drm_clip_rect *pbox = sarea_priv->boxes;
int nbox = sarea_priv->nbox;
u32 scandir = 0, i;
DMA_LOCALS;
DRM_DEBUG("\n");
BEGIN_DMA(4 + nbox);
DMA_BLOCK(MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_DWGSYNC, 0x00007100,
MGA_DWGSYNC, 0x00007000);
DMA_BLOCK(MGA_DWGCTL, MGA_DWGCTL_COPY,
MGA_PLNWT, blit->planemask,
MGA_SRCORG, blit->srcorg,
MGA_DSTORG, blit->dstorg);
DMA_BLOCK(MGA_SGN, scandir,
MGA_MACCESS, dev_priv->maccess,
MGA_AR5, blit->ydir * blit->src_pitch,
MGA_PITCH, blit->dst_pitch);
for (i = 0; i < nbox; i++) {
int srcx = pbox[i].x1 + blit->delta_sx;
int srcy = pbox[i].y1 + blit->delta_sy;
int dstx = pbox[i].x1 + blit->delta_dx;
int dsty = pbox[i].y1 + blit->delta_dy;
int h = pbox[i].y2 - pbox[i].y1;
int w = pbox[i].x2 - pbox[i].x1 - 1;
int start;
if (blit->ydir == -1) {
srcy = blit->height - srcy - 1;
}
start = srcy * blit->src_pitch + srcx;
DMA_BLOCK(MGA_AR0, start + w,
MGA_AR3, start,
MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff),
MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h);
}
/* Do something to flush AGP?
*/
/* Force reset of DWGCTL */
DMA_BLOCK(MGA_DMAPAD, 0x00000000,
MGA_PLNWT, ctx->plnwt,
MGA_PITCH, dev_priv->front_pitch,
MGA_DWGCTL, ctx->dwgctl);
ADVANCE_DMA();
}
static inline void mga_g200_emit_context( drm_mga_private_t *dev_priv )
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
DMA_LOCALS;
BEGIN_DMA( 3 );
DMA_BLOCK( MGA_DSTORG, ctx->dstorg,
MGA_MACCESS, ctx->maccess,
MGA_PLNWT, ctx->plnwt,
MGA_DWGCTL, ctx->dwgctl );
DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl,
MGA_FOGCOL, ctx->fogcolor,
MGA_WFLAG, ctx->wflag,
MGA_ZORG, dev_priv->depth_offset );
DMA_BLOCK( MGA_FCOL, ctx->fcol,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000 );
ADVANCE_DMA();
}
static __inline__ void mga_g200_emit_pipe(drm_mga_private_t *dev_priv)
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
unsigned int pipe = sarea_priv->warp_pipe;
DMA_LOCALS;
BEGIN_DMA(3);
DMA_BLOCK(MGA_WIADDR, MGA_WMODE_SUSPEND,
MGA_WVRTXSZ, 0x00000007,
MGA_WFLAG, 0x00000000, MGA_WR24, 0x00000000);
DMA_BLOCK(MGA_WR25, 0x00000100,
MGA_WR34, 0x00000000,
MGA_WR42, 0x0000ffff, MGA_WR60, 0x0000ffff);
/* Padding required due to hardware bug.
*/
DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
MGA_DMAPAD, 0xffffffff,
MGA_DMAPAD, 0xffffffff,
MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] |
MGA_WMODE_START | dev_priv->wagp_enable));
ADVANCE_DMA();
}
static __inline__ void mga_g200_emit_tex0(drm_mga_private_t *dev_priv)
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
DMA_LOCALS;
BEGIN_DMA(4);
DMA_BLOCK(MGA_TEXCTL2, tex->texctl2,
MGA_TEXCTL, tex->texctl,
MGA_TEXFILTER, tex->texfilter,
MGA_TEXBORDERCOL, tex->texbordercol);
DMA_BLOCK(MGA_TEXORG, tex->texorg,
MGA_TEXORG1, tex->texorg1,
MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3);
DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
MGA_TEXWIDTH, tex->texwidth,
MGA_TEXHEIGHT, tex->texheight, MGA_WR24, tex->texwidth);
DMA_BLOCK(MGA_WR34, tex->texheight,
MGA_TEXTRANS, 0x0000ffff,
MGA_TEXTRANSHIGH, 0x0000ffff, MGA_DMAPAD, 0x00000000);
ADVANCE_DMA();
}
static void mga_emit_clip_rect( drm_mga_private_t *dev_priv,
drm_clip_rect_t *box )
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
unsigned int pitch = dev_priv->front_pitch;
DMA_LOCALS;
BEGIN_DMA( 2 );
/* Force reset of DWGCTL on G400 (eliminates clip disable bit).
*/
if (dev_priv->chipset >= MGA_CARD_TYPE_G400) {
DMA_BLOCK(MGA_DWGCTL, ctx->dwgctl,
MGA_LEN + MGA_EXEC, 0x80000000,
MGA_DWGCTL, ctx->dwgctl,
MGA_LEN + MGA_EXEC, 0x80000000);
}
DMA_BLOCK(MGA_DMAPAD, 0x00000000,
MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1,
MGA_YTOP, box->y1 * pitch,
MGA_YBOT, (box->y2 - 1) * pitch);
ADVANCE_DMA();
}
static void mga_dma_dispatch_swap( drm_device_t *dev )
{
drm_mga_private_t *dev_priv = dev->dev_private;
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
drm_clip_rect_t *pbox = sarea_priv->boxes;
int nbox = sarea_priv->nbox;
int i;
DMA_LOCALS;
DRM_DEBUG( "\n" );
sarea_priv->last_frame.head = dev_priv->prim.tail;
sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
BEGIN_DMA( 4 + nbox );
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_DWGSYNC, 0x00007100,
MGA_DWGSYNC, 0x00007000 );
DMA_BLOCK( MGA_DSTORG, dev_priv->front_offset,
MGA_MACCESS, dev_priv->maccess,
MGA_SRCORG, dev_priv->back_offset,
MGA_AR5, dev_priv->front_pitch );
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_PLNWT, 0xffffffff,
MGA_DWGCTL, MGA_DWGCTL_COPY );
for ( i = 0 ; i < nbox ; i++ ) {
drm_clip_rect_t *box = &pbox[i];
u32 height = box->y2 - box->y1;
u32 start = box->y1 * dev_priv->front_pitch;
DRM_DEBUG( " from=%d,%d to=%d,%d\n",
box->x1, box->y1, box->x2, box->y2 );
DMA_BLOCK( MGA_AR0, start + box->x2 - 1,
MGA_AR3, start + box->x1,
MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1,
MGA_YDSTLEN + MGA_EXEC,
(box->y1 << 16) | height );
}
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
MGA_PLNWT, ctx->plnwt,
MGA_SRCORG, dev_priv->front_offset,
MGA_DWGCTL, ctx->dwgctl );
ADVANCE_DMA();
FLUSH_DMA();
DRM_DEBUG( "%s... done.\n", __FUNCTION__ );
}
/* This copies a 64 byte aligned agp region to the frambuffer with a
* standard blit, the ioctl needs to do checking.
*/
static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf,
unsigned int dstorg, unsigned int length )
{
drm_mga_private_t *dev_priv = dev->dev_private;
drm_mga_buf_priv_t *buf_priv = buf->dev_private;
drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM;
u32 y2;
DMA_LOCALS;
DRM_DEBUG( "%s: buf=%d used=%d\n",
__FUNCTION__, buf->idx, buf->used );
y2 = length / 64;
BEGIN_DMA( 5 );
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_DWGSYNC, 0x00007100,
MGA_DWGSYNC, 0x00007000 );
DMA_BLOCK( MGA_DSTORG, dstorg,
MGA_MACCESS, 0x00000000,
MGA_SRCORG, srcorg,
MGA_AR5, 64 );
DMA_BLOCK( MGA_PITCH, 64,
MGA_PLNWT, 0xffffffff,
MGA_DMAPAD, 0x00000000,
MGA_DWGCTL, MGA_DWGCTL_COPY );
DMA_BLOCK( MGA_AR0, 63,
MGA_AR3, 0,
MGA_FXBNDRY, (63 << 16) | 0,
MGA_YDSTLEN + MGA_EXEC, y2 );
DMA_BLOCK( MGA_PLNWT, ctx->plnwt,
MGA_SRCORG, dev_priv->front_offset,
MGA_PITCH, dev_priv->front_pitch,
MGA_DWGSYNC, 0x00007000 );
ADVANCE_DMA();
AGE_BUFFER( buf_priv );
buf->pending = 0;
buf->used = 0;
buf_priv->dispatched = 0;
mga_freelist_put( dev, buf );
FLUSH_DMA();
}
static int mga_set_fence(DRM_IOCTL_ARGS)
{
DRM_DEVICE;
drm_mga_private_t *dev_priv = dev->dev_private;
u32 temp;
DMA_LOCALS;
if (!dev_priv) {
DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
return DRM_ERR(EINVAL);
}
DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
/* I would normal do this assignment in the declaration of temp,
* but dev_priv may be NULL.
*/
temp = dev_priv->next_fence_to_post;
dev_priv->next_fence_to_post++;
BEGIN_DMA(1);
DMA_BLOCK(MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_SOFTRAP, 0x00000000);
ADVANCE_DMA();
if (DRM_COPY_TO_USER( (u32 __user *) data, & temp, sizeof(u32))) {
DRM_ERROR("copy_to_user\n");
return DRM_ERR(EFAULT);
}
return 0;
}
static int mga_set_fence(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_mga_private_t *dev_priv = dev->dev_private;
u32 *fence = data;
DMA_LOCALS;
if (!dev_priv) {
DRM_ERROR("called with no initialization\n");
return -EINVAL;
}
DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
/* I would normal do this assignment in the declaration of fence,
* but dev_priv may be NULL.
*/
*fence = dev_priv->next_fence_to_post;
dev_priv->next_fence_to_post++;
BEGIN_DMA(1);
DMA_BLOCK(MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000, MGA_SOFTRAP, 0x00000000);
ADVANCE_DMA();
return 0;
}
void mga_do_dma_flush( drm_mga_private_t *dev_priv )
{
drm_mga_primary_buffer_t *primary = &dev_priv->prim;
u32 head, tail;
u32 status = 0;
int i;
DMA_LOCALS;
DRM_DEBUG( "\n" );
/* We need to wait so that we can do an safe flush */
for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
if ( status == MGA_ENDPRDMASTS ) break;
udelay( 1 );
}
if ( primary->tail == primary->last_flush ) {
DRM_DEBUG( " bailing out...\n" );
return;
}
tail = primary->tail + dev_priv->primary->offset;
/* We need to pad the stream between flushes, as the card
* actually (partially?) reads the first of these commands.
* See page 4-16 in the G400 manual, middle of the page or so.
*/
BEGIN_DMA( 1 );
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000 );
ADVANCE_DMA();
primary->last_flush = primary->tail;
head = MGA_READ( MGA_PRIMADDRESS );
if ( head <= tail ) {
primary->space = primary->size - primary->tail;
} else {
primary->space = head - tail;
}
DRM_DEBUG( " head = 0x%06lx\n", head - dev_priv->primary->offset );
DRM_DEBUG( " tail = 0x%06lx\n", tail - dev_priv->primary->offset );
DRM_DEBUG( " space = 0x%06x\n", primary->space );
mga_flush_write_combine();
MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER );
DRM_DEBUG( "done.\n" );
}
static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv )
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
DMA_LOCALS;
/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
/* tex->texctl, tex->texctl2); */
BEGIN_DMA( 5 );
DMA_BLOCK( MGA_TEXCTL2, (tex->texctl2 |
MGA_MAP1_ENABLE |
MGA_G400_TC2_MAGIC),
MGA_TEXCTL, tex->texctl,
MGA_TEXFILTER, tex->texfilter,
MGA_TEXBORDERCOL, tex->texbordercol );
DMA_BLOCK( MGA_TEXORG, tex->texorg,
MGA_TEXORG1, tex->texorg1,
MGA_TEXORG2, tex->texorg2,
MGA_TEXORG3, tex->texorg3 );
DMA_BLOCK( MGA_TEXORG4, tex->texorg4,
MGA_TEXWIDTH, tex->texwidth,
MGA_TEXHEIGHT, tex->texheight,
MGA_WR49, 0x00000000 );
DMA_BLOCK( MGA_WR57, 0x00000000,
MGA_WR53, 0x00000000,
MGA_WR61, 0x00000000,
MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC );
DMA_BLOCK( MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC,
MGA_TEXTRANS, 0x0000ffff,
MGA_TEXTRANSHIGH, 0x0000ffff,
MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC );
ADVANCE_DMA();
}
static __inline__ void mga_g400_emit_pipe(drm_mga_private_t *dev_priv)
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
unsigned int pipe = sarea_priv->warp_pipe;
DMA_LOCALS;
/* printk("mga_g400_emit_pipe %x\n", pipe); */
BEGIN_DMA(10);
DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
if (pipe & MGA_T2) {
DMA_BLOCK(MGA_WVRTXSZ, 0x00001e09,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
MGA_WACCEPTSEQ, 0x00000000,
MGA_WACCEPTSEQ, 0x00000
static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
{
drm_mga_private_t *dev_priv = dev->dev_private;
drm_mga_buf_priv_t *buf_priv = buf->dev_private;
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
u32 address = (u32) buf->bus_address;
u32 length = (u32) buf->used;
int i = 0;
DMA_LOCALS;
DRM_DEBUG( "vertex: buf=%d used=%d\n", buf->idx, buf->used );
if ( buf->used ) {
buf_priv->dispatched = 1;
MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
do {
if ( i < sarea_priv->nbox ) {
mga_emit_clip_rect( dev_priv,
&sarea_priv->boxes[i] );
}
BEGIN_DMA( 1 );
DMA_BLOCK(MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_SECADDRESS, (address |
MGA_DMA_VERTEX),
MGA_SECEND, ((address + length) |
dev_priv->dma_access));
ADVANCE_DMA();
} while ( ++i < sarea_priv->nbox );
}
if ( buf_priv->discard ) {
AGE_BUFFER( buf_priv );
buf->pending = 0;
buf->used = 0;
buf_priv->dispatched = 0;
mga_freelist_put( dev, buf );
}
FLUSH_DMA();
}
static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf,
unsigned int start, unsigned int end )
{
drm_mga_private_t *dev_priv = dev->dev_private;
drm_mga_buf_priv_t *buf_priv = buf->dev_private;
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
u32 address = (u32) buf->bus_address;
int i = 0;
DMA_LOCALS;
DRM_DEBUG( "indices: buf=%d start=%d end=%d\n", buf->idx, start, end );
if ( start != end ) {
buf_priv->dispatched = 1;
MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
do {
if ( i < sarea_priv->nbox ) {
mga_emit_clip_rect( dev_priv,
&sarea_priv->boxes[i] );
}
BEGIN_DMA( 1 );
DMA_BLOCK(MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_SETUPADDRESS, address + start,
MGA_SETUPEND, ((address + end) |
dev_priv->dma_access));
ADVANCE_DMA();
} while ( ++i < sarea_priv->nbox );
}
if ( buf_priv->discard ) {
AGE_BUFFER( buf_priv );
buf->pending = 0;
buf->used = 0;
buf_priv->dispatched = 0;
mga_freelist_put( dev, buf );
}
FLUSH_DMA();
}
void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv )
{
drm_mga_primary_buffer_t *primary = &dev_priv->prim;
u32 head, tail;
DMA_LOCALS;
DRM_DEBUG( "\n" );
BEGIN_DMA_WRAP();
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000 );
ADVANCE_DMA();
tail = primary->tail + dev_priv->primary->offset;
primary->tail = 0;
primary->last_flush = 0;
primary->last_wrap++;
head = MGA_READ( MGA_PRIMADDRESS );
if ( head == dev_priv->primary->offset ) {
primary->space = primary->size;
} else {
primary->space = head - dev_priv->primary->offset;
}
DRM_DEBUG( " head = 0x%06lx\n",
head - dev_priv->primary->offset );
DRM_DEBUG( " tail = 0x%06x\n", primary->tail );
DRM_DEBUG( " wrap = %d\n", primary->last_wrap );
DRM_DEBUG( " space = 0x%06x\n", primary->space );
mga_flush_write_combine();
MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER );
set_bit( 0, &primary->wrapped );
DRM_DEBUG( "done.\n" );
}
static inline void mga_g400_emit_tex0( drm_mga_private_t *dev_priv )
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
DMA_LOCALS;
BEGIN_DMA( 6 );
DMA_BLOCK( MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
MGA_TEXCTL, tex->texctl,
MGA_TEXFILTER, tex->texfilter,
MGA_TEXBORDERCOL, tex->texbordercol );
DMA_BLOCK( MGA_TEXORG, tex->texorg,
MGA_TEXORG1, tex->texorg1,
MGA_TEXORG2, tex->texorg2,
MGA_TEXORG3, tex->texorg3 );
DMA_BLOCK( MGA_TEXORG4, tex->texorg4,
MGA_TEXWIDTH, tex->texwidth,
MGA_TEXHEIGHT, tex->texheight,
MGA_WR49, 0x00000000 );
DMA_BLOCK( MGA_WR57, 0x00000000,
MGA_WR53, 0x00000000,
MGA_WR61, 0x00000000,
MGA_WR52, MGA_G400_WR_MAGIC );
DMA_BLOCK( MGA_WR60, MGA_G400_WR_MAGIC,
MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC,
MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC,
MGA_DMAPAD, 0x00000000 );
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_TEXTRANS, 0x0000ffff,
MGA_TEXTRANSHIGH, 0x0000ffff );
ADVANCE_DMA();
}
static __inline__ void mga_g400_emit_pipe(drm_mga_private_t *dev_priv)
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
unsigned int pipe = sarea_priv->warp_pipe;
DMA_LOCALS;
BEGIN_DMA(10);
DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
if (pipe & MGA_T2) {
DMA_BLOCK(MGA_WVRTXSZ, 0x00001e09,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
MGA_WACCEPTSEQ, 0x00000000,
MGA_WACCEPTSEQ, 0x00000000,
MGA_WACCEPTSEQ, 0x1e000000);
} else {
if (dev_priv->warp_pipe & MGA_T2) {
DMA_BLOCK(MGA_YDST, 0x00000000,
MGA_FXLEFT, 0x00000000,
MGA_FXRIGHT, 0x00000001,
MGA_DWGCTL, MGA_DWGCTL_FLUSH);
DMA_BLOCK(MGA_LEN + MGA_EXEC, 0x00000001,
MGA_DWGSYNC, 0x00007000,
MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
MGA_LEN + MGA_EXEC, 0x00000000);
DMA_BLOCK(MGA_TEXCTL2, (MGA_DUALTEX |
MGA_G400_TC2_MAGIC),
MGA_LEN + MGA_EXEC, 0x00000000,
MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
MGA_DMAPAD, 0x00000000);
}
DMA_BLOCK(MGA_WVRTXSZ, 0x00001807,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
MGA_WACCEPTSEQ, 0x00000000,
MGA_WACCEPTSEQ, 0x00000000,
MGA_WACCEPTSEQ, 0x18000000);
}
DMA_BLOCK(MGA_WFLAG, 0x00000000,
MGA_WFLAG1, 0x00000000,
MGA_WR56, MGA_G400_WR56_MAGIC, MGA_DMAPAD, 0x00000000);
DMA_BLOCK(MGA_WR49, 0x00000000,
MGA_WR57, 0x00000000,
MGA_WR53, 0x00000000,
MGA_WR61, 0x00000000);
DMA_BLOCK(MGA_WR54, MGA_G400_WR_MAGIC,
MGA_WR62, MGA_G400_WR_MAGIC,
MGA_WR52, MGA_G400_WR_MAGIC,
MGA_WR60, MGA_G400_WR_MAGIC);
DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
MGA_DMAPAD, 0xffffffff,
MGA_DMAPAD, 0xffffffff,
MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] |
MGA_WMODE_START | dev_priv->wagp_enable));
ADVANCE_DMA();
}
static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv )
{
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
unsigned int pipe = sarea_priv->warp_pipe;
DMA_LOCALS;
/* printk("mga_g400_emit_pipe %x\n", pipe); */
BEGIN_DMA( 10 );
DMA_BLOCK( MGA_WIADDR2, MGA_WMODE_SUSPEND,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000 );
if ( pipe & MGA_T2 ) {
DMA_BLOCK( MGA_WVRTXSZ, 0x00001e09,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000 );
DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000,
MGA_WACCEPTSEQ, 0x00000000,
MGA_WACCEPTSEQ, 0x00000000,
MGA_WACCEPTSEQ, 0x1e000000 );
} else {
if ( dev_priv->warp_pipe & MGA_T2 ) {
/* Flush the WARP pipe */
DMA_BLOCK( MGA_YDST, 0x00000000,
MGA_FXLEFT, 0x00000000,
MGA_FXRIGHT, 0x00000001,
MGA_DWGCTL, MGA_DWGCTL_FLUSH );
DMA_BLOCK( MGA_LEN + MGA_EXEC, 0x00000001,
MGA_DWGSYNC, 0x00007000,
MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
MGA_LEN + MGA_EXEC, 0x00000000 );
DMA_BLOCK( MGA_TEXCTL2, (MGA_DUALTEX |
MGA_G400_TC2_MAGIC),
MGA_LEN + MGA_EXEC, 0x00000000,
MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
MGA_DMAPAD, 0x00000000 );
}
DMA_BLOCK( MGA_WVRTXSZ, 0x00001807,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000 );
DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000,
MGA_WACCEPTSEQ, 0x00000000,
MGA_WACCEPTSEQ, 0x00000000,
MGA_WACCEPTSEQ, 0x18000000 );
}
DMA_BLOCK( MGA_WFLAG, 0x00000000,
MGA_WFLAG1, 0x00000000,
MGA_WR56, MGA_G400_WR56_MAGIC,
MGA_DMAPAD, 0x00000000 );
DMA_BLOCK( MGA_WR49, 0x00000000, /* tex0 */
MGA_WR57, 0x00000000, /* tex0 */
MGA_WR53, 0x00000000, /* tex1 */
MGA_WR61, 0x00000000 ); /* tex1 */
DMA_BLOCK( MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */
MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */
MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */
MGA_WR60, MGA_G400_WR_MAGIC ); /* tex1 height */
/* Padding required to to hardware bug */
DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
MGA_DMAPAD, 0xffffffff,
MGA_DMAPAD, 0xffffffff,
MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] |
MGA_WMODE_START | dev_priv->wagp_enable));
ADVANCE_DMA();
}
static void mga_dma_dispatch_clear( drm_device_t *dev,
drm_mga_clear_t *clear )
{
drm_mga_private_t *dev_priv = dev->dev_private;
drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
drm_clip_rect_t *pbox = sarea_priv->boxes;
int nbox = sarea_priv->nbox;
int i;
DMA_LOCALS;
DRM_DEBUG( "\n" );
BEGIN_DMA( 1 );
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_DWGSYNC, 0x00007100,
MGA_DWGSYNC, 0x00007000 );
ADVANCE_DMA();
for ( i = 0 ; i < nbox ; i++ ) {
drm_clip_rect_t *box = &pbox[i];
u32 height = box->y2 - box->y1;
DRM_DEBUG( " from=%d,%d to=%d,%d\n",
box->x1, box->y1, box->x2, box->y2 );
if ( clear->flags & MGA_FRONT ) {
BEGIN_DMA( 2 );
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
MGA_PLNWT, clear->color_mask,
MGA_YDSTLEN, (box->y1 << 16) | height,
MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
MGA_FCOL, clear->clear_color,
MGA_DSTORG, dev_priv->front_offset,
MGA_DWGCTL + MGA_EXEC,
dev_priv->clear_cmd );
ADVANCE_DMA();
}
if ( clear->flags & MGA_BACK ) {
BEGIN_DMA( 2 );
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
MGA_PLNWT, clear->color_mask,
MGA_YDSTLEN, (box->y1 << 16) | height,
MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
MGA_FCOL, clear->clear_color,
MGA_DSTORG, dev_priv->back_offset,
MGA_DWGCTL + MGA_EXEC,
dev_priv->clear_cmd );
ADVANCE_DMA();
}
if ( clear->flags & MGA_DEPTH ) {
BEGIN_DMA( 2 );
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
MGA_PLNWT, clear->depth_mask,
MGA_YDSTLEN, (box->y1 << 16) | height,
MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
MGA_FCOL, clear->clear_depth,
MGA_DSTORG, dev_priv->depth_offset,
MGA_DWGCTL + MGA_EXEC,
dev_priv->clear_cmd );
ADVANCE_DMA();
}
}
BEGIN_DMA( 1 );
/* Force reset of DWGCTL */
DMA_BLOCK( MGA_DMAPAD, 0x00000000,
MGA_DMAPAD, 0x00000000,
MGA_PLNWT, ctx->plnwt,
MGA_DWGCTL, ctx->dwgctl );
ADVANCE_DMA();
FLUSH_DMA();
}
