/* INPUT */ input.MK0 = (kal_int16) input_mk; /* LSB */ input.MK1 = (kal_int16)(input_mk >> 16); /* MSB */ input.DIRECTION = direction; /*decipher=1;cipher=0*/ key_ptr = (kal_uint8 *)&key; DRVPDN_Disable(DRVPDN_CON0,DRVPDN_CON0_GCU,PDN_GCU); GCU_InputData(&input); if(cipher_algo == 1) /*A5_1 == 1*/ GCU_GEA1Start(); /* for uplink link. According to spec. 04.64 */ else if(cipher_algo == 2) GCU_GEA2Start(); /* for uplink link. According to spec. 04.64 */ #if defined(DRV_GCU_GEA3) else if(cipher_algo == 3) GCU_GEA3Start(); #endif else ASSERT(0); for(index1=0;index1 < ((buff_len+3)/4);index1++) { GCU_ReadKey(key); for(index2=0;index2 < 4;index2++) { if((index1*4+index2) == buff_len) break; #if defined(DRV_GCU_GEA3) // Julie : GEA3 RBO reverse with bithe GEA1 and GEA2 if(cipher_algo == 3) dest_buff_ptr[(index1*4+index2)] = src_buff_ptr[(index1*4+index2)] ^ key_ptr[3-index2]; else dest_buff_ptr[(index1*4+index2)] = src_buff_ptr[(index1*4+index2)] ^ key_ptr[index2]; #else dest_buff_ptr[(index1*4+index2)] = src_buff_ptr[(index1*4+index2)] ^ key_ptr[index2]; #endif } } DRVPDN_Enable(DRVPDN_CON0,DRVPDN_CON0_GCU,PDN_GCU); return KAL_TRUE; } #ifdef DRV_GCU_REV_BIT_DISABLE/*only 6218B has this, Others projects dont have*/ void GCU_Disable_ReverseBit(void) { DRVPDN_Disable(DRVPDN_CON0,DRVPDN_CON0_GCU,PDN_GCU); // clear GCU reverse bit DRV_Reg(GCU_CTRL) &= ~GCU_CTRL_RBO; DRVPDN_Enable(DRVPDN_CON0,DRVPDN_CON0_GCU,PDN_GCU); }
void adc_pwrdown_enable(void) { #ifndef DRV_ADC_NOT_EXIST #ifndef DRV_ADC_NO_PDN #if (!defined(DRV_ADC_6208_PWRDOWN)) && (!defined(DRV_ADC_MODEM_SIDE)) if((adc_sche_rw_status==0)&&!(DRV_ADC_Reg(AUXADC_CON) & AUXADC_CON_RUN)) #endif // #if (!defined(DRV_ADC_6208_PWRDOWN)) && (!defined(DRV_ADC_MODEM_SIDE)) { #if defined(__OLD_PDN_ARCH__) #ifdef ADC_DRVPDN_FAST DRVPDN_ENABLE2(ADC_CG_PDN_CON_ADDR,ADC_CG_PDN_CON_BIT,PDN_ADC); #else /*ADC_DRVPDN_FAST*/ DRVPDN_Enable(ADC_CG_PDN_CON_ADDR,ADC_CG_PDN_CON_BIT,PDN_ADC); #endif /*ADC_DRVPDN_FAST*/ #else // #if defined(__OLD_PDN_ARCH__) #ifdef ADC_DRVPDN_FAST DRVPDN_ENABLE2(PDN_ADC); #else /*ADC_DRVPDN_FAST*/ //DRVPDN_Enable(PDN_ADC); PDN_SET(PDN_ADC); L1SM_SleepEnable(ADCSM_handler); #endif /*ADC_DRVPDN_FAST*/ #endif // #if defined(__OLD_PDN_ARCH__) } #endif //#ifndef DRV_ADC_NO_PDN #endif // #ifndef DRV_ADC_NOT_EXIST }
/* * FUNCTION * IMGPROC_Close * * DESCRIPTION * Release the ownership of IMGPORC * * CALLS * * PARAMETERS * * RETURNS * None * * GLOBALS AFFECTED * imgproc_dcb.owner */ kal_int32 API IMGPROC_Close(MMDI_SCENERIO_ID owner) { #if (defined(DRV_IDP_6219_SERIES)) ASSERT(imgproc_dcb.owner == owner); IMGPROC_Stop(owner); IMGPROC_RESET(); IMGPROC_DISABLE_INT(); kal_mem_set(&imgproc_dcb,0,sizeof(IMGPROC_DCB_STRUCT)); DRVPDN_Enable(DRVPDN_CON3,DRVPDN_CON3_IMGPROC,PDN_IMGPROC); #endif return NO_ERROR; }
/* * FUNCTION * GPT_Stop * * DESCRIPTION * Stop GPT timer * * CALLS * It is called to stop GPT timer * * PARAMETERS * timerNum = 1(GPT1) or 2(GPT2) * * RETURNS * None * * GLOBALS AFFECTED * external_global */ void GPT_Stop(kal_uint8 timerNum) { kal_uint16 gpt_ctrl1; kal_uint16 gpt_ctrl2; #if defined(DRV_GPT_GPT3) kal_uint16 gpt_ctrl3; #endif gpt_ctrl1 = DRV_Reg(GPT1_CTRL); gpt_ctrl2 = DRV_Reg(GPT2_CTRL); #if defined(DRV_GPT_GPT3) gpt_ctrl3 = DRV_Reg(GPT3_CTRL); #endif if (timerNum == 1) { gpt_ctrl1 &= ~GPT_CTRL_Enable; DRV_WriteReg(GPT1_CTRL,gpt_ctrl1); } if (timerNum == 2) { gpt_ctrl2 &= ~GPT_CTRL_Enable; DRV_WriteReg(GPT2_CTRL,gpt_ctrl2); } #if defined(DRV_GPT_GPT3) if (timerNum == 3) { gpt_ctrl3 =(kal_uint16) ~GPT3_ENABLE; DRV_WriteReg(GPT3_CTRL,gpt_ctrl3); } if ( (((gpt_ctrl1|gpt_ctrl2)&GPT_CTRL_Enable)==0)&& (!(gpt_ctrl3&GPT3_ENABLE))) #else if ( ((gpt_ctrl1|gpt_ctrl2)&GPT_CTRL_Enable)==0 ) #endif { kal_uint16 GPT_Status; GPT_Status = DRV_Reg(GPT_STS); IRQMask(IRQ_GPT_CODE); IRQClearInt(IRQ_GPT_CODE); #ifdef GPT_DRVPDN_FAST DRVPDN_ENABLE2(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT); #else DRVPDN_Enable(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT); #endif } }
/************************************************************************* * FUNCTION * GIF_Reset * * DESCRIPTION * reset the gif decoder and control block * * PARAMETERS * * RETURNS * * GLOBALS AFFECTED * gif_dcb *************************************************************************/ void GIF_Reset(void) { DRVPDN_Disable(DRVPDN_CON3,DRVPDN_CON3_GIF,PDN_GIF); GIF_RESET(); DRV_WriteReg32(GIF_STACK_BASE_ADDR, gif_resource.stack); DRV_WriteReg32(GIF_TREE_BASE_ADDR, gif_resource.tree); DRV_WriteReg32(GIF_GCT_BASE_ADDR, gif_resource.GCT); DRV_WriteReg32(GIF_LCT_BASE_ADDR, gif_resource.LCT); DRVPDN_Enable(DRVPDN_CON3,DRVPDN_CON3_GIF,PDN_GIF); gif_dcb.out_location = GIF_MEMORY; //gif_dcb.timeout_period = GIF_TIMEOUT_PERIOD; gif_dcb.is_timeout = KAL_FALSE; gif_dcb.frame_counter = 0; gif_dcb.trailer = KAL_FALSE; if(gif_dcb.gpt_handle == 0) GPTI_GetHandle(&gif_dcb.gpt_handle); kal_mem_set(&gif_dcb.gif_info,0,sizeof(gif_info_struct)); }
void adc_pwrdown_enable(void) { #ifndef DRV_ADC_NOT_EXIST { #if defined(DRV_DIE_TO_DIE_INTERFACE) { kal_uint32 mask; mask = SaveAndSetIRQMask(); auxadc_die2die_enable = KAL_FALSE; DRV_ADC_ClearBits(ABB_AUX_CON0, AUX_FIFO_EN); // auxadc fifo enable DRV_ADC_ClearBits(ABB_AUX_CON0, AUX_FIFO_CLK_EN); // auxadc fifo enable ust_busy_wait(8); DRV_ADC_ClearBits(ABB_WR_PATH0, AUX_PWDB); //triggle die to die interface to send and receive auxadc data DRV_ADC_ClearBits(ABBA_WR_PATH0, ABBA_AUX_PWDB); // enable clock for auxadc analog interface logic // DRV_ADC_ClearBits(ABB_WR_PATH0, F26M_CLK_EN); //enable clock for die to die interface // DRV_ADC_ClearBits(ABB_RSV_CON1, AUXADC_FSM_CTRL|AUXADC_26M_CLK_CTRL); //enable clock for die to die interface DRV_ADC_ClearBits(ABB_RSV_CON1, AUXADC_FSM_CTRL); //enable clock for die to die interface ust_busy_wait(2); DRV_ADC_ClearBits(ABB_RSV_CON1, AUXADC_26M_CLK_CTRL); //enable clock for die to die interface PDN_SET(PDN_ADC); // TP use the AuxADC PDN, make sure the PDN is enable DRV_ADC_ClearBits(0xa0160020,0x8000); RestoreIRQMask(mask); } #elif defined(DRV_DIE_TO_DIE_INTERFACE_V2) { DRV_ADC_ClearBits(D2D_D_APC_AUX_CON1, D2D_D_AUX_EN); DRV_ADC_ClearBits(D2D_A_APC_AUD_CON1, D2D_A_AUX_EN); ust_busy_wait(8); DRV_ADC_ClearBits(D2D_D_APC_AUX_CON1, D2D_D_AUX_EN | D2D_D_F26M_AUX_EN); } #endif #if defined(__OLD_PDN_ARCH__) #ifdef ADC_DRVPDN_FAST DRVPDN_ENABLE2(ADC_CG_PDN_CON_ADDR,ADC_CG_PDN_CON_BIT,PDN_ADC); #else /*ADC_DRVPDN_FAST*/ DRVPDN_Enable(ADC_CG_PDN_CON_ADDR,ADC_CG_PDN_CON_BIT,PDN_ADC); #endif /*ADC_DRVPDN_FAST*/ #else // #if defined(__OLD_PDN_ARCH__) #ifdef ADC_DRVPDN_FAST DRVPDN_ENABLE2(PDN_ADC); #else /*ADC_DRVPDN_FAST*/ #if !defined(__DRV_SUPPORT_LPWR__) PDN_SET(PDN_ADC); L1SM_SleepEnable(ADCSM_handler); #else DRVPDN_Enable(PDN_ADC); #endif //#if !defined(__DRV_SUPPORT_LPWR__) #endif /*ADC_DRVPDN_FAST*/ #endif // #if defined(__OLD_PDN_ARCH__) } #endif // #ifndef DRV_ADC_NOT_EXIST }
/*-----------------------------------------------------------------------* * * This function is to close GPT source clock. * *------------------------------------------------------------------------*/ static void GPT_PDN_disable() { #if !defined(DRV_GPT_NO_PDN_BIT) #if defined(__OLD_PDN_ARCH__) #if defined(DRV_GPT_GPT_INTR_WAKEUP_SLEEP) // Set GPT PDN bit directly #if defined(DRV_MISC_PDN_NO_SET_CLR) #if defined(__OLD_PDN_DEFINE__) DRV_GPT_SetBits(DRVPDN_CON1, DRVPDN_CON1_GPT); //DRV_GPT_Reg(DRVPDN_CON1) |= DRVPDN_CON1_GPT; #elif defined(__CLKG_DEFINE__) #if defined(DRV_GPT_NO_GPT_CG_BIT) ; #else // #if defined(DRV_GPT_NO_GPT_CG_BIT) ASSERT(0); #endif // #if defined(DRV_GPT_NO_GPT_CG_BIT) #endif // #if defined(__OLD_PDN_DEFINE__) #else // #if defined(DRV_MISC_PDN_NO_SET_CLR) #if defined(__OLD_PDN_DEFINE__) DRV_GPT_WriteReg(DRVPDN_CON1_SET, DRVPDN_CON1_GPT); #elif defined(__CLKG_DEFINE__) #if defined(DRV_GPT_NO_GPT_CG_BIT) ; #else // #if defined(DRV_GPT_NO_GPT_CG_BIT) ASSERT(0); #endif // #if defined(DRV_GPT_NO_GPT_CG_BIT) #endif // #if defined(__OLD_PDN_DEFINE__) #endif // #if defined(DRV_MISC_PDN_NO_SET_CLR) #else // #if defined(DRV_GPT_GPT_INTR_WAKEUP_SLEEP) // We need to to un-hook sleep mode handler to allow MCU enter sleep mode #if defined(__OLD_PDN_DEFINE__) #if defined(DRV_GPT_DIRECT_SLEEP_MODE_HANDLE) // Set GPT PDN bit directly #if defined(DRV_MISC_PDN_NO_SET_CLR) DRV_GPT_SetBits(DRVPDN_CON1, DRVPDN_CON1_GPT); //DRV_GPT_Reg(DRVPDN_CON1) |= DRVPDN_CON1_GPT; #else // #if defined(DRV_MISC_PDN_NO_SET_CLR) DRV_GPT_WriteReg(DRVPDN_CON1_SET, DRVPDN_CON1_GPT); #endif // #if defined(DRV_MISC_PDN_NO_SET_CLR) #else // #if defined(DRV_GPT_DIRECT_SLEEP_MODE_HANDLE) #ifdef GPT_DRVPDN_FAST DRVPDN_ENABLE2(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT); #else DRVPDN_Enable(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT); #endif #endif #elif defined(__CLKG_DEFINE__) #if defined(DRV_GPT_NO_GPT_CG_BIT) #ifdef GPT_DRVPDN_FAST // DRVPDN_ENABLE2(0,0,PDN_GPT); // TTTTTTTT, Temp commented for MT6268A DVT load #else // #ifdef GPT_DRVPDN_FAST DRVPDN_Enable(0,0,PDN_GPT); #endif // #ifdef GPT_DRVPDN_FAST #else // #if defined(DRV_GPT_NO_GPT_CG_BIT) ASSERT(0); #endif // #if defined(DRV_GPT_NO_GPT_CG_BIT) #endif // #if defined(__OLD_PDN_DEFINE__) #endif // #if defined(DRV_GPT_GPT_INTR_WAKEUP_SLEEP) #else //#if defined(__OLD_PDN_ARCH__) PDN_SET(PDN_GPT); #endif //#if defined(__OLD_PDN_ARCH__) #endif //#if !defined(DRV_GPT_NO_PDN_BIT) }
kal_bool gea_cidecipher (kal_uint8 *src_buff_ptr, kal_uint8 *dest_buff_ptr, kal_uint16 buff_len, kal_uint8 cipher_algo, kal_bool direction, kal_uint8 *input_sk, kal_uint32 input_mk) { kal_uint16 index1; kal_uint16 index2; kal_uint32 key; kal_uint8 *key_ptr; gcu_input input; input.SK3 = input_sk[1] | (input_sk[0] << 8); input.SK2 = input_sk[3] | (input_sk[2] << 8); input.SK1 = input_sk[5] | (input_sk[4] << 8); input.SK0 = input_sk[7] | (input_sk[6] << 8); /* INPUT */ input.MK0 = (kal_int16) input_mk; /* LSB */ input.MK1 = (kal_int16)(input_mk >> 16); /* MSB */ input.DIRECTION = direction; /*decipher=1;cipher=0*/ key_ptr = (kal_uint8 *)&key; DRVPDN_Disable(DRVPDN_CON0,DRVPDN_CON0_GCU,PDN_GCU); GCU_InputData(&input); if(cipher_algo == 1) /*A5_1 == 1*/ GCU_GEA1Start(); /* for uplink link. According to spec. 04.64 */ else if(cipher_algo == 2) GCU_GEA2Start(); /* for uplink link. According to spec. 04.64 */ #if defined(DRV_GCU_GEA3) else if(cipher_algo == 3) GCU_GEA3Start(); #endif else ASSERT(0); for(index1=0;index1 < ((buff_len+3)/4);index1++) { GCU_ReadKey(key); for(index2=0;index2 < 4;index2++) { if((index1*4+index2) == buff_len) break; #if defined(DRV_GCU_GEA3) // Julie : GEA3 RBO reverse with bithe GEA1 and GEA2 if(cipher_algo == 3) dest_buff_ptr[(index1*4+index2)] = src_buff_ptr[(index1*4+index2)] ^ key_ptr[3-index2]; else dest_buff_ptr[(index1*4+index2)] = src_buff_ptr[(index1*4+index2)] ^ key_ptr[index2]; #else dest_buff_ptr[(index1*4+index2)] = src_buff_ptr[(index1*4+index2)] ^ key_ptr[index2]; #endif } } DRVPDN_Enable(DRVPDN_CON0,DRVPDN_CON0_GCU,PDN_GCU); return KAL_TRUE; }