/* * this function set PLL P, M and S value in D-PHY */ void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim, unsigned int value) { struct exynos_mipi_dsim *mipi_dsim = (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); writel(DSIM_AFC_CTL(value), &mipi_dsim->phyacchr); }
void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, unsigned int enable, unsigned int afc_code) { struct exynos_mipi_dsim *mipi_dsim = (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); unsigned int reg = readl(&mipi_dsim->phyacchr); reg = 0; if (enable) { reg |= DSIM_AFC_EN; reg &= ~(0x7 << DSIM_AFC_CTL_SHIFT); reg |= DSIM_AFC_CTL(afc_code); } else reg &= ~DSIM_AFC_EN; writel(reg, &mipi_dsim->phyacchr); }
/* * this function set PLL P, M and S value in D-PHY */ void s5p_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim, unsigned int value) { writel(DSIM_AFC_CTL(value), dsim->reg_base + S5P_DSIM_PHYACCHR); }
/* * this function set PLL P, M and S value in D-PHY */ void s5p_dsim_set_phy_tunning(unsigned int dsim_base, unsigned int value) { writel(DSIM_AFC_CTL(value), dsim_base + S5P_DSIM_PHYACCHR); dprintk("%s : %x\n", __func__, DSIM_AFC_CTL(value)); }
/* * this function set PLL P, M and S value in D-PHY */ void s5p_dsim_set_phy_tunning(unsigned int dsim_base, unsigned int value) { writel(DSIM_AFC_CTL(value), dsim_base + S5P_DSIM_PHYACCHR); }