C++ (Cpp) DSIM_M_PLLCTRL_SET3 Exemples

Exemple #1

Fichier : dsim_reg_5430.c Projet : bju2000/android_kernel_samsung_slteskt

void dsim_reg_set_dphy_timing_values(struct dphy_timing_value *t)
{
	u32 val, mask;

	val = DSIM_PHYTIMING_M_TLPXCTL(t->lpx) |
		DSIM_PHYTIMING_M_THSEXITCTL(t->hs_exit);
	dsim_write(DSIM_PHYTIMING, val);

	val = DSIM_PHYTIMING1_M_TCLKPRPRCTL(t->clk_prepare) |
		DSIM_PHYTIMING1_M_TCLKZEROCTL(t->clk_zero) |
		DSIM_PHYTIMING1_M_TCLKPOSTCTL(t->clk_post) |
		DSIM_PHYTIMING1_M_TCLKTRAILCTL(t->clk_trail);
	dsim_write(DSIM_PHYTIMING1, val);

	val = DSIM_PHYTIMING2_M_THSPRPRCTL(t->hs_prepare) |
		DSIM_PHYTIMING2_M_THSZEROCTL(t->hs_zero) |
		DSIM_PHYTIMING2_M_THSTRAILCTL(t->hs_trail);
	dsim_write(DSIM_PHYTIMING2, val);

	val = DSIM_PHYCTRL_B_DPHYCTL(t->b_dphyctl) |
		DSIM_PHYCTRL_B_DPHYCTL_VREG_LP;
	mask = DSIM_PHYCTRL_B_DPHYCTL_MASK | DSIM_PHYCTRL_B_DPHYCTL_VREG_LP;
#if defined(CONFIG_DECON_LCD_EA8064G) && !defined(CONFIG_SEC_FACTORY)	/* Should be removed */
	val |= DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP;
	mask |= DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP;
#endif
	dsim_write_mask(DSIM_B_DPHYCTRL, val, mask);

	val = DSIM_PHYCTRL_M_DPHYCTL_VREG_HS;
	mask = DSIM_PHYCTRL_M_DPHYCTL_VREG_HS;
	dsim_write_mask(DSIM_M_DPHYCTRL, val, mask);

	val = DSIM_M_PLLCTRL_SET1(t->m_pllctl) |
		DSIM_M_PLLCTRL_SET3(DSIM_M_PLLCTRL_VALUE3) |
		DSIM_M_PLLCTRL_SET2;
	mask = DSIM_M_PLLCTRL_SET1_MASK |
		DSIM_M_PLLCTRL_SET3_MASK |
		DSIM_M_PLLCTRL_SET2;
	dsim_write_mask(DSIM_M_PLLCTRL, val, mask);
}

Exemple #2

Fichier : dsim_reg_5430.c Projet : BigBot96/android_kernel_samsung_gts2wifi

void dsim_reg_set_dphy_timing_values(struct dphy_timing_value *t)
{
	u32 val, mask;

	val = DSIM_PHYTIMING_M_TLPXCTL(t->lpx) |
		DSIM_PHYTIMING_M_THSEXITCTL(t->hs_exit);
	dsim_write(DSIM_PHYTIMING, val);

	val = DSIM_PHYTIMING1_M_TCLKPRPRCTL(t->clk_prepare) |
		DSIM_PHYTIMING1_M_TCLKZEROCTL(t->clk_zero) |
		DSIM_PHYTIMING1_M_TCLKPOSTCTL(t->clk_post) |
		DSIM_PHYTIMING1_M_TCLKTRAILCTL(t->clk_trail);
	dsim_write(DSIM_PHYTIMING1, val);

	val = DSIM_PHYTIMING2_M_THSPRPRCTL(t->hs_prepare) |
		DSIM_PHYTIMING2_M_THSZEROCTL(t->hs_zero) |
		DSIM_PHYTIMING2_M_THSTRAILCTL(t->hs_trail);
	dsim_write(DSIM_PHYTIMING2, val);

	val = DSIM_PHYCTRL_B_DPHYCTL(t->b_dphyctl) |
		DSIM_PHYCTRL_B_DPHYCTL_VREG_LP |
		DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP;
	mask = DSIM_PHYCTRL_B_DPHYCTL_MASK |
		DSIM_PHYCTRL_B_DPHYCTL_VREG_LP |
		DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP;
	dsim_write_mask(DSIM_B_DPHYCTRL, val, mask);

	val = DSIM_PHYCTRL_M_DPHYCTL_VREG_HS;
	mask = DSIM_PHYCTRL_M_DPHYCTL_VREG_HS;
	dsim_write_mask(DSIM_M_DPHYCTRL, val, mask);

	val = DSIM_M_PLLCTRL_SET1(t->m_pllctl) |
		DSIM_M_PLLCTRL_SET3(DSIM_M_PLLCTRL_VALUE3) |
		DSIM_M_PLLCTRL_SET2;
	mask = DSIM_M_PLLCTRL_SET1_MASK |
		DSIM_M_PLLCTRL_SET3_MASK |
		DSIM_M_PLLCTRL_SET2;
	dsim_write_mask(DSIM_M_PLLCTRL, val, mask);
}