{199, 199, 199},
                                {153, 153, 153},
                                {116, 116, 116},
                                {85, 85, 85},
                                {59, 59, 59},
                                {36, 36, 36},
                                {17, 17, 17},
                                {0, 0, 0},
                        },
                },
        .sd_brightness = &sd_brightness,
        .use_vpulse2 = true,
};

static struct tegra_dsi_cmd dsi_j_qxga_8_9_init_cmd[] = {
	DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_EXIT_SLEEP_MODE, 0x0, CMD_NOT_CLUBBED),
	DSI_DLY_MS(120),
	DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_1_PARAM, 0x53, 0x24, CMD_CLUBBED),
	DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_1_PARAM, 0x55, 0x00, CMD_CLUBBED),
	DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_1_PARAM, 0x35, 0x00, CMD_CLUBBED),
	DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_ON, 0x0, CMD_CLUBBED),
};

static struct tegra_dsi_cmd dsi_j_qxga_8_9_suspend_cmd[] = {
	DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_1_PARAM, 0x51, 0x00, CMD_CLUBBED),
	DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_OFF, 0x0, CMD_CLUBBED),
	DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_ENTER_SLEEP_MODE, 0x0, CMD_CLUBBED),
	DSI_SEND_FRAME(3),
	DSI_CMD_VBLANK_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xB0, 0x04, CMD_CLUBBED),
	DSI_CMD_VBLANK_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xB1, 0x01, CMD_CLUBBED),
};
	186, 187, 188, 189, 190, 191, 192, 194,
	195, 196, 197, 198, 199, 200, 201, 202,
	203, 204, 205, 206, 207, 208, 209, 210,
	211, 212, 213, 214, 215, 216, 217, 219,
	220, 221, 222, 224, 225, 226, 227, 229,
	230, 231, 232, 233, 234, 235, 236, 238,
	239, 240, 241, 242, 243, 244, 245, 246,
	247, 248, 249, 250, 251, 252, 253, 255
};

static u8 test_key[] = {0xF0, 0x5A, 0x5A};
static u8 enable_pwr[] = {0xC3, 0x40, 0x00, 0x28};
static struct tegra_dsi_cmd dsi_a_1200_800_8_0_init_cmd[] = {
	DSI_CMD_VBLANK_LONG(MIPI_DSI_DCS_LONG_WRITE, test_key),
	DSI_DLY_MS(5),
	DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_EXIT_SLEEP_MODE, 0x0),
	DSI_DLY_MS(5),
	DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_ON, 0x0),
	DSI_DLY_MS(10),
	DSI_CMD_VBLANK_LONG(MIPI_DSI_DCS_LONG_WRITE, enable_pwr),
	DSI_DLY_MS(170),
};


static struct tegra_dsi_out dsi_a_1200_800_8_0_pdata = {
	.controller_vs = DSI_VS_1,
	.n_data_lanes = 4,
	.video_burst_mode = TEGRA_DSI_VIDEO_NONE_BURST_MODE,

	.pixel_format = TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
	.refresh_rate = 60,