static DISP_STATUS dsi_init(UINT32 fbVA, UINT32 fbPA, BOOL isLcmInited)
{
if (!disp_drv_dsi_init_context())
return DISP_STATUS_NOT_IMPLEMENTED;
if(lcm_params->dsi.mode == CMD_MODE) {
#ifndef MT65XX_NEW_DISP
init_lcd();
#endif
init_dsi(isLcmInited);
if (NULL != lcm_drv->init && !isLcmInited)
{
lcm_drv->init();
DSI_LP_Reset();
}
#ifndef MT65XX_NEW_DISP
DSI_clk_HS_mode(0);
#else
DSI_clk_HS_mode(1);
#endif
DSI_SetMode(lcm_params->dsi.mode);
#ifndef MT65XX_NEW_DISP
DPI_PowerOn();
DPI_PowerOff();
init_lcd_te_control();
#endif
}
else {
#ifndef MT65XX_NEW_DISP
init_intermediate_buffers(fbPA);
init_lcd();
init_dpi(isLcmInited);
#endif
if (!isLcmInited)
{
DSI_SetMode(0);
mdelay(100);
DSI_DisableClk();
}
else
{
is_video_mode_running = true;
}
init_dsi(isLcmInited);
if (NULL != lcm_drv->init && !isLcmInited) {
lcm_drv->init();
DSI_LP_Reset();
}
DSI_SetMode(lcm_params->dsi.mode);
#ifndef BUILD_UBOOT
#ifndef MT65XX_NEW_DISP
if(lcm_params->dsi.lcm_ext_te_monitor)
{
is_video_mode_running = false;
LCD_TE_SetMode(LCD_TE_MODE_VSYNC_ONLY);
LCD_TE_SetEdgePolarity(LCM_POLARITY_RISING);
LCD_TE_Enable(FALSE);
}
if(lcm_params->dsi.noncont_clock)
DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period);
if(lcm_params->dsi.lcm_int_te_monitor)
DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period);
#endif
#endif
}
#ifdef MT65XX_NEW_DISP
{
struct disp_path_config_struct config = {0};
config.srcModule = DISP_MODULE_OVL;
config.bgROI.x = 0;
config.bgROI.y = 0;
config.bgROI.width = DISP_GetScreenWidth();
config.bgROI.height = DISP_GetScreenHeight();
config.bgColor = 0x0; // background color
config.pitch = DISP_GetScreenWidth()*2;
config.srcROI.x = 0;config.srcROI.y = 0;
config.srcROI.height= DISP_GetScreenHeight();config.srcROI.width= DISP_GetScreenWidth();
config.ovl_config.source = OVL_LAYER_SOURCE_MEM;
if(lcm_params->dsi.mode != CMD_MODE)
{
config.ovl_config.layer = FB_LAYER;
config.ovl_config.layer_en = 0;
disp_path_get_mutex();
disp_path_config_layer(&config.ovl_config);
disp_path_release_mutex();
disp_path_wait_reg_update();
}
// Config FB_Layer port to be physical.
{
M4U_PORT_STRUCT portStruct;
portStruct.ePortID = M4U_PORT_OVL_CH3; //hardware port ID, defined in M4U_PORT_ID_ENUM
portStruct.Virtuality = 1;
portStruct.Security = 0;
portStruct.domain = 3; //domain : 0 1 2 3
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
}
config.ovl_config.layer = FB_LAYER;
config.ovl_config.layer_en = 1;
config.ovl_config.fmt = OVL_INPUT_FORMAT_RGB565;
config.ovl_config.addr = fbPA;
config.ovl_config.source = OVL_LAYER_SOURCE_MEM;
config.ovl_config.src_x = 0;
config.ovl_config.src_y = 0;
config.ovl_config.dst_x = 0; // ROI
config.ovl_config.dst_y = 0;
config.ovl_config.dst_w = DISP_GetScreenWidth();
config.ovl_config.dst_h = DISP_GetScreenHeight();
config.ovl_config.src_pitch = ALIGN_TO(DISP_GetScreenWidth(),32)*2; //pixel number
config.ovl_config.keyEn = 0;
config.ovl_config.key = 0xFF; // color key
config.ovl_config.aen = 0; // alpha enable
config.ovl_config.alpha = 0;
LCD_LayerSetAddress(FB_LAYER, fbPA);
LCD_LayerSetFormat(FB_LAYER, LCD_LAYER_FORMAT_RGB565);
LCD_LayerSetOffset(FB_LAYER, 0, 0);
LCD_LayerSetSize(FB_LAYER,DISP_GetScreenWidth(),DISP_GetScreenHeight());
LCD_LayerSetPitch(FB_LAYER, ALIGN_TO(DISP_GetScreenWidth(),32) * 2);
LCD_LayerEnable(FB_LAYER, TRUE);
if(lcm_params->dsi.mode == CMD_MODE)
config.dstModule = DISP_MODULE_DSI_CMD;// DISP_MODULE_WDMA1
else
config.dstModule = DISP_MODULE_DSI_VDO;// DISP_MODULE_WDMA1
config.outFormat = RDMA_OUTPUT_FORMAT_ARGB;
if(lcm_params->dsi.mode != CMD_MODE)
disp_path_get_mutex();
disp_path_config(&config);
if(lcm_params->dsi.mode != CMD_MODE)
disp_path_release_mutex();
// Disable LK UI layer (Layer2)
if(lcm_params->dsi.mode != CMD_MODE)
{
config.ovl_config.layer = FB_LAYER-1;
config.ovl_config.layer_en = 0;
disp_path_get_mutex();
disp_path_config_layer(&config.ovl_config);
disp_path_release_mutex();
disp_path_wait_reg_update();
}
// Config LK UI layer port to be physical.
{
M4U_PORT_STRUCT portStruct;
portStruct.ePortID = M4U_PORT_OVL_CH2; //hardware port ID, defined in M4U_PORT_ID_ENUM
portStruct.Virtuality = 1;
portStruct.Security = 0;
portStruct.domain = 3; //domain : 0 1 2 3
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
}
}
#endif
return DISP_STATUS_OK;
}
// protected by sem_early_suspend, sem_update_screen
static DISP_STATUS dsi_enable_power(BOOL enable)
{
disp_drv_dsi_init_context();
if(lcm_params->dsi.mode == CMD_MODE) {
if (enable) {
#if 0
// Switch bus to MIPI TX.
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
DSI_PHY_clk_switch(TRUE, lcm_params);
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
DSI_CHECK_RET(DSI_PowerOn());
DSI_WaitForNotBusy();
DSI_clk_HS_mode(0);
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
DSI_Reset();
LCD_CHECK_RET(LCD_PowerOn());
#else
#ifndef MT65XX_NEW_DISP
DSI_PHY_clk_switch(TRUE, lcm_params);
DSI_CHECK_RET(DSI_PowerOn());
if(Need_Wait_ULPS())
Wait_ULPS_Mode();
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
#else
// enable MMSYS CG
DSI_CHECK_RET(DSI_PowerOn());
// initialize clock setting
DSI_PHY_clk_setting(lcm_params);
// initialize dsi timing
DSI_PHY_TIMCONFIG(lcm_params);
// restore dsi register
DSI_CHECK_RET(DSI_RestoreRegisters());
// enable sleep-out mode
DSI_CHECK_RET(DSI_SleepOut());
// enter HS mode
DSI_PHY_clk_switch(TRUE, lcm_params);
// enter wakeup
DSI_CHECK_RET(DSI_Wakeup());
// enable clock
DSI_CHECK_RET(DSI_EnableClk());
// engine reset
DSI_Reset();
#endif
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
#ifndef MT65XX_NEW_DISP
Wait_WakeUp();
#endif
#endif
}
else {
// backup dsi register
DSI_CHECK_RET(DSI_WaitForEngineNotBusy());
DSI_CHECK_RET(DSI_BackupRegisters());
// enter ULPS mode
DSI_clk_ULP_mode(1);
DSI_lane0_ULP_mode(1);
mdelay(1);
// disable engine clock
DSI_CHECK_RET(DSI_DisableClk());
// disable CG
DSI_CHECK_RET(DSI_PowerOff());
// disable mipi pll
DSI_PHY_clk_switch(FALSE, lcm_params);
// Switch bus to GPIO, then power level will be decided by GPIO setting.
DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
}
}
else {
if (enable) {
#if 0
// Switch bus to MIPI TX.
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
DSI_PHY_clk_switch(TRUE, lcm_params);
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
DSI_CHECK_RET(DSI_PowerOn());
DSI_clk_ULP_mode(0);
DSI_lane0_ULP_mode(0);
DSI_clk_HS_mode(0);
DSI_Reset();
DPI_CHECK_RET(DPI_PowerOn());
LCD_CHECK_RET(LCD_PowerOn());
#else
#ifndef MT65XX_NEW_DISP
DSI_PHY_clk_switch(TRUE, lcm_params);
DSI_CHECK_RET(DSI_PowerOn());
if(Need_Wait_ULPS())
Wait_ULPS_Mode();
DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
#else
needStartDSI = true;
// enable MMSYS CG
DSI_CHECK_RET(DSI_PowerOn());
// initialize clock setting
DSI_PHY_clk_setting(lcm_params);
// initialize dsi timing
DSI_PHY_TIMCONFIG(lcm_params);
// restore dsi register
DSI_CHECK_RET(DSI_RestoreRegisters());
// enable sleep-out mode
DSI_CHECK_RET(DSI_SleepOut());
// enter HS mode
DSI_PHY_clk_switch(TRUE, lcm_params);
// enter wakeup
DSI_CHECK_RET(DSI_Wakeup());
// enable clock
DSI_CHECK_RET(DSI_EnableClk());
// engine reset
DSI_Reset();
#endif
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
#ifndef MT65XX_NEW_DISP
Wait_WakeUp();
#endif
#endif
}
else {
#ifndef BUILD_UBOOT
is_video_mode_running = false;
if(lcm_params->dsi.noncont_clock)
DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period);
if(lcm_params->dsi.lcm_int_te_monitor)
DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period);
#endif
// backup dsi register
DSI_CHECK_RET(DSI_WaitForEngineNotBusy());
DSI_CHECK_RET(DSI_BackupRegisters());
// enter ULPS mode
DSI_clk_ULP_mode(1);
DSI_lane0_ULP_mode(1);
mdelay(1);
// disable engine clock
DSI_CHECK_RET(DSI_DisableClk());
// disable CG
DSI_CHECK_RET(DSI_PowerOff());
// disable mipi pll
DSI_PHY_clk_switch(FALSE, lcm_params);
// Switch bus to GPIO, then power level will be decided by GPIO setting.
DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
}
}
return DISP_STATUS_OK;
}
// protected by sem_early_suspend, sem_update_screen
static DISP_STATUS dsi_enable_power(BOOL enable)
{
disp_drv_dsi_init_context();
if(lcm_params->dsi.mode == CMD_MODE)
{
if (enable)
{
// enable MMSYS CG
DSI_CHECK_RET(DSI_PowerOn());
// initialize clock setting
DSI_PHY_clk_setting(lcm_params);
// restore dsi register
DSI_CHECK_RET(DSI_RestoreRegisters());
// enable sleep-out mode
DSI_CHECK_RET(DSI_SleepOut());
// enter HS mode
DSI_PHY_clk_switch(1);
// enter wakeup
DSI_CHECK_RET(DSI_Wakeup());
// enable clock
DSI_CHECK_RET(DSI_EnableClk());
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
DSI_Reset();
}
else
{
// backup dsi register
DSI_CHECK_RET(DSI_WaitForNotBusy());
DSI_CHECK_RET(DSI_BackupRegisters());
// enter ULPS mode
DSI_clk_ULP_mode(1);
DSI_lane0_ULP_mode(1);
DSI_clk_HS_mode(0);
// disable clock
DSI_CHECK_RET(DSI_DisableClk());
DSI_CHECK_RET(DSI_PowerOff());
// disable mipi pll
DSI_PHY_clk_switch(0);
// Switch bus to GPIO, then power level will be decided by GPIO setting.
DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
}
}
else
{
if (enable)
{
// enable MMSYS CG
DSI_CHECK_RET(DSI_PowerOn());
// initialize clock setting
DSI_PHY_clk_setting(lcm_params);
// restore dsi register
DSI_CHECK_RET(DSI_RestoreRegisters());
// enable sleep-out mode
DSI_CHECK_RET(DSI_SleepOut());
// enter HS mode
DSI_PHY_clk_switch(1);
// enter wakeup
DSI_CHECK_RET(DSI_Wakeup());
DSI_clk_HS_mode(0);
// enable clock
DSI_CHECK_RET(DSI_EnableClk());
DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
DSI_Reset();
needStartDSI = true;
}
else
{
is_video_mode_running = false;
// backup dsi register
DSI_CHECK_RET(DSI_WaitForNotBusy());
DSI_CHECK_RET(DSI_BackupRegisters());
// enter ULPS mode
DSI_clk_ULP_mode(1);
DSI_lane0_ULP_mode(1);
// disable clock
DSI_CHECK_RET(DSI_DisableClk());
DSI_CHECK_RET(DSI_PowerOff());
// disable mipi pll
DSI_PHY_clk_switch(0);
// Switch bus to GPIO, then power level will be decided by GPIO setting.
DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
}
}
return DISP_STATUS_OK;
}
