/****************************************************************************
* SramInit
****************************************************************************/
void SramInit(struct DibBridgeContext *pContext)
{
/** Sram Controller Initialization code ***/
#if (DIBCOM_TEST_MODE == TEST_MODE_HOOK)
HookInit(pContext,DIBBRIDGE_MODE_SRAM,pContext->BoardHdl);
if(pContext->DibChip == DIB_FIREFLY)
DibBridgeWriteReg16(pContext, 1817, 3);
#endif
}
/****************************************************************************
* Setup chip memory controller
****************************************************************************/
static DIBSTATUS DibBridgeFireflySetupDma(struct DibBridgeContext *pContext, struct DibBridgeDmaCtx *pDmaCtx)
{
union Dwd l;
DIBSTATUS ret = DIBSTATUS_ERROR;
uint8_t CfgBlk[14];
uint32_t ChipAddr = pDmaCtx->ChipAddr;
DIB_ASSERT(pDmaCtx->DmaLen > 0);
/* Set Len of transfer at Len */
pDmaCtx->DmaSize = pDmaCtx->DmaLen;
/** Overwrite ChipAddr to set the HostIf Interface register instead of the real chip.
* The pDmaCtx->ChipAddr is set to REG_RAMIF_DATA.
* The Byte Enabled flag will be set on the address by the DibBridgeSetHostIfMode function
* if the ByteMode passed to DibBridgeTargetDma, DibBridgeTargetWrite or DibBridgeTargetRead
* is DIBBRIDGE_BIT_MODE_8. The DibBridgeSetHostIfMode function will also disable autoincrement
* is destination address is REG_RAMIF_DATA, and enable it otherwise. */
pDmaCtx->Mode = DIBBRIDGE_BIT_MODE_8;
/* address formatting: use byte mode */
pDmaCtx->FmtChipAddr = REG_RAMIF_DATA | 0x2000;
/* Firefly previous porting compatibility */
pDmaCtx->ChipAddr = REG_RAMIF_DATA | 0x2000;
/* Odd start address at chip external space is not supported */
if((ChipAddr & 1) && (ChipAddr & (1L << 23)))
{
DIB_DEBUG(DMA_ERR, (CRB "Forbidden: odd start at ext mem" CRA));
return DIBSTATUS_ERROR;
}
ret = DibBridgeWriteReg16(pContext, REG_RAMIF_IRAMCFG, 1);
if(ret != DIBSTATUS_SUCCESS)
return ret;
CfgBlk[0] = 0;
CfgBlk[1] = 1;
l.l = ChipAddr;
CfgBlk[3] = l.b.hl;
CfgBlk[4] = l.b.lh;
CfgBlk[5] = l.b.ll;
l.l = pDmaCtx->ChipBaseMax;
CfgBlk[7] = l.b.hl;
CfgBlk[8] = l.b.lh;
CfgBlk[9] = l.b.ll;
l.l = pDmaCtx->ChipBaseMin;
CfgBlk[11] = l.b.hl;
CfgBlk[12] = l.b.lh;
CfgBlk[13] = l.b.ll;
ret = DibBridgeTargetWrite(pContext, REG_RAMIF_MODE | 0x1000, DIBBRIDGE_BIT_MODE_16, 14, &CfgBlk[0]);
if(ret != DIBSTATUS_SUCCESS)
return ret;
if(pDmaCtx->Dir == DIBBRIDGE_DMA_READ)
{
ret = DibBridgeWriteReg16(pContext, REG_RAMIF_MODE, (1L << 15) | 1);
if(ret != DIBSTATUS_SUCCESS)
return ret;
}
return DIBSTATUS_SUCCESS;
}
