//*****************************************************************************
//
//! \brief ADCSingleMode
//!
//! \param None
//!
//! \return None
//
//*****************************************************************************
void ADCSingleMode(void)
{
UNLOCKREG();
GCR->P5_MFP = (GCR->P5_MFP & 0x00FFFCFC) | 0x03; /* P5.1 -> XTAL2, P5.0 -> XTAL1 */
CLK->PWRCON_BITS.XTLCLK_EN = 1;
/* Waiting for 12M Xtal stalble */
while (DrvSYS_GetChipClockSourceStatus(XTL_CLK) != 1);
/* ADC sample code */
/* default setting: single end input, single operation mode, all channel disable, ADC clock frequency = 12MHz/(3+1) */
DrvADC_Open(0, EXTERNAL_CLOCK, 3);
AdcSingleModeTest();
DrvADC_Close();
}
void w55fa93_adc_recording_setup(void)
{
UINT32 u32Reg;
UINT32 eMode = eDRVADC_RECORD_MODE_1;
ENTER();
#if 1
DrvADC_Open(eDRVADC_RECORD, //Record mode
eDRVSYS_APLL, //Source clock come from UPLL
8); //Deafult 8K sample rate.
DrvADC_SetGainControl(eDRVADC_PRE_P14, eDRVADC_POST_P34P5);
// DrvADC_SetGainControl(eDRVADC_PRE_P14, eDRVADC_POST_P34P5);
//eDRVADC_POST_P0);
DrvADC_SetAutoGainTiming(4, //Period
4, //Attack
4, //Recovery
4); //Hold
DrvADC_SetAutoGainControl(TRUE,
//11, //Output target -12db
//15, //Output target -6db
//13, //Output target -9db
12, //Output target -10.5db
eDRVADC_BAND_P0P5,
eDRVADC_BAND_N0P5);
DrvADC_SetOffsetCancellation(FALSE, //BOOL bIsMuteEnable,
FALSE, //BOOL bIsOffsetCalibration,
FALSE, //BOOL bIsHardwareMode,
0x10); //UINT32 u32Offset
DrvADC_SetOffsetCancellationEx(1, //255 sample
512); //Delay sample count
DrvADC_SetNoiseGate(FALSE, eDRVADC_NG_N48);
#else
DrvADC_Open(eDRVADC_RECORD, //Record mode
eDRVSYS_APLL, //Source clock come from UPLL
8); //Deafult 8K sample rate.
DrvADC_SetGainControl(eDRVADC_PRE_P14,
eDRVADC_POST_P0);
DrvADC_SetClampingAGC(eDRVADC_MAX_P17P25,
eDRVADC_MIN_N12);
DrvADC_SetAutoGainTiming(4, //Period
4, //Attack
4, //Recovery sync
4); //Hold
DrvADC_SetOffsetCancellation(FALSE, //BOOL bIsMuteEnable,
FALSE, //BOOL bIsOffsetCalibration,
FALSE, //BOOL bIsHardwareMode,
0x1A); //UINT32 u32Offset
DrvADC_SetOffsetCancellationEx(1, //255 sample
256); //Delay sample count
DrvADC_SetNoiseGate(FALSE, eDRVADC_NG_N36);
DrvADC_SetAutoGainControl(TRUE,
12, //Output target -10.5db //11, //Output target -12db
eDRVADC_BAND_P0P5,
eDRVADC_BAND_N0P5);
#endif
outp32(REG_AUDIO_CON, inp32(REG_AUDIO_CON) &
~AUDIO_INT_MODE & ~AUDIO_INT_EN); // one sample if finish
outp32(REG_AGCP1,inp32(REG_AGCP1) | 0x80000000); // Enabe EDMA for ADC
}