/*
** EDMA Completion Interrupt Service Routine(ISR).
*/
static void Edma3CompletionIsr(void)
{
volatile unsigned int pendingIrqs;
unsigned int index = 1;
unsigned int count = 0;
if(EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS))
{
/*
** Wait for a finite time to monitor the EDMA Completion Interrupt
** status.
*/
while ((count < EDMA3CC_COMPL_HANDLER_RETRY_COUNT) && (index != 0u))
{
index = 0;
/* Get the Interrupt status. */
pendingIrqs = EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS);
while(pendingIrqs)
{
if((pendingIrqs & 1u) == TRUE)
{
/* Clear the interrupt status. */
EDMA3ClrIntr(SOC_EDMA30CC_0_REGS, index);
(*cb_Fxn[index])(index);
}
++index;
pendingIrqs >>= 1u;
}
count++;
}
}
}
/*
** EDMA transfer completion ISR
*/
static void EDMA3CCComplIsr(void)
{
/* Check if transmit DMA completed */
if(EDMA3GetIntrStatus(EDMA_INST_BASE) & (1 << EDMA_CHANNEL_IN_USE))
{
/* Clear the interrupt status for the first channel */
EDMA3ClrIntr(EDMA_INST_BASE, EDMA_CHANNEL_IN_USE);
McASPTxDMAComplHandler();
}
}
void isr_Edma3Completion(unsigned int intnum) {
UNUSED(intnum);
unsigned int pendingIrqsL, pendingIrqsH;
pendingIrqsL = EDMA3GetIntrStatus(EDMA_INST_BASE);
pendingIrqsH = EDMA3IntrStatusHighGet(EDMA_INST_BASE);
/*shift and test status bit ,if set call hook function that registed by user*/
if (pendingIrqsL) {
for (int i = 0; i < 32; i++) {
if (pendingIrqsL & (1ul << i)) {
if (dma_Fxn[i] != NULL) {
(*dma_Fxn[i])(i, EDMA3_XFER_COMPLETE);
}
EDMA3ClrIntr(EDMA_INST_BASE, i);
pendingIrqsL &= ~(1ul << i);
if (!pendingIrqsL) break;
}
}
}
if (pendingIrqsH) {
for (int i = 0; i < 32; i++) {
if (pendingIrqsH & (1ul << i)) {
if (dma_Fxn[i + 32] != NULL) {
(*dma_Fxn[i + 32])(i + 32, EDMA3_XFER_COMPLETE);
}
EDMA3ClrIntr(EDMA_INST_BASE, i + 32);
pendingIrqsH &= ~(1ul << i);
if (!pendingIrqsH) break;
}
}
}
/*revaluate interrupt bit ,retrig interrupt if interrupt state bit set*/
pendingIrqsL = EDMA3GetIntrStatus(EDMA_INST_BASE);
pendingIrqsH = EDMA3IntrStatusHighGet(EDMA_INST_BASE);
if (pendingIrqsL || pendingIrqsH) {
EDMA3ErrIntrTrig(EDMA_INST_BASE);
}
}
/*
** EDMA transfer completion ISR
*/
static void EDMA3CCComplIsr(void)
{
#ifdef _TMS320C6X
IntEventClear(SYS_INT_EDMA3_0_CC0_INT1);
#else
IntSystemStatusClear(SYS_INT_CCINT0);
#endif
/* Check if receive DMA completed */
if(EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS) & (1 << EDMA3_CHA_MCASP0_RX))
{
/* Clear the interrupt status for the 0th channel */
EDMA3ClrIntr(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX);
McASPRxDMAComplHandler();
}
/* Check if transmit DMA completed */
if(EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS) & (1 << EDMA3_CHA_MCASP0_TX))
{
/* Clear the interrupt status for the first channel */
EDMA3ClrIntr(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_TX);
McASPTxDMAComplHandler();
}
}
static void Edma3CompletionIsr(void)
{
volatile unsigned int pendingIrqs;
volatile unsigned int isIPR = 0;
unsigned int indexl;
unsigned int Cnt = 0;
indexl = 1;
isIPR = EDMA3GetIntrStatus(EDMA_INST_BASE);
if(isIPR)
{
while ((Cnt < EDMA3CC_COMPL_HANDLER_RETRY_COUNT)&& (indexl != 0u))
{
indexl = 0u;
pendingIrqs = EDMA3GetIntrStatus(EDMA_INST_BASE);
while (pendingIrqs)
{
if((pendingIrqs & 1u) == TRUE)
{
/**
* If the user has not given any callback function
* while requesting the TCC, its TCC specific bit
* in the IPR register will NOT be cleared.
*/
/* here write to ICR to clear the corresponding IPR bits */
EDMA3ClrIntr(EDMA_INST_BASE, indexl);
if (cb_Fxn[indexl] != NULL)
{
(*cb_Fxn[indexl])(indexl, EDMA3_XFER_COMPLETE);
}
}
++indexl;
pendingIrqs >>= 1u;
}
Cnt++;
}
}
}
/*
** EDMA3 completion Interrupt Service Routine(ISR).
*/
static void Edma3ComplHandlerIsr(void)
{
unsigned int pendingIrqs;
unsigned int isIPR = 0;
unsigned int indexl;
unsigned int Cnt = 0;
indexl = 1;
isIPR = EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS);
if(isIPR)
{
while ((Cnt < EDMA3CC_COMPL_HANDLER_RETRY_COUNT)&& (indexl != 0))
{
indexl = 0;
pendingIrqs = EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS);
while (pendingIrqs)
{
if((pendingIrqs & 1) == TRUE)
{
/**
* If the user has not given any callback function
* while requesting the TCC, its TCC specific bit
* in the IPR register will NOT be cleared.
*/
/* Here write to ICR to clear the corresponding IPR bits. */
EDMA3ClrIntr(SOC_EDMA30CC_0_REGS, indexl);
(*cb_Fxn[indexl])(indexl, EDMA3_XFER_COMPLETE);
}
++indexl;
pendingIrqs >>= 1;
}
Cnt++;
}
}
}
/*
** ISR for successful transfer completion.
**
** Note: This function first disables its own interrupt to make it non-entrant.
*/
void _EDMAAppEdma3ccComplIsr()
{
volatile unsigned int pendingIrqs;
volatile unsigned int isIntrPending = 0u;
volatile unsigned int isHighIntrPending = 0u;
unsigned int index;
unsigned int count = 0u;
index = 1u;
isIntrPending = EDMA3GetIntrStatus(EDMAAPP_EDMACC_BASE_ADDRESS);
isHighIntrPending = EDMA3IntrStatusHighGet(EDMAAPP_EDMACC_BASE_ADDRESS);
if(isIntrPending | isHighIntrPending)
{
while ((count < EDMA3CC_COMPL_HANDLER_RETRY_COUNT)&& (index != 0u))
{
index = 0u;
if(isIntrPending)
{
pendingIrqs = EDMA3GetIntrStatus(EDMAAPP_EDMACC_BASE_ADDRESS);
}
else
{
pendingIrqs =
EDMA3IntrStatusHighGet(EDMAAPP_EDMACC_BASE_ADDRESS);
}
while(pendingIrqs)
{
if(TRUE == (pendingIrqs & 1u))
{
/*
**
** If the user has not given any Callback function
** while requesting the TCC, its TCC specific bit
** in the IPR register will NOT be cleared.
*/
if(isIntrPending)
{
/*
** Here write to ICR to clear the corresponding
** IPR bits
*/
EDMA3ClrIntr(EDMAAPP_EDMACC_BASE_ADDRESS, index);
(*EDMAAppCallbackFxn[index])(EDMA3_XFER_COMPLETE);
}
else
{
/*
** Here write to ICR to clear the corresponding
** IPR bits
*/
EDMA3ClrIntr(EDMAAPP_EDMACC_BASE_ADDRESS, index + 32u);
(*EDMAAppCallbackFxn[index + 32u])(EDMA3_XFER_COMPLETE);
}
}
++index;
pendingIrqs >>= 1u;
}
count++;
}
}
}