static bool siena_mcdi_poll_response(struct efx_nic *efx)
{
unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
efx_dword_t hdr;
efx_readd(efx, &hdr, pdu);
/* All 1's indicates that shared memory is in reset (and is
* not a valid hdr). Wait for it to come out reset before
* completing the command
*/
return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
}
static int siena_mcdi_poll_reboot(struct efx_nic *efx)
{
struct siena_nic_data *nic_data = efx->nic_data;
unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
efx_dword_t reg;
u32 value;
efx_readd(efx, ®, addr);
value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
if (value == 0)
return 0;
EFX_ZERO_DWORD(reg);
efx_writed(efx, ®, addr);
/* MAC statistics have been cleared on the NIC; clear the local
* copies that we update with efx_update_diff_stat().
*/
nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;
nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;
if (value == MC_STATUS_DWORD_ASSERT)
return -EINTR;
else
return -EIO;
}
void
efx_intr_status_line(
__in efx_nic_t *enp,
__out boolean_t *fatalp,
__out uint32_t *qmaskp)
{
efx_intr_t *eip = &(enp->en_intr);
efx_dword_t dword;
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
/*
* Read the queue mask and implicitly acknowledge the
* interrupt.
*/
EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE);
*qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
EFSYS_PROBE1(qmask, uint32_t, *qmaskp);
if (*qmaskp & (1U << eip->ei_level))
*fatalp = efx_intr_check_fatal(enp);
else
*fatalp = B_FALSE;
}
static int efx_mcdi_bist(struct efx_nic *efx, unsigned int bist_mode,
int *results)
{
unsigned int retry, i, count = 0;
size_t outlen;
u32 status;
MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_SFT9001_LEN);
u8 *ptr;
int rc;
BUILD_BUG_ON(MC_CMD_START_BIST_OUT_LEN != 0);
MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_mode);
rc = efx_mcdi_rpc(efx, MC_CMD_START_BIST,
inbuf, MC_CMD_START_BIST_IN_LEN, NULL, 0, NULL);
if (rc)
goto out;
/* Wait up to 10s for BIST to finish */
for (retry = 0; retry < 100; ++retry) {
BUILD_BUG_ON(MC_CMD_POLL_BIST_IN_LEN != 0);
rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
outbuf, sizeof(outbuf), &outlen);
if (rc)
goto out;
status = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
if (status != MC_CMD_POLL_BIST_RUNNING)
goto finished;
msleep(100);
}
rc = -ETIMEDOUT;
goto out;
finished:
results[count++] = (status == MC_CMD_POLL_BIST_PASSED) ? 1 : -1;
/* SFT9001 specific cable diagnostics output */
if (efx->phy_type == PHY_TYPE_SFT9001B &&
(bist_mode == MC_CMD_PHY_BIST_CABLE_SHORT ||
bist_mode == MC_CMD_PHY_BIST_CABLE_LONG)) {
ptr = MCDI_PTR(outbuf, POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A);
if (status == MC_CMD_POLL_BIST_PASSED &&
outlen >= MC_CMD_POLL_BIST_OUT_SFT9001_LEN) {
for (i = 0; i < 8; i++) {
results[count + i] =
EFX_DWORD_FIELD(((efx_dword_t *)ptr)[i],
EFX_DWORD_0);
}
}
count += 8;
}
rc = count;
out:
return rc;
}
void
hunt_mcdi_request_copyout(
__in efx_nic_t *enp,
__in efx_mcdi_req_t *emrp)
{
#if EFSYS_OPT_MCDI_LOGGING
const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp;
#endif /* EFSYS_OPT_MCDI_LOGGING */
efx_dword_t hdr[2];
unsigned int hdr_len;
size_t bytes;
if (emrp->emr_out_buf == NULL)
return;
/* Read the command header to detect MCDI response format */
hdr_len = sizeof (hdr[0]);
hunt_mcdi_read_response(enp, &hdr[0], 0, hdr_len);
if (EFX_DWORD_FIELD(hdr[0], MCDI_HEADER_CODE) == MC_CMD_V2_EXTN) {
/*
* Read the actual payload length. The length given in the event
* is only correct for responses with the V1 format.
*/
hunt_mcdi_read_response(enp, &hdr[1], hdr_len, sizeof (hdr[1]));
hdr_len += sizeof (hdr[1]);
emrp->emr_out_length_used = EFX_DWORD_FIELD(hdr[1],
MC_CMD_V2_EXTN_IN_ACTUAL_LEN);
}
/* Copy payload out into caller supplied buffer */
bytes = MIN(emrp->emr_out_length_used, emrp->emr_out_length);
hunt_mcdi_read_response(enp, emrp->emr_out_buf, hdr_len, bytes);
#if EFSYS_OPT_MCDI_LOGGING
if (emtp->emt_logger != NULL) {
emtp->emt_logger(emtp->emt_context,
EFX_LOG_MCDI_RESPONSE,
&hdr, hdr_len,
emrp->emr_out_buf, bytes);
}
#endif /* EFSYS_OPT_MCDI_LOGGING */
}
/*
* To support clients which aren't provided with any PCI context infer
* the hardware family by inspecting the hardware. Obviously the caller
* must be damn sure they're really talking to a supported device.
*/
__checkReturn int
efx_infer_family(
__in efsys_bar_t *esbp,
__out efx_family_t *efp)
{
efx_family_t family;
efx_oword_t oword;
unsigned int portnum;
int rc;
EFSYS_BAR_READO(esbp, FR_AZ_CS_DEBUG_REG_OFST, &oword, B_TRUE);
portnum = EFX_OWORD_FIELD(oword, FRF_CZ_CS_PORT_NUM);
switch (portnum) {
case 0: {
efx_dword_t dword;
uint32_t hw_rev;
EFSYS_BAR_READD(esbp, ER_DZ_BIU_HW_REV_ID_REG_OFST, &dword,
B_TRUE);
hw_rev = EFX_DWORD_FIELD(dword, ERF_DZ_HW_REV_ID);
if (hw_rev == ER_DZ_BIU_HW_REV_ID_REG_RESET) {
#if EFSYS_OPT_HUNTINGTON
family = EFX_FAMILY_HUNTINGTON;
break;
#endif
} else {
#if EFSYS_OPT_FALCON
family = EFX_FAMILY_FALCON;
break;
#endif
}
rc = ENOTSUP;
goto fail1;
}
#if EFSYS_OPT_SIENA
case 1:
case 2:
family = EFX_FAMILY_SIENA;
break;
#endif
default:
rc = ENOTSUP;
goto fail1;
}
if (efp != NULL)
*efp = family;
return (0);
fail1:
EFSYS_PROBE1(fail1, int, rc);
return (rc);
}
__checkReturn boolean_t
hunt_mcdi_poll_response(
__in efx_nic_t *enp)
{
const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp;
efsys_mem_t *esmp = emtp->emt_dma_mem;
efx_dword_t hdr;
EFSYS_MEM_READD(esmp, 0, &hdr);
return (EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE) ? B_TRUE : B_FALSE);
}
/*
* To support clients which aren't provided with any PCI context infer
* the hardware family by inspecting the hardware. Obviously the caller
* must be damn sure they're really talking to a supported device.
*/
__checkReturn efx_rc_t
efx_infer_family(
__in efsys_bar_t *esbp,
__out efx_family_t *efp)
{
efx_family_t family;
efx_oword_t oword;
unsigned int portnum;
efx_rc_t rc;
EFSYS_BAR_READO(esbp, FR_AZ_CS_DEBUG_REG_OFST, &oword, B_TRUE);
portnum = EFX_OWORD_FIELD(oword, FRF_CZ_CS_PORT_NUM);
if ((portnum == 1) || (portnum == 2)) {
#if EFSYS_OPT_SIENA
family = EFX_FAMILY_SIENA;
goto out;
#endif
} else if (portnum == 0) {
efx_dword_t dword;
uint32_t hw_rev;
EFSYS_BAR_READD(esbp, ER_DZ_BIU_HW_REV_ID_REG_OFST, &dword,
B_TRUE);
hw_rev = EFX_DWORD_FIELD(dword, ERF_DZ_HW_REV_ID);
if (hw_rev == ER_DZ_BIU_HW_REV_ID_REG_RESET) {
#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
/*
* BIU_HW_REV_ID is the same for Huntington and Medford.
* Assume Huntington, as Medford is very similar.
*/
family = EFX_FAMILY_HUNTINGTON;
goto out;
#endif
} else {
#if EFSYS_OPT_FALCON
family = EFX_FAMILY_FALCON;
goto out;
#endif
}
}
rc = ENOTSUP;
goto fail1;
out:
if (efp != NULL)
*efp = family;
return (0);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
return (rc);
}
/* Test and clear MC-rebooted flag for this port/function */
int efx_mcdi_poll_reboot(struct efx_nic *efx)
{
unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_REBOOT_FLAG(efx);
efx_dword_t reg;
uint32_t value;
if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
return false;
efx_readd(efx, ®, addr);
value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
if (value == 0)
return 0;
EFX_ZERO_DWORD(reg);
efx_writed(efx, ®, addr);
if (value == MC_STATUS_DWORD_ASSERT)
return -EINTR;
else
return -EIO;
}
void
efx_intr_status_line(
__in efx_nic_t *enp,
__out boolean_t *fatalp,
__out uint32_t *qmaskp)
{
efx_intr_t *eip = &(enp->en_intr);
efx_dword_t dword;
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
/* Ensure Huntington and Falcon/Siena ISR at same location */
EFX_STATIC_ASSERT(FR_BZ_INT_ISR0_REG_OFST ==
ER_DZ_BIU_INT_ISR_REG_OFST);
/*
* Read the queue mask and implicitly acknowledge the
* interrupt.
*/
EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE);
*qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
EFSYS_PROBE1(qmask, uint32_t, *qmaskp);
#if EFSYS_OPT_HUNTINGTON
if (enp->en_family == EFX_FAMILY_HUNTINGTON) {
/* Huntington reports fatal errors via events */
*fatalp = B_FALSE;
return;
}
#endif
if (*qmaskp & (1U << eip->ei_level))
*fatalp = falconsiena_intr_check_fatal(enp);
else
*fatalp = B_FALSE;
}
static int efx_mcdi_poll(struct efx_nic *efx)
{
struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
unsigned int time, finish;
unsigned int respseq, respcmd, error;
unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
unsigned int rc, spins;
efx_dword_t reg;
/* Check for a reboot atomically with respect to efx_mcdi_copyout() */
rc = -efx_mcdi_poll_reboot(efx);
if (rc)
goto out;
/* Poll for completion. Poll quickly (once a us) for the 1st jiffy,
* because generally mcdi responses are fast. After that, back off
* and poll once a jiffy (approximately)
*/
spins = TICK_USEC;
finish = get_seconds() + MCDI_RPC_TIMEOUT;
while (1) {
if (spins != 0) {
--spins;
udelay(1);
} else {
schedule_timeout_uninterruptible(1);
}
time = get_seconds();
rmb();
efx_readd(efx, ®, pdu);
/* All 1's indicates that shared memory is in reset (and is
* not a valid header). Wait for it to come out reset before
* completing the command */
if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) != 0xffffffff &&
EFX_DWORD_FIELD(reg, MCDI_HEADER_RESPONSE))
break;
if (time >= finish)
return -ETIMEDOUT;
}
mcdi->resplen = EFX_DWORD_FIELD(reg, MCDI_HEADER_DATALEN);
respseq = EFX_DWORD_FIELD(reg, MCDI_HEADER_SEQ);
respcmd = EFX_DWORD_FIELD(reg, MCDI_HEADER_CODE);
error = EFX_DWORD_FIELD(reg, MCDI_HEADER_ERROR);
if (error && mcdi->resplen == 0) {
netif_err(efx, hw, efx->net_dev, "MC rebooted\n");
rc = EIO;
} else if ((respseq ^ mcdi->seqno) & SEQ_MASK) {
netif_err(efx, hw, efx->net_dev,
"MC response mismatch tx seq 0x%x rx seq 0x%x\n",
respseq, mcdi->seqno);
rc = EIO;
} else if (error) {
efx_readd(efx, ®, pdu + 4);
switch (EFX_DWORD_FIELD(reg, EFX_DWORD_0)) {
#define TRANSLATE_ERROR(name) \
case MC_CMD_ERR_ ## name: \
rc = name; \
break
TRANSLATE_ERROR(ENOENT);
TRANSLATE_ERROR(EINTR);
TRANSLATE_ERROR(EACCES);
TRANSLATE_ERROR(EBUSY);
TRANSLATE_ERROR(EINVAL);
TRANSLATE_ERROR(EDEADLK);
TRANSLATE_ERROR(ENOSYS);
TRANSLATE_ERROR(ETIME);
#undef TRANSLATE_ERROR
default:
rc = EIO;
break;
}
} else
rc = 0;
out:
mcdi->resprc = rc;
if (rc)
mcdi->resplen = 0;
/* Return rc=0 like wait_event_timeout() */
return 0;
}
static __checkReturn efx_rc_t
siena_board_cfg(
__in efx_nic_t *enp)
{
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
uint8_t mac_addr[6];
efx_dword_t capabilities;
uint32_t board_type;
uint32_t nevq, nrxq, ntxq;
efx_rc_t rc;
/* External port identifier using one-based port numbering */
encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port;
/* Board configuration */
if ((rc = efx_mcdi_get_board_cfg(enp, &board_type,
&capabilities, mac_addr)) != 0)
goto fail1;
EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
encp->enc_board_type = board_type;
/* Additional capabilities */
encp->enc_clk_mult = 1;
if (EFX_DWORD_FIELD(capabilities, MC_CMD_CAPABILITIES_TURBO)) {
enp->en_features |= EFX_FEATURE_TURBO;
if (EFX_DWORD_FIELD(capabilities,
MC_CMD_CAPABILITIES_TURBO_ACTIVE)) {
encp->enc_clk_mult = 2;
}
}
encp->enc_evq_timer_quantum_ns =
EFX_EVQ_SIENA_TIMER_QUANTUM_NS / encp->enc_clk_mult;
encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
/* When hash header insertion is enabled, Siena inserts 16 bytes */
encp->enc_rx_prefix_size = 16;
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
encp->enc_rx_buf_align_end = 1;
/* Alignment for WPTR updates */
encp->enc_rx_push_align = 1;
/* Resource limits */
rc = efx_mcdi_get_resource_limits(enp, &nevq, &nrxq, &ntxq);
if (rc != 0) {
if (rc != ENOTSUP)
goto fail2;
nevq = 1024;
nrxq = EFX_RXQ_LIMIT_TARGET;
ntxq = EFX_TXQ_LIMIT_TARGET;
}
encp->enc_evq_limit = nevq;
encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
(encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -
(encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
encp->enc_fw_assisted_tso_enabled = B_FALSE;
encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
return (0);
fail2:
EFSYS_PROBE(fail2);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
return (rc);
}
void
efx_mcdi_read_response_header(
__in efx_nic_t *enp,
__inout efx_mcdi_req_t *emrp)
{
#if EFSYS_OPT_MCDI_LOGGING
const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp;
#endif /* EFSYS_OPT_MCDI_LOGGING */
efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
efx_dword_t hdr[2];
unsigned int hdr_len;
unsigned int data_len;
unsigned int seq;
unsigned int cmd;
unsigned int error;
efx_rc_t rc;
EFSYS_ASSERT(emrp != NULL);
efx_mcdi_read_response(enp, &hdr[0], 0, sizeof (hdr[0]));
hdr_len = sizeof (hdr[0]);
cmd = EFX_DWORD_FIELD(hdr[0], MCDI_HEADER_CODE);
seq = EFX_DWORD_FIELD(hdr[0], MCDI_HEADER_SEQ);
error = EFX_DWORD_FIELD(hdr[0], MCDI_HEADER_ERROR);
if (cmd != MC_CMD_V2_EXTN) {
data_len = EFX_DWORD_FIELD(hdr[0], MCDI_HEADER_DATALEN);
} else {
efx_mcdi_read_response(enp, &hdr[1], hdr_len, sizeof (hdr[1]));
hdr_len += sizeof (hdr[1]);
cmd = EFX_DWORD_FIELD(hdr[1], MC_CMD_V2_EXTN_IN_EXTENDED_CMD);
data_len =
EFX_DWORD_FIELD(hdr[1], MC_CMD_V2_EXTN_IN_ACTUAL_LEN);
}
if (error && (data_len == 0)) {
/* The MC has rebooted since the request was sent. */
EFSYS_SPIN(EFX_MCDI_STATUS_SLEEP_US);
efx_mcdi_poll_reboot(enp);
rc = EIO;
goto fail1;
}
if ((cmd != emrp->emr_cmd) ||
(seq != ((emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ)))) {
/* Response is for a different request */
rc = EIO;
goto fail2;
}
if (error) {
efx_dword_t err[2];
unsigned int err_len = MIN(data_len, sizeof (err));
int err_code = MC_CMD_ERR_EPROTO;
int err_arg = 0;
/* Read error code (and arg num for MCDI v2 commands) */
efx_mcdi_read_response(enp, &err, hdr_len, err_len);
if (err_len >= (MC_CMD_ERR_CODE_OFST + sizeof (efx_dword_t)))
err_code = EFX_DWORD_FIELD(err[0], EFX_DWORD_0);
#ifdef WITH_MCDI_V2
if (err_len >= (MC_CMD_ERR_ARG_OFST + sizeof (efx_dword_t)))
err_arg = EFX_DWORD_FIELD(err[1], EFX_DWORD_0);
#endif
emrp->emr_err_code = err_code;
emrp->emr_err_arg = err_arg;
#if EFSYS_OPT_MCDI_PROXY_AUTH
if ((err_code == MC_CMD_ERR_PROXY_PENDING) &&
(err_len == sizeof (err))) {
/*
* The MCDI request would normally fail with EPERM, but
* firmware has forwarded it to an authorization agent
* attached to a privileged PF.
*
* Save the authorization request handle. The client
* must wait for a PROXY_RESPONSE event, or timeout.
*/
emrp->emr_proxy_handle = err_arg;
}
#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
#if EFSYS_OPT_MCDI_LOGGING
if (emtp->emt_logger != NULL) {
emtp->emt_logger(emtp->emt_context,
EFX_LOG_MCDI_RESPONSE,
&hdr, hdr_len,
&err, err_len);
}
#endif /* EFSYS_OPT_MCDI_LOGGING */
if (!emrp->emr_quiet) {
EFSYS_PROBE3(mcdi_err_arg, int, emrp->emr_cmd,
int, err_code, int, err_arg);
}
rc = efx_mcdi_request_errcode(err_code);
goto fail3;
}
static __checkReturn efx_rc_t
siena_board_cfg(
__in efx_nic_t *enp)
{
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
uint8_t mac_addr[6];
efx_dword_t capabilities;
uint32_t board_type;
uint32_t nevq, nrxq, ntxq;
efx_rc_t rc;
/* External port identifier using one-based port numbering */
encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port;
/* Board configuration */
if ((rc = efx_mcdi_get_board_cfg(enp, &board_type,
&capabilities, mac_addr)) != 0)
goto fail1;
EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
encp->enc_board_type = board_type;
/*
* There is no possibility to determine the number of PFs on Siena
* by issuing MCDI request, and it is not an easy task to find the
* value based on the board type, so 'enc_hw_pf_count' is set to 1
*/
encp->enc_hw_pf_count = 1;
/* Additional capabilities */
encp->enc_clk_mult = 1;
if (EFX_DWORD_FIELD(capabilities, MC_CMD_CAPABILITIES_TURBO)) {
enp->en_features |= EFX_FEATURE_TURBO;
if (EFX_DWORD_FIELD(capabilities,
MC_CMD_CAPABILITIES_TURBO_ACTIVE)) {
encp->enc_clk_mult = 2;
}
}
encp->enc_evq_timer_quantum_ns =
EFX_EVQ_SIENA_TIMER_QUANTUM_NS / encp->enc_clk_mult;
encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
/* When hash header insertion is enabled, Siena inserts 16 bytes */
encp->enc_rx_prefix_size = 16;
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
encp->enc_rx_buf_align_end = 1;
/* Alignment for WPTR updates */
encp->enc_rx_push_align = 1;
encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
/* Fragments must not span 4k boundaries. */
encp->enc_tx_dma_desc_boundary = 4096;
/* Resource limits */
rc = efx_mcdi_get_resource_limits(enp, &nevq, &nrxq, &ntxq);
if (rc != 0) {
if (rc != ENOTSUP)
goto fail2;
nevq = 1024;
nrxq = EFX_RXQ_LIMIT_TARGET;
ntxq = EFX_TXQ_LIMIT_TARGET;
}
encp->enc_evq_limit = nevq;
encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
(encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -
(encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
encp->enc_fw_assisted_tso_enabled = B_FALSE;
encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
encp->enc_fw_assisted_tso_v2_n_contexts = 0;
encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
/* Siena supports two 10G ports, and 8 lanes of PCIe Gen2 */
encp->enc_required_pcie_bandwidth_mbps = 2 * 10000;
encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN2;
encp->enc_fw_verified_nvram_update_required = B_FALSE;
return (0);
fail2:
EFSYS_PROBE(fail2);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
return (rc);
}
* Until its callers are fixed, it should always return 0. */ _NOTE(ARGUNUSED(enp)) return (0); #else efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); unsigned int rebootr; efx_dword_t dword; uint32_t value; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); EFSYS_ASSERT(emip->emi_port == 1 || emip->emi_port == 2); rebootr = SIENA_MCDI_STATUS(emip); EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM, rebootr, &dword, B_FALSE); value = EFX_DWORD_FIELD(dword, EFX_DWORD_0); if (value == 0) return (0); EFX_ZERO_DWORD(dword); EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, rebootr, &dword, B_FALSE); if (value == MC_STATUS_DWORD_ASSERT) return (EINTR); else return (EIO); #endif } extern __checkReturn boolean_t
static int efx_mcdi_bist(struct efx_nic *efx, unsigned int bist_mode,
int *results)
{
unsigned int retry, i, count = 0;
size_t outlen;
u32 status;
u8 *buf, *ptr;
int rc;
buf = kzalloc(0x100, GFP_KERNEL);
if (buf == NULL)
return -ENOMEM;
BUILD_BUG_ON(MC_CMD_START_BIST_OUT_LEN != 0);
MCDI_SET_DWORD(buf, START_BIST_IN_TYPE, bist_mode);
rc = efx_mcdi_rpc(efx, MC_CMD_START_BIST, buf, MC_CMD_START_BIST_IN_LEN,
NULL, 0, NULL);
if (rc)
goto out;
for (retry = 0; retry < 100; ++retry) {
BUILD_BUG_ON(MC_CMD_POLL_BIST_IN_LEN != 0);
rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
buf, 0x100, &outlen);
if (rc)
goto out;
status = MCDI_DWORD(buf, POLL_BIST_OUT_RESULT);
if (status != MC_CMD_POLL_BIST_RUNNING)
goto finished;
msleep(100);
}
rc = -ETIMEDOUT;
goto out;
finished:
results[count++] = (status == MC_CMD_POLL_BIST_PASSED) ? 1 : -1;
if (efx->phy_type == PHY_TYPE_SFT9001B &&
(bist_mode == MC_CMD_PHY_BIST_CABLE_SHORT ||
bist_mode == MC_CMD_PHY_BIST_CABLE_LONG)) {
ptr = MCDI_PTR(buf, POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A);
if (status == MC_CMD_POLL_BIST_PASSED &&
outlen >= MC_CMD_POLL_BIST_OUT_SFT9001_LEN) {
for (i = 0; i < 8; i++) {
results[count + i] =
EFX_DWORD_FIELD(((efx_dword_t *)ptr)[i],
EFX_DWORD_0);
}
}
count += 8;
}
rc = count;
out:
kfree(buf);
return rc;
}
