void sb_WriteMem(u32 addr,u32 data,u32 sz)
{
u32 offset = addr-SB_BASE;
#ifdef TRACE
if (offset & 3/*(size-1)*/) //4 is min align size
{
EMUERROR("Unaligned System bus register write");
}
#endif
offset>>=2;
#ifdef TRACE
if (sb_regs[offset].flags & sz)
{
#endif
if (!(sb_regs[offset].flags & REG_WF) )
{
if (sz==4)
sb_regs[offset].data32=data;
else if (sz==2)
sb_regs[offset].data16=(u16)data;
else
sb_regs[offset].data8=(u8)data;
return;
}
else
{
//printf("SBW: %08X\n",addr);
sb_regs[offset].writeFunctionAddr(addr,data);
/*
if (sb_regs[offset].flags & REG_CONST)
EMUERROR("Error [Write to read only register , const]");
else
{
if ()
{
sb_regs[offset].writeFunction(data);
return;
}
else
{
if (!(sb_regs[offset].flags& REG_NOT_IMPL))
EMUERROR("ERROR [Write to read only register]");
}
}*/
return;
}
#ifdef TRACE
}
else
{
if (!(sb_regs[offset].flags& REG_NOT_IMPL))
EMUERROR4("ERROR :wrong size write on register ; offset=%x , data=%x,sz=%d",offset,data,sz);
}
if ((sb_regs[offset].flags& REG_NOT_IMPL))
EMUERROR3("Write to System Control Regs , not implemented , addr=%x,data=%x",addr,data);
#endif
}
void WriteBios(u32 addr,u32 data,u32 sz)
{
if (!(addr&0x10000)) //upper 64 kb is flashrom
{
EMUERROR4("Write to [Boot ROM] is not possible, addr=%x,data=%x,size=%d",addr,data,sz);
}
else
{
sys_nvmem.Write(addr,data,sz);
}
}
INLINE void RegSWrite(RegisterStruct* reg,u32 offset,u32 data)
{
#ifdef TRACE
if (offset & 3/*(size-1)*/) //4 is min allign size
{
EMUERROR("unallinged register write");
}
#endif
offset>>=2;
#ifdef TRACE
if (reg[offset].flags & size)
{
#endif
if (reg[offset].flags & REG_WRITE_DATA)
{
if (size==4)
*reg[offset].data32=data;
else if (size==2)
*reg[offset].data16=(u16)data;
else
*reg[offset].data8=(u8)data;
return;
}
else
{
if (reg[offset].flags & REG_CONST)
EMUERROR("Error [Write to read olny register , const]");
else
{
if (reg[offset].writeFunction)
{
reg[offset].writeFunction(data);
return;
}
else
{
if (!(reg[offset].flags& REG_NOT_IMPL))
EMUERROR("ERROR [Write to read olny register]");
}
}
}
#ifdef TRACE
}
else
{
if (!(reg[offset].flags& REG_NOT_IMPL))
EMUERROR4("ERROR :wrong size write on register ; offset=%x , data=%x,sz=%d",offset,data,size);
}
#endif
if ((reg[offset].flags& REG_NOT_IMPL))
EMUERROR3("Write to internal Regs , not implemented , offset=%x,data=%x",offset,data);
}
void WriteFlash(u32 addr,u32 data,u32 sz) { EMUERROR4("Write to [Flash ROM] is not possible, addr=%x,data=%x,size=%d",addr,data,sz); }
void WriteBios(u32 addr,u32 data,u32 sz) { EMUERROR4("Write to [Boot ROM] is not possible, addr=%x,data=%x,size=%d",addr,data,sz); }
void DYNACALL WriteMem_area0(u32 addr,T data)
{
addr &= 0x01FFFFFF;//to get rid of non needed bits
const u32 base=(addr>>16);
//map 0x0000 to 0x001F
if ((base <=0x001F) /*&& (addr<=0x001FFFFF)*/)// :MPX System/Boot ROM
{
//EMUERROR4("Write to [MPX System/Boot ROM] is not possible, addr=%x,data=%x,size=%d",addr,data,sz);
WriteBios(addr,data,sz);
}
//map 0x0020 to 0x0021
else if ((base >=0x0020) && (base <=0x0021) /*&& (addr>= 0x00200000) && (addr<= 0x0021FFFF)*/) // Flash Memory
{
//EMUERROR4("Write to [Flash Memory] , sz?!, addr=%x,data=%x,size=%d",addr,data,sz);
WriteFlash(addr,data,sz);
}
//map 0x0040 to 0x005F -> actually, I'll only map 0x005F to 0x005F, b/c the rest of it is unspammed (left to default handler)
//map 0x005F to 0x005F
else if ( likely(base==0x005F) )
{
if (/*&& (addr>= 0x00400000) */ (addr<= 0x005F67FF)) // Unassigned
{
EMUERROR4("Write to area0_32 not implemented [Unassigned], addr=%x,data=%x,size=%d",addr,data,sz);
}
else if ((addr>= 0x005F7000) && (addr<= 0x005F70FF)) // GD-ROM
{
//EMUERROR4("Write to area0_32 not implemented [GD-ROM], addr=%x,data=%x,size=%d",addr,data,sz);
#if DC_PLATFORM == DC_PLATFORM_NAOMI || DC_PLATFORM == DC_PLATFORM_ATOMISWAVE
WriteMem_naomi(addr,data,sz);
#else
WriteMem_gdrom(addr,data,sz);
#endif
}
else if ( likely((addr>= 0x005F6800) && (addr<=0x005F7CFF)) ) // /*:PVR i/f Control Reg.*/ -> ALL SB registers
{
//EMUERROR4("Write to area0_32 not implemented [PVR i/f Control Reg], addr=%x,data=%x,size=%d",addr,data,sz);
sb_WriteMem(addr,data,sz);
}
else if ( likely((addr>= 0x005F8000) && (addr<=0x005F9FFF)) ) // TA / PVR Core Reg.
{
//EMUERROR4("Write to area0_32 not implemented [TA / PVR Core Reg], addr=%x,data=%x,size=%d",addr,data,sz);
verify(sz==4);
pvr_WriteReg(addr,data);
}
}
//map 0x0060 to 0x0060
else if ((base ==0x0060) /*&& (addr>= 0x00600000)*/ && (addr<= 0x006007FF)) // MODEM
{
//EMUERROR4("Write to area0_32 not implemented [MODEM], addr=%x,data=%x,size=%d",addr,data,sz);
libExtDevice_WriteMem_A0_006(addr,data,sz);
}
//map 0x0060 to 0x006F
else if ((base >=0x0060) && (base <=0x006F) && (addr>= 0x00600800) && (addr<= 0x006FFFFF)) // G2 (Reserved)
{
EMUERROR4("Write to area0_32 not implemented [G2 (Reserved)], addr=%x,data=%x,size=%d",addr,data,sz);
}
//map 0x0070 to 0x0070
else if ((base >=0x0070) && (base <=0x0070) /*&& (addr>= 0x00700000)*/ && (addr<=0x00707FFF)) // AICA- Sound Cntr. Reg.
{
//EMUERROR4("Write to area0_32 not implemented [AICA- Sound Cntr. Reg], addr=%x,data=%x,size=%d",addr,data,sz);
WriteMem_aica_reg(addr,data,sz);
return;
}
//map 0x0071 to 0x0071
else if ((base >=0x0071) && (base <=0x0071) /*&& (addr>= 0x00710000)*/ && (addr<= 0x0071000B)) // AICA- RTC Cntr. Reg.
{
//EMUERROR4("Write to area0_32 not implemented [AICA- RTC Cntr. Reg], addr=%x,data=%x,size=%d",addr,data,sz);
WriteMem_aica_rtc(addr,data,sz);
return;
}
//map 0x0080 to 0x00FF
else if ((base >=0x0080) && (base <=0x00FF) /*&& (addr>= 0x00800000) && (addr<=0x00FFFFFF)*/) // AICA- Wave Memory
{
//EMUERROR4("Write to area0_32 not implemented [AICA- Wave Memory], addr=%x,data=%x,size=%d",addr,data,sz);
//aica_writeram(addr,data,sz);
WriteMemArrRet(aica_ram.data,addr&ARAM_MASK,data,sz);
return;
}
//map 0x0100 to 0x01FF
else if ((base >=0x0100) && (base <=0x01FF) /*&& (addr>= 0x01000000) && (addr<= 0x01FFFFFF)*/) // Ext. Device
{
//EMUERROR4("Write to area0_32 not implemented [Ext. Device], addr=%x,data=%x,size=%d",addr,data,sz);
libExtDevice_WriteMem_A0_010(addr,data,sz);
}
return;
}
