/* ===================================================================*/
LDD_TDeviceData* ETH1_Init(LDD_TUserData *UserDataPtr)
{
ETH1_TDeviceData *DeviceDataPrv;
ETH1_TTxQueueItem *TxQueueItemPtr;
ETH1_TRxQueueItem *RxQueueItemPtr;
uint8_t* MemPtr;
/* Allocate internal device data structure */
/* {FreeRTOS RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->DuplexMode = LDD_ETH_FULL_DUPLEX; /* Store duplex mode configuration */
DeviceDataPrv->FilterMode = LDD_ETH_ACCEPT_BC; /* Store filter mode configuration */
DeviceDataPrv->SleepMode = LDD_ETH_DISABLED; /* Store sleep mode configuration */
DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
DeviceDataPrv->Index = 0U; /* Set the component instance index */
DeviceDataPrv->EventMask = /* Initialize the event mask */
LDD_ETH_ON_FRAME_TRANSMITTED |
LDD_ETH_ON_FRAME_RECEIVED |
LDD_ETH_ON_FATAL_ERROR |0U;
DeviceDataPrv->EnabledMode = TRUE; /* Enable the device clock configuration */
/* SIM_SCGC2: ENET=1 */
SIM_SCGC2 |= SIM_SCGC2_ENET_MASK;
ENET_PDD_DisableDevice(ENET_BASE_PTR);
DeviceDataPrv->Enabled = FALSE;
ENET_PDD_EnableMIBCounters(ENET_BASE_PTR, FALSE); /* Disable statistic counters */
ENET_PDD_ClearMIBCounters(ENET_BASE_PTR); /* Clear statistic counters */
ENET_PDD_EnableMIBCounters(ENET_BASE_PTR, TRUE); /* Enable statistic counters */
/* Set pin assignments */
/* PORTB_PCR1: ISF=0,MUX=4 */
PORTB_PCR1 = (uint32_t)((PORTB_PCR1 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x03)
)) | (uint32_t)(
PORT_PCR_MUX(0x04)
));
/* PORTB_PCR0: ISF=0,MUX=4 */
PORTB_PCR0 = (uint32_t)((PORTB_PCR0 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x03)
)) | (uint32_t)(
PORT_PCR_MUX(0x04)
));
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* PORTA_PCR16: ISF=0,MUX=4 */
PORTA_PCR16 = (uint32_t)((PORTA_PCR16 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x03)
)) | (uint32_t)(
PORT_PCR_MUX(0x04)
));
/* PORTA_PCR17: ISF=0,MUX=4 */
PORTA_PCR17 = (uint32_t)((PORTA_PCR17 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x03)
)) | (uint32_t)(
PORT_PCR_MUX(0x04)
));
/* PORTA_PCR15: ISF=0,MUX=4 */
PORTA_PCR15 = (uint32_t)((PORTA_PCR15 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x03)
)) | (uint32_t)(
PORT_PCR_MUX(0x04)
));
/* PORTA_PCR14: ISF=0,MUX=4 */
PORTA_PCR14 = (uint32_t)((PORTA_PCR14 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x03)
)) | (uint32_t)(
PORT_PCR_MUX(0x04)
));
/* PORTA_PCR13: ISF=0,MUX=4 */
PORTA_PCR13 = (uint32_t)((PORTA_PCR13 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x03)
)) | (uint32_t)(
PORT_PCR_MUX(0x04)
));
/* PORTA_PCR12: ISF=0,MUX=4 */
PORTA_PCR12 = (uint32_t)((PORTA_PCR12 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x03)
)) | (uint32_t)(
PORT_PCR_MUX(0x04)
));
/* Set interrupt priorities */
/* NVICIP76: PRI76=0x80 */
NVICIP76 = NVIC_IP_PRI76(0x80);
/* NVICISER2: SETENA|=0x1000 */
NVICISER2 |= NVIC_ISER_SETENA(0x1000);
/* NVICIP77: PRI77=0x80 */
NVICIP77 = NVIC_IP_PRI77(0x80);
/* NVICISER2: SETENA|=0x2000 */
NVICISER2 |= NVIC_ISER_SETENA(0x2000);
/* NVICIP78: PRI78=0x80 */
NVICIP78 = NVIC_IP_PRI78(0x80);
/* NVICISER2: SETENA|=0x4000 */
NVICISER2 |= NVIC_ISER_SETENA(0x4000);
/* Set interrupt mask */
/* ENET_EIMR: ??=0,BABR=0,BABT=0,GRA=0,TXF=1,TXB=0,RXF=1,RXB=0,MII=0,EBERR=1,LC=0,RL=0,UN=0,PLR=0,WAKEUP=0,TS_AVAIL=0,TS_TIMER=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
ENET_EIMR = (ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK);
/* Clear interrupt flags */
/* ENET_EIR: ??=1,BABR=1,BABT=1,GRA=1,TXF=1,TXB=1,RXF=1,RXB=1,MII=1,EBERR=1,LC=1,RL=1,UN=1,PLR=0,WAKEUP=0,TS_AVAIL=0,TS_TIMER=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
ENET_EIR = ENET_EIR_BABR_MASK |
ENET_EIR_BABT_MASK |
ENET_EIR_GRA_MASK |
ENET_EIR_TXF_MASK |
ENET_EIR_TXB_MASK |
ENET_EIR_RXF_MASK |
ENET_EIR_RXB_MASK |
ENET_EIR_MII_MASK |
ENET_EIR_EBERR_MASK |
ENET_EIR_LC_MASK |
ENET_EIR_RL_MASK |
ENET_EIR_UN_MASK |
0x80000000U;
/* Allocate the transmit frame interrupt vector */
/* {FreeRTOS RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_ENET_Transmit__BAREBOARD_RTOS_ISRPARAM = DeviceDataPrv;
/* Allocate the receive frame interrupt vector */
/* {FreeRTOS RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_ENET_Receive__BAREBOARD_RTOS_ISRPARAM = DeviceDataPrv;
/* Allocate the shared interrupt vector */
/* {FreeRTOS RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_ENET_Error__BAREBOARD_RTOS_ISRPARAM = DeviceDataPrv;
/* Set MAC address */
/* ENET_PALR: PADDR1=0x43EF783A */
ENET_PALR = ENET_PALR_PADDR1(0x43EF783A);
/* ENET_PAUR: PADDR2=0x2E19,TYPE=0 */
ENET_PAUR = (ENET_PAUR_PADDR2(0x2E19) | ENET_PAUR_TYPE(0x00));
/* Set unicast address hash table */
/* ENET_IAUR: IADDR1=0 */
ENET_IAUR = ENET_IAUR_IADDR1(0x00);
/* ENET_IALR: IADDR2=0 */
ENET_IALR = ENET_IALR_IADDR2(0x00);
/* Set multicast address hash table */
/* ENET_GAUR: GADDR1=0 */
ENET_GAUR = ENET_GAUR_GADDR1(0x00);
/* ENET_GALR: GADDR2=0 */
ENET_GALR = ENET_GALR_GADDR2(0x00);
/* Set PAUSE frame duration */
/* ENET_OPD: OPCODE=0,PAUSE_DUR=0 */
ENET_OPD = (ENET_OPD_OPCODE(0x00) | ENET_OPD_PAUSE_DUR(0x00));
/* Set transmit control register */
/* ENET_TCR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CRCFWD=0,ADDINS=0,ADDSEL=0,RFC_PAUSE=0,TFC_PAUSE=0,FDEN=1,??=0,GTS=0 */
ENET_TCR = (ENET_TCR_ADDSEL(0x00) | ENET_TCR_FDEN_MASK);
/* Set transmit accelerator function configuration register */
/* ENET_TACC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,PROCHK=0,IPCHK=0,??=0,??=0,SHIFT16=0 */
ENET_TACC = 0x00U;
/* Set receive control register */
/* ENET_RCR: GRS=0,NLC=0,MAX_FL=0x05EE,CFEN=0,CRCFWD=0,PAUFWD=1,PADEN=0,??=0,??=0,RMII_10T=0,RMII_MODE=1,??=0,??=0,FCE=1,BC_REJ=0,PROM=0,MII_MODE=1,DRT=0,LOOP=0 */
ENET_RCR = ENET_RCR_MAX_FL(0x05EE) |
ENET_RCR_PAUFWD_MASK |
ENET_RCR_RMII_MODE_MASK |
ENET_RCR_FCE_MASK |
ENET_RCR_MII_MODE_MASK;
/* Set receive accelerator function configuration register */
/* ENET_RACC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,SHIFT16=0,LINEDIS=0,??=0,??=0,??=0,PRODIS=0,IPDIS=0,PADREM=0 */
ENET_RACC = 0x00U;
/* Set transmit inter-packet gap */
/* ENET_TIPG: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,IPG=8 */
ENET_TIPG = ENET_TIPG_IPG(0x08);
/* Set frame truncation length */
/* ENET_FTRL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TRUNC_FL=0x0800 */
ENET_FTRL = ENET_FTRL_TRUNC_FL(0x0800);
/* Set transmit FIFO watermark */
/* ENET_TFWR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,STRFWD=1,??=0,??=0,TFWR=0 */
ENET_TFWR = (ENET_TFWR_STRFWD_MASK | ENET_TFWR_TFWR(0x00));
/* Set transmit FIFO section empty threshold */
/* ENET_TSEM: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TX_SECTION_EMPTY=0 */
ENET_TSEM = ENET_TSEM_TX_SECTION_EMPTY(0x00);
/* Set transmit FIFO almost empty threshold */
/* ENET_TAEM: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TX_ALMOST_EMPTY=8 */
ENET_TAEM = ENET_TAEM_TX_ALMOST_EMPTY(0x08);
/* Set transmit FIFO almost full threshold */
/* ENET_TAFL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TX_ALMOST_FULL=8 */
ENET_TAFL = ENET_TAFL_TX_ALMOST_FULL(0x08);
/* Set receive FIFO section full threshold */
/* ENET_RSFL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,RX_SECTION_FULL=0 */
ENET_RSFL = ENET_RSFL_RX_SECTION_FULL(0x00);
/* Set receive FIFO section empty threshold */
/* ENET_RSEM: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,RX_SECTION_EMPTY=0 */
ENET_RSEM = ENET_RSEM_RX_SECTION_EMPTY(0x00);
/* Set receive FIFO almost empty threshold */
/* ENET_RAEM: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,RX_ALMOST_EMPTY=8 */
ENET_RAEM = ENET_RAEM_RX_ALMOST_EMPTY(0x08);
/* Set receive FIFO almost full threshold */
/* ENET_RAFL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,RX_ALMOST_FULL=8 */
ENET_RAFL = ENET_RAFL_RX_ALMOST_FULL(0x08);
/* Set MII speed control register */
/* ENET_MSCR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HOLDTIME=7,DIS_PRE=1,MII_SPEED=3,??=0 */
ENET_MSCR = ENET_MSCR_HOLDTIME(0x07) |
ENET_MSCR_DIS_PRE_MASK |
ENET_MSCR_MII_SPEED(0x03);
/* Set receive buffer size */
/* ENET_MRBR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,R_BUF_SIZE=0,??=0,??=0,??=0,??=0 */
ENET_MRBR = ENET_MRBR_R_BUF_SIZE(0x00);
/* Initialize the transmit frame buffer queue */
LDD_QUEUE_INIT(ETH1_TTxQueueItem, DeviceDataPrv->TxQueue, ETH1_QUEUE_MEM_ALIGN); /* Initialize the queue data structure */
TxQueueItemPtr = LDD_QUEUE_GET_DATA_START(DeviceDataPrv->TxQueue);
while (TxQueueItemPtr != (LDD_QUEUE_GET_DATA_END(DeviceDataPrv->TxQueue) + 1)) {
/* Clear queue item */
for (MemPtr = (uint8_t*)(uint32_t)TxQueueItemPtr; MemPtr != (uint8_t*)(uint32_t)(TxQueueItemPtr + 1); MemPtr++) {
*MemPtr = 0U;
}
TxQueueItemPtr++; /* Move to the next queue item */
}
setReg32(ENET_TDSR, LDD_QUEUE_GET_DATA_START(DeviceDataPrv->TxQueue));
/* Initialize the receive frame buffer queue */
LDD_QUEUE_INIT(ETH1_TRxQueueItem, DeviceDataPrv->RxQueue, ETH1_QUEUE_MEM_ALIGN); /* Initialize the queue data structure */
RxQueueItemPtr = LDD_QUEUE_GET_DATA_START(DeviceDataPrv->RxQueue);
while (RxQueueItemPtr != (LDD_QUEUE_GET_DATA_END(DeviceDataPrv->RxQueue) + 1)) {
/* Clear queue item */
for (MemPtr = (uint8_t*)(uint32_t)RxQueueItemPtr; MemPtr != (uint8_t*)(uint32_t)(RxQueueItemPtr + 1); MemPtr++) {
*MemPtr = 0U;
}
RxQueueItemPtr++; /* Move to the next queue item */
}
setReg32(ENET_RDSR, LDD_QUEUE_GET_DATA_START(DeviceDataPrv->RxQueue));
/* ENET_ECR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DBSWP=0,STOPEN=0,DBGEN=0,??=0,EN1588=0,SLEEP=0,MAGICEN=0,ETHEREN=0,RESET=0 */
ENET_ECR = 0x00U;
/* Enable the device */
ENET_PDD_EnableDevice(ENET_BASE_PTR);
DeviceDataPrv->Enabled = TRUE;
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ETH1_ID,DeviceDataPrv);
return (LDD_TDeviceData*)DeviceDataPrv;
}
/*
* \brief Initialize the MII interface controller
* \param System Clock Frequency (in MHz)
* \warning The system clock in this case is the clock that drives
* the FEC logic. This may be different from the speed at which
* the CPU is operating.
*
* Initialize the MII clock (EMDC) frequency. The desired MII clock is 2.5MHz:
*
* MII Speed Setting = System_Clock / (2.5MHz * 2)
* (plus 1 to round up)
*/
void mii_init(uint32_t clk) {
ENET_MSCR = ENET_MSCR_MII_SPEED((2 * clk / 5) + 1);
}
