void EP_Reset (U32 EPNum) {
U32 num, val;
num = EPNum & 0x0F;
val = EPxREG(num);
if (EPNum & 0x80) { /* IN Endpoint */
EPxREG(num) = val & (EP_MASK | EP_DTOG_TX);
} else { /* OUT Endpoint */
EPxREG(num) = val & (EP_MASK | EP_DTOG_RX);
}
}
void EP_Status (U32 EPNum, U32 stat) {
U32 num, val;
num = EPNum & 0x0F;
val = EPxREG(num);
if (EPNum & 0x80) { /* IN Endpoint */
EPxREG(num) = (val ^ (stat & EP_STAT_TX)) & (EP_MASK | EP_STAT_TX);
} else { /* OUT Endpoint */
EPxREG(num) = (val ^ (stat & EP_STAT_RX)) & (EP_MASK | EP_STAT_RX);
}
}
void USB_Reset (void) {
/* Double Buffering is not yet supported */
ISTR = 0; /* Clear Interrupt Status */
CNTR = CNTR_CTRM | CNTR_RESETM | CNTR_SUSPM | CNTR_WKUPM |
(USB_ERROR_EVENT ? CNTR_ERRM : 0) |
(USB_ERROR_EVENT ? CNTR_PMAOVRM : 0) |
(USB_SOF_EVENT ? CNTR_SOFM : 0) |
(USB_SOF_EVENT ? CNTR_ESOFM : 0);
FreeBufAddr = EP_BUF_ADDR;
BTABLE = 0x00; /* set BTABLE Address */
/* Setup Control Endpoint 0 */
pBUF_DSCR->ADDR_TX = FreeBufAddr;
FreeBufAddr += USB_MAX_PACKET0;
pBUF_DSCR->ADDR_RX = FreeBufAddr;
FreeBufAddr += USB_MAX_PACKET0;
if (USB_MAX_PACKET0 > 62) {
pBUF_DSCR->COUNT_RX = ((USB_MAX_PACKET0 << 5) - 1) | 0x8000;
} else {
pBUF_DSCR->COUNT_RX = USB_MAX_PACKET0 << 9;
}
EPxREG(0) = EP_CONTROL | EP_RX_VALID;
DADDR = DADDR_EF | 0; /* Enable USB Default Address */
}
void
CmtUsbDev::USB_Reset() {
ISTR = 0; /* Clear Interrupt Status */
CNTR = CNTR_CTRM | CNTR_RESETM |
(USB_SUSPEND_EVENT ? CNTR_SUSPM : 0) |
(USB_WAKEUP_EVENT ? CNTR_WKUPM : 0) |
(USB_ERROR_EVENT ? CNTR_ERRM : 0) |
(USB_ERROR_EVENT ? CNTR_PMAOVRM : 0) |
(USB_SOF_EVENT ? CNTR_SOFM : 0) |
(USB_SOF_EVENT ? CNTR_ESOFM : 0);
FreeBufAddr = EP_BUF_ADDR;
BTABLE = 0x00; /* set BTABLE Address */
/* Setup Control Endpoint 0 */
pBUF_DSCR->ADDR_TX = FreeBufAddr;
FreeBufAddr += USB_MAX_PACKET0;
pBUF_DSCR->ADDR_RX = FreeBufAddr;
FreeBufAddr += USB_MAX_PACKET0;
if (USB_MAX_PACKET0 > 62) {
pBUF_DSCR->COUNT_RX = ((USB_MAX_PACKET0 << 5) - 1) | 0x8000;
}
else {
pBUF_DSCR->COUNT_RX = USB_MAX_PACKET0 << 9;
}
EPxREG(0) = EP_CONTROL | EP_RX_VALID;
DADDR = DADDR_EF | 0; /* Enable USB Default Address */
USB_ResetCore();
}
void
CmtUsbDev::USB_ConfigEP( USB_ENDPOINT_DESCRIPTOR *pEPD ) {
/* Double Buffering is not yet supported */
uint32 num, val;
num = pEPD->bEndpointAddress & 0x0F;
val = pEPD->wMaxPacketSize;
if( pEPD->bEndpointAddress & USB_ENDPOINT_DIRECTION_MASK ) {
(pBUF_DSCR + num)->ADDR_TX = FreeBufAddr;
val = (val + 1) & ~1;
}
else {
(pBUF_DSCR + num)->ADDR_RX = FreeBufAddr;
if(val > 62) {
val = (val + 31) & ~31;
(pBUF_DSCR + num)->COUNT_RX = ((val << 5) - 1) | 0x8000;
}
else {
val = (val + 1) & ~1;
(pBUF_DSCR + num)->COUNT_RX = val << 9;
}
}
FreeBufAddr += val;
switch (pEPD->bmAttributes & USB_ENDPOINT_TYPE_MASK) {
case USB_ENDPOINT_TYPE_CONTROL:
val = EP_CONTROL;
break;
case USB_ENDPOINT_TYPE_ISOCHRONOUS:
val = EP_ISOCHRONOUS;
break;
case USB_ENDPOINT_TYPE_BULK:
val = EP_BULK;
if( USB_DBL_BUF_EP & (1 << num) ) {
val |= EP_KIND;
}
break;
case USB_ENDPOINT_TYPE_INTERRUPT:
val = EP_INTERRUPT;
break;
}
val |= num;
EPxREG(num) = val;
}
U32 USB_WriteEP (U32 EPNum, U8 *pData, U32 cnt) {
/* Double Buffering is not yet supported */
U32 num, *pv, n;
U16 statusEP;
num = EPNum & 0x0F;
pv = (U32 *)(USB_PMA_ADDR + 2*((pBUF_DSCR + num)->ADDR_TX));
for (n = 0; n < (cnt + 1) / 2; n++) {
*pv++ = *((__packed U16 *)pData);
pData += 2;
}
(pBUF_DSCR + num)->COUNT_TX = cnt;
statusEP = EPxREG(num);
if ((statusEP & EP_STAT_TX) != EP_TX_STALL) {
EP_Status(EPNum, EP_TX_VALID); /* do not make EP valid if it is stalled previously */
}
return (cnt);
}
void USB_LP_IRQHandler (void) {
U32 istr, num, val;
istr = ISTR;
/* USB Reset Request */
if (istr & ISTR_RESET) {
USB_Reset();
#if USB_RESET_EVENT
USB_Reset_Event();
#endif
ISTR = ~ISTR_RESET;
}
/* USB Suspend Request */
if (istr & ISTR_SUSP) {
USB_Suspend();
#if USB_SUSPEND_EVENT
USB_Suspend_Event();
#endif
ISTR = ~ISTR_SUSP;
}
/* USB Wakeup */
if (istr & ISTR_WKUP) {
USB_WakeUp();
#if USB_RESUME_EVENT
USB_Resume_Event();
#endif
ISTR = ~ISTR_WKUP;
}
/* Start of Frame */
if (istr & ISTR_SOF) {
#if USB_SOF_EVENT
USB_SOF_Event();
#endif
ISTR = ~ISTR_SOF;
}
#if USB_ERROR_EVENT
/* PMA Over/underrun */
if (istr & ISTR_PMAOVR) {
USB_Error_Event(1);
ISTR = ~ISTR_PMAOVR;
}
/* Error: No Answer, CRC Error, Bit Stuff Error, Frame Format Error */
if (istr & ISTR_ERR) {
USB_Error_Event(0);
ISTR = ~ISTR_ERR;
}
#endif
/* Endpoint Interrupts */
while ((istr = ISTR) & ISTR_CTR) {
ISTR = ~ISTR_CTR;
num = istr & ISTR_EP_ID;
val = EPxREG(num);
if (val & EP_CTR_RX) {
EPxREG(num) = val & ~EP_CTR_RX & EP_MASK;
if (USB_P_EP[num]) {
if (val & EP_SETUP) {
USB_P_EP[num](USB_EVT_SETUP);
} else {
USB_P_EP[num](USB_EVT_OUT);
}
}
}
if (val & EP_CTR_TX) {
EPxREG(num) = val & ~EP_CTR_TX & EP_MASK;
if (USB_P_EP[num]) {
USB_P_EP[num](USB_EVT_IN);
}
}
}
}
void USB_LP_CAN1_RX0_IRQHandler(void) {
U32 istr, num, val;
istr = ISTR;
/* USB Reset Request */
if (istr & ISTR_RESET) {
USBD_Reset();
usbd_reset_core();
#ifdef __RTX
if (USBD_RTX_DevTask) {
isr_evt_set(USBD_EVT_RESET, USBD_RTX_DevTask);
}
#else
if (USBD_P_Reset_Event) {
USBD_P_Reset_Event();
}
#endif
ISTR = ~ISTR_RESET;
}
/* USB Suspend Request */
if (istr & ISTR_SUSP) {
USBD_Suspend();
#ifdef __RTX
if (USBD_RTX_DevTask) {
isr_evt_set(USBD_EVT_SUSPEND, USBD_RTX_DevTask);
}
#else
if (USBD_P_Suspend_Event) {
USBD_P_Suspend_Event();
}
#endif
ISTR = ~ISTR_SUSP;
}
/* USB Wakeup */
if (istr & ISTR_WKUP) {
USBD_WakeUp();
#ifdef __RTX
if (USBD_RTX_DevTask) {
isr_evt_set(USBD_EVT_RESUME, USBD_RTX_DevTask);
}
#else
if (USBD_P_Resume_Event) {
USBD_P_Resume_Event();
}
#endif
ISTR = ~ISTR_WKUP;
}
/* Start of Frame */
if (istr & ISTR_SOF) {
#ifdef __RTX
if (USBD_RTX_DevTask) {
isr_evt_set(USBD_EVT_SOF, USBD_RTX_DevTask);
}
#else
if (USBD_P_SOF_Event) {
USBD_P_SOF_Event();
}
#endif
ISTR = ~ISTR_SOF;
}
/* PMA Over/underrun */
if (istr & ISTR_PMAOVR) {
#ifdef __RTX
LastError = 2;
if (USBD_RTX_DevTask) {
isr_evt_set(USBD_EVT_ERROR, USBD_RTX_DevTask);
}
#else
if (USBD_P_Error_Event) {
USBD_P_Error_Event(2);
}
#endif
ISTR = ~ISTR_PMAOVR;
}
/* Error: No Answer, CRC Error, Bit Stuff Error, Frame Format Error */
if (istr & ISTR_ERR) {
#ifdef __RTX
LastError = 1;
if (USBD_RTX_DevTask) {
isr_evt_set(USBD_EVT_ERROR, USBD_RTX_DevTask);
}
#else
if (USBD_P_Error_Event) {
USBD_P_Error_Event(1);
}
#endif
ISTR = ~ISTR_ERR;
}
/* Endpoint Interrupts */
while ((istr = ISTR) & ISTR_CTR) {
ISTR = ~ISTR_CTR;
num = istr & ISTR_EP_ID;
val = EPxREG(num);
if (val & EP_CTR_RX) {
EPxREG(num) = val & ~EP_CTR_RX & EP_MASK;
#ifdef __RTX
if (USBD_RTX_EPTask[num]) {
isr_evt_set((val & EP_SETUP) ? USBD_EVT_SETUP : USBD_EVT_OUT, USBD_RTX_EPTask[num]);
}
#else
if (USBD_P_EP[num]) {
USBD_P_EP[num]((val & EP_SETUP) ? USBD_EVT_SETUP : USBD_EVT_OUT);
}
#endif
}
if (val & EP_CTR_TX) {
EPxREG(num) = val & ~EP_CTR_TX & EP_MASK;
#ifdef __RTX
if (USBD_RTX_EPTask[num]) {
isr_evt_set(USBD_EVT_IN, USBD_RTX_EPTask[num]);
}
#else
if (USBD_P_EP[num]) {
USBD_P_EP[num](USBD_EVT_IN);
}
#endif
}
}
}
void
CmtUsbDev::IrqHandler() {
uint32 istr, num, val;
istr = ISTR;
/* USB Reset Request */
if (istr & ISTR_RESET) {
USB_Reset();
ISTR = ~ISTR_RESET;
}
/* USB Suspend Request */
if (istr & ISTR_SUSP) {
USB_Suspend();
ISTR = ~ISTR_SUSP;
}
/* USB Wakeup */
if (istr & ISTR_WKUP) {
USB_WakeUp();
ISTR = ~ISTR_WKUP;
}
/* Start of Frame */
if (istr & ISTR_SOF) {
USB_StartOfFrame();
ISTR = ~ISTR_SOF;
}
/* PMA Over/underrun */
if (istr & ISTR_PMAOVR) {
USB_Error(1);
ISTR = ~ISTR_PMAOVR;
}
/* Error: No Answer, CRC Error, Bit Stuff Error, Frame Format Error */
if (istr & ISTR_ERR) {
USB_Error(0);
ISTR = ~ISTR_ERR;
}
/* Endpoint Interrupts */
while( (istr = ISTR) & ISTR_CTR) {
ISTR = ~ISTR_CTR;
num = istr & ISTR_EP_ID;
val = EPxREG(num);
if (val & EP_CTR_RX) {
EPxREG(num) = val & ~EP_CTR_RX & EP_MASK;
switch( num ) {
case 0 : EndPoint0( val & EP_SETUP ? USB_EVT_SETUP : USB_EVT_OUT ); break;
case 1 : EndPoint1( USB_EVT_OUT ); break;
case 2 : EndPoint2( USB_EVT_OUT ); break;
case 3 : EndPoint3( USB_EVT_OUT ); break;
case 4 : EndPoint4( USB_EVT_OUT ); break;
case 5 : EndPoint5( USB_EVT_OUT ); break;
case 6 : EndPoint6( USB_EVT_OUT ); break;
case 7 : EndPoint7( USB_EVT_OUT ); break;
case 8 : EndPoint8( USB_EVT_OUT ); break;
case 9 : EndPoint9( USB_EVT_OUT ); break;
case 10 : EndPoint10( USB_EVT_OUT ); break;
case 11 : EndPoint11( USB_EVT_OUT ); break;
case 12 : EndPoint12( USB_EVT_OUT ); break;
case 13 : EndPoint13( USB_EVT_OUT ); break;
case 14 : EndPoint14( USB_EVT_OUT ); break;
case 15 : EndPoint15( USB_EVT_OUT ); break;
}
}
if (val & EP_CTR_TX) {
EPxREG(num) = val & ~EP_CTR_TX & EP_MASK;
switch( num ) {
case 0 : EndPoint0( USB_EVT_IN ); break;
case 1 : EndPoint1( USB_EVT_IN ); break;
case 2 : EndPoint2( USB_EVT_IN ); break;
case 3 : EndPoint3( USB_EVT_IN ); break;
case 4 : EndPoint4( USB_EVT_IN ); break;
case 5 : EndPoint5( USB_EVT_IN ); break;
case 6 : EndPoint6( USB_EVT_IN ); break;
case 7 : EndPoint7( USB_EVT_IN ); break;
case 8 : EndPoint8( USB_EVT_IN ); break;
case 9 : EndPoint9( USB_EVT_IN ); break;
case 10 : EndPoint10( USB_EVT_IN ); break;
case 11 : EndPoint11( USB_EVT_IN ); break;
case 12 : EndPoint12( USB_EVT_IN ); break;
case 13 : EndPoint13( USB_EVT_IN ); break;
case 14 : EndPoint14( USB_EVT_IN ); break;
case 15 : EndPoint15( USB_EVT_IN ); break;
}
}
}
}