static void __inline
disable_16(struct ata_avila_softc *sc)
{
DELAY(100); /* XXX? */
EXP_BUS_WRITE_4(sc, sc->sc_16bit_off,
EXP_BUS_READ_4(sc, sc->sc_16bit_off) | EXP_BYTE_EN);
}
static int
ata_avila_probe(device_t dev)
{
struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
/* XXX any way to check? */
if (EXP_BUS_READ_4(sa, EXP_TIMING_CS2_OFFSET) != 0)
device_set_desc_copy(dev, "Gateworks Avila IDE/CF Controller");
else
device_set_desc_copy(dev,
"ADI Pronghorn Metro IDE/CF Controller");
return 0;
}
static int
cfi_ixp4xx_probe(device_t dev)
{
struct cfi_softc *sc = device_get_softc(dev);
/*
* NB: we assume the boot loader sets up EXP_TIMING_CS0_OFFSET
* according to the flash on the board. If it does not then it
* can be done here.
*/
if (bootverbose) {
struct ixp425_softc *sa =
device_get_softc(device_get_parent(dev));
device_printf(dev, "EXP_TIMING_CS0_OFFSET 0x%x\n",
EXP_BUS_READ_4(sa, EXP_TIMING_CS0_OFFSET));
}
sc->sc_width = 2; /* NB: don't probe interface width */
return cfi_probe(dev);
}
void
cambria_exp_bus_init(struct ixp425_softc *sc)
{
static struct expbus_softc c3; /* NB: no need to malloc */
uint32_t cs3;
KASSERT(cpu_is_ixp43x(), ("wrong cpu type"));
c3.sc = sc;
c3.csoff = EXP_TIMING_CS3_OFFSET;
EXP_LOCK_INIT(&c3);
cambria_exp_bs_tag.bs_cookie = &c3;
cs3 = EXP_BUS_READ_4(sc, EXP_TIMING_CS3_OFFSET);
/* XXX force slowest possible timings and byte mode */
EXP_BUS_WRITE_4(sc, EXP_TIMING_CS3_OFFSET,
cs3 | (EXP_T1|EXP_T2|EXP_T3|EXP_T4|EXP_T5) |
EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
/* XXX force GPIO 3+4 for GPS+RS485 uarts */
ixp425_set_gpio(sc, 3, GPIO_TYPE_EDG_RISING);
ixp425_set_gpio(sc, 4, GPIO_TYPE_EDG_RISING);
}
static __inline void
disable_16(struct ixp425_softc *sc, bus_size_t cs)
{
EXP_BUS_WRITE_4(sc, cs, EXP_BUS_READ_4(sc, cs) | EXP_BYTE_EN);
}
static int
ata_avila_attach(device_t dev)
{
struct ata_avila_softc *sc = device_get_softc(dev);
struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
u_int32_t alt_t_off, ide_gpin, ide_irq;
sc->sc_dev = dev;
/* NB: borrow from parent */
sc->sc_iot = sa->sc_iot;
sc->sc_exp_ioh = sa->sc_exp_ioh;
if (EXP_BUS_READ_4(sc, EXP_TIMING_CS2_OFFSET) != 0) {
/* Avila board */
if (bus_space_map(sc->sc_iot, IXP425_EXP_BUS_CS1_HWBASE,
IXP425_EXP_BUS_CS1_SIZE, 0, &sc->sc_ioh))
panic("%s: unable to map Expansion Bus CS1 window",
__func__);
if (bus_space_map(sc->sc_iot, IXP425_EXP_BUS_CS2_HWBASE,
IXP425_EXP_BUS_CS2_SIZE, 0, &sc->sc_alt_ioh))
panic("%s: unable to map Expansion Bus CS2 window",
__func__);
ide_gpin = AVILA_IDE_GPIN;
ide_irq = AVILA_IDE_IRQ;
sc->sc_16bit_off = EXP_TIMING_CS1_OFFSET;
alt_t_off = EXP_TIMING_CS2_OFFSET;
} else {
/* Pronghorn */
if (bus_space_map(sc->sc_iot, IXP425_EXP_BUS_CS3_HWBASE,
IXP425_EXP_BUS_CS3_SIZE, 0, &sc->sc_ioh))
panic("%s: unable to map Expansion Bus CS3 window",
__func__);
if (bus_space_map(sc->sc_iot, IXP425_EXP_BUS_CS4_HWBASE,
IXP425_EXP_BUS_CS4_SIZE, 0, &sc->sc_alt_ioh))
panic("%s: unable to map Expansion Bus CS4 window",
__func__);
ide_gpin = PRONGHORN_IDE_GPIN;
ide_irq = PRONGHORN_IDE_IRQ;
sc->sc_16bit_off = EXP_TIMING_CS3_OFFSET;
alt_t_off = EXP_TIMING_CS4_OFFSET;
}
/*
* Craft special resource for ATA bus space ops
* that go through the expansion bus and require
* special hackery to ena/dis 16-bit operations.
*
* XXX probably should just make this generic for
* accessing the expansion bus.
*/
sc->sc_expbus_tag.bs_cookie = sc; /* NB: backpointer */
/* read single */
sc->sc_expbus_tag.bs_r_1 = ata_bs_r_1,
sc->sc_expbus_tag.bs_r_2 = ata_bs_r_2,
/* read multiple */
sc->sc_expbus_tag.bs_rm_2 = ata_bs_rm_2,
sc->sc_expbus_tag.bs_rm_2_s = ata_bs_rm_2_s,
/* write (single) */
sc->sc_expbus_tag.bs_w_1 = ata_bs_w_1,
sc->sc_expbus_tag.bs_w_2 = ata_bs_w_2,
/* write multiple */
sc->sc_expbus_tag.bs_wm_2 = ata_bs_wm_2,
sc->sc_expbus_tag.bs_wm_2_s = ata_bs_wm_2_s,
rman_set_bustag(&sc->sc_ata, &sc->sc_expbus_tag);
rman_set_bushandle(&sc->sc_ata, sc->sc_ioh);
rman_set_bustag(&sc->sc_alt_ata, &sc->sc_expbus_tag);
rman_set_bushandle(&sc->sc_alt_ata, sc->sc_alt_ioh);
GPIO_CONF_WRITE_4(sa, IXP425_GPIO_GPOER,
GPIO_CONF_READ_4(sa, IXP425_GPIO_GPOER) | (1<<ide_gpin));
/* set interrupt type */
GPIO_CONF_WRITE_4(sa, GPIO_TYPE_REG(ide_gpin),
(GPIO_CONF_READ_4(sa, GPIO_TYPE_REG(ide_gpin)) &~
GPIO_TYPE(ide_gpin, GPIO_TYPE_MASK)) |
GPIO_TYPE(ide_gpin, GPIO_TYPE_EDG_RISING));
/* clear ISR */
GPIO_CONF_WRITE_4(sa, IXP425_GPIO_GPISR, (1<<ide_gpin));
/* configure CS1/3 window, leaving timing unchanged */
EXP_BUS_WRITE_4(sc, sc->sc_16bit_off,
EXP_BUS_READ_4(sc, sc->sc_16bit_off) |
EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
/* configure CS2/4 window, leaving timing unchanged */
EXP_BUS_WRITE_4(sc, alt_t_off,
EXP_BUS_READ_4(sc, alt_t_off) |
EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
/* setup interrupt */
sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->sc_rid,
ide_irq, ide_irq, 1, RF_ACTIVE);
if (!sc->sc_irq)
panic("Unable to allocate irq %u.\n", ide_irq);
bus_setup_intr(dev, sc->sc_irq,
INTR_TYPE_BIO | INTR_MPSAFE | INTR_ENTROPY,
NULL, ata_avila_intr, sc, &sc->sc_ih);
/* attach channel on this controller */
device_add_child(dev, "ata", devclass_find_free_unit(ata_devclass, 0));
bus_generic_attach(dev);
return 0;
}