void map_init_Bandai(BYTE model) {
chr_ram_4k_max = info.chr.rom[0].banks_4k - 1;
switch (model) {
case B161X02X74:
EXTCL_CPU_WR_MEM(Bandai_161x02x74);
EXTCL_SAVE_MAPPER(Bandai_161x02x74);
EXTCL_UPDATE_R2006(Bandai_161x02x74);
EXTCL_RD_NMT(Bandai_161x02x74);
mapper.internal_struct[0] = (BYTE *) &b161x02x74;
mapper.internal_struct_size[0] = sizeof(b161x02x74);
if (info.reset >= HARD) {
b161x02x74.chr_rom_bank = 0;
map_prg_rom_8k(4, 0, 0);
{
BYTE value, save = 0;
DBWORD bank;
b161x02x74_chr_4k_update();
}
}
break;
case FCGx:
case E24C01:
case E24C02:
case DATACH: {
EXTCL_CPU_WR_MEM(Bandai_FCGX);
EXTCL_CPU_RD_MEM(Bandai_FCGX);
EXTCL_SAVE_MAPPER(Bandai_FCGX);
EXTCL_BATTERY_IO(Bandai_FCGX);
EXTCL_CPU_EVERY_CYCLE(Bandai_FCGX);
mapper.internal_struct[0] = (BYTE *) &FCGX;
mapper.internal_struct_size[0] = sizeof(FCGX);
info.mapper.extend_wr = TRUE;
if (info.reset >= HARD) {
memset(&FCGX, 0x00, sizeof(FCGX));
FCGX.e0.output = FCGX.e1.output = 0x10;
if (info.prg.rom[0].banks_16k >= 32) {
map_prg_rom_8k(2, 2, info.prg.rom[0].max.banks_16k);
}
} else {
BYTE i;
for (i = 0; i < 8; i++) {
FCGX.reg[i] = 0;
}
}
switch (model) {
case E24C01:
info.prg.ram.bat.banks = TRUE;
FCGX.e0.size = 128;
break;
case E24C02:
info.prg.ram.bat.banks = TRUE;
FCGX.e0.size = 256;
break;
case DATACH:
info.prg.ram.bat.banks = TRUE;
FCGX.e0.size = 256;
FCGX.e1.size = 128;
break;
}
break;
}
}
switch (info.id) {
case FAMICOMJUMPII:
info.prg.ram.banks_8k_plus = 1;
info.prg.ram.bat.banks = 1;
break;
}
type = model;
}
void map_init_MMC5(void) {
EXTCL_CPU_WR_MEM(MMC5);
EXTCL_CPU_RD_MEM(MMC5);
EXTCL_SAVE_MAPPER(MMC5);
EXTCL_PPU_256_TO_319(MMC5);
EXTCL_PPU_320_TO_34X(MMC5);
EXTCL_AFTER_RD_CHR(MMC5);
EXTCL_RD_NMT(MMC5);
EXTCL_RD_CHR(MMC5);
EXTCL_LENGTH_CLOCK(MMC5);
EXTCL_ENVELOPE_CLOCK(MMC5);
EXTCL_APU_TICK(MMC5);
mapper.internal_struct[0] = (BYTE *) &mmc5;
mapper.internal_struct_size[0] = sizeof(mmc5);
if (info.reset >= HARD) {
BYTE i;
memset(&mmc5, 0x00, sizeof(mmc5));
memset(&irql2f, 0x00, sizeof(irql2f));
mmc5.prg_mode = MODE3;
mmc5.chr_mode = MODE0;
mmc5.ext_mode = MODE0;
mmc5.chr_last = CHR_S;
mmc5.S3.frequency = 1;
mmc5.S4.frequency = 1;
irql2f.scanline = 255;
irql2f.frame_x = 339;
for (i = 0; i < 4; ++i) {
mmc5.prg_bank[i] = 0xFF;
}
for (i = 0; i < 8; ++i) {
mmc5.chr_s[i] = i;
}
for (i = 0; i < 4; ++i) {
mmc5.chr_b[i] = i;
}
use_chr_s();
} else {
mmc5.S3.length.enabled = 0;
mmc5.S3.length.value = 0;
mmc5.S4.length.enabled = 0;
mmc5.S4.length.value = 0;
}
info.mapper.extend_wr = TRUE;
irql2f.present = TRUE;
switch (info.mapper.submapper) {
case EKROM:
info.prg.ram.banks_8k_plus = 1;
info.prg.ram.bat.banks = 1;
prg_ram_mode = PRG_RAM_8K;
break;
case ELROM:
default:
info.prg.ram.banks_8k_plus = FALSE;
info.prg.ram.bat.banks = FALSE;
prg_ram_mode = PRG_RAM_NONE;
break;
case ETROM:
info.prg.ram.banks_8k_plus = 2;
info.prg.ram.bat.banks = 1;
info.prg.ram.bat.start = 0;
prg_ram_mode = PRG_RAM_16K;
break;
case EWROM:
info.prg.ram.banks_8k_plus = 4;
info.prg.ram.bat.banks = 4;
prg_ram_mode = PRG_RAM_32K;
break;
}
}
