void TWRK40_flexbus_init(void){
/* Enable the FlexBus */
/* Configure the FlexBus Registers for 8-bit port size */
/* with multiplexed address and data using chip select 0 */
/* These configurations are specific to communicating with */
/* the MRAM used in this example */
/* For K40 tower module - use the byte lane shift because there */
/* is a latch on the board which handles multiplexed address/data */
//Set Base address
FB_CSAR0 = (uint32)&MRAM_START_ADDRESS;
FB_CSCR0 = FB_CSCR_BLS_MASK // set byte lane shift for data on FB_AD[7:0] aka. right justified mode
| FB_CSCR_PS(1) // 8-bit port
| FB_CSCR_AA_MASK // auto-acknowledge
| FB_CSCR_ASET(0x1) // assert chip select on second clock edge after address is asserted
| FB_CSCR_WS(0x1) // 1 wait state - may need a wait state depending on the bus speed
;
FB_CSMR0 = FB_CSMR_BAM(0x7) //Set base address mask for 512K address space
| FB_CSMR_V_MASK //Enable cs signal
;
//enable BE signals - note, not used in this example
FB_CSPMCR = 0x02200000;
//fb clock divider 3
SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV3(0x3);
/* Configure the pins needed to FlexBus Function (Alt 5) */
/* this example uses low drive strength settings */
//address/Data
PORTA_PCR7=PORT_PCR_MUX(5); //fb_ad[18]
PORTA_PCR8=PORT_PCR_MUX(5); //fb_ad[17]
PORTA_PCR9=PORT_PCR_MUX(5); //fb_ad[16]
PORTA_PCR10=PORT_PCR_MUX(5); //fb_ad[15]
PORTA_PCR24=PORT_PCR_MUX(5); //fb_ad[14]
PORTA_PCR25=PORT_PCR_MUX(5); //fb_ad[13]
PORTA_PCR26=PORT_PCR_MUX(5); //fb_ad[12]
PORTA_PCR27=PORT_PCR_MUX(5); //fb_ad[11]
PORTA_PCR28=PORT_PCR_MUX(5); //fb_ad[10]
PORTD_PCR10=PORT_PCR_MUX(5); //fb_ad[9]
PORTD_PCR11=PORT_PCR_MUX(5); //fb_ad[8]
PORTD_PCR12=PORT_PCR_MUX(5); //fb_ad[7]
PORTD_PCR13=PORT_PCR_MUX(5); //fb_ad[6]
PORTD_PCR14=PORT_PCR_MUX(5); //fb_ad[5]
PORTE_PCR8=PORT_PCR_MUX(5); //fb_ad[4]
PORTE_PCR9=PORT_PCR_MUX(5); //fb_ad[3]
PORTE_PCR10=PORT_PCR_MUX(5); //fb_ad[2]
PORTE_PCR11=PORT_PCR_MUX(5); //fb_ad[1]
PORTE_PCR12=PORT_PCR_MUX(5); //fb_ad[0]
//control signals
PORTA_PCR11=PORT_PCR_MUX(5); //fb_oe_b
PORTD_PCR15=PORT_PCR_MUX(5); //fb_rw_b
PORTE_PCR7=PORT_PCR_MUX(5); //fb_cs0_b
PORTE_PCR6=PORT_PCR_MUX(5); //fb_ale
}
/*FUNCTION*---------------------------------------------------------------------
*
* Function Name : _bsp_flexbus_mram_setup
* Returned Value :
* Comments :
* Setup FlexBus for MRAM operation
*
*END*-------------------------------------------------------------------------*/
static void _bsp_flexbus_mram_setup (const uint_32 base_address)
{
FB_MemMapPtr fb_ptr = FB_BASE_PTR;
/* Enable external MRAM mapped on CS0 */
/* CS0 base address */
fb_ptr->CS[0].CSAR = base_address;
/* CS0 control (8bit data, 1 wait state, multiplexed mode) */
fb_ptr->CS[0].CSCR = FB_CSCR_ASET(1) |
FB_CSCR_AA_MASK |
FB_CSCR_WS(2) |
FB_CSCR_PS(1) |
FB_CSCR_BEM_MASK |
FB_CSCR_BLS_MASK;
/* CS0 address mask and enable */
fb_ptr->CS[0].CSMR = FB_CSMR_BAM(0x07) | FB_CSMR_V_MASK;
}
/*FUNCTION*---------------------------------------------------------------------
*
* Function Name : _bsp_flexbus_pccard_setup
* Returned Value :
* Comments :
* Setup flexbus for pccard operation
*
*END*-------------------------------------------------------------------------*/
void _bsp_flexbus_pccard_setup (const uint_32 base_address)
{
FB_MemMapPtr fb_ptr = FB_BASE_PTR;
/* invalidate CS configuration first */
fb_ptr->CS[0].CSMR = 0;
/* Enable external PCCARD mapped on CS0 */
fb_ptr->CS[0].CSAR = base_address;
/* CS0 control (8bit data, 5 waitstates, multiplexed mode) */
fb_ptr->CS[0].CSCR = FB_CSCR_ASET(1) |
FB_CSCR_AA_MASK |
FB_CSCR_WS(11) |
FB_CSCR_PS(1) |
FB_CSCR_BEM_MASK |
FB_CSCR_BLS_MASK;
/* CS0 address mask (64 KB) and enable */
fb_ptr->CS[0].CSMR = FB_CSMR_BAM(0) | FB_CSMR_V_MASK;
}
void TWRK60_flexbus_init(void){
/* Enable the FlexBus */
/* Configure the FlexBus Registers for 8-bit port size */
/* with separate address and data using chip select 0 */
/* These configurations are specific to communicating with */
/* the MRAM used in this example */
/* For K60 tower module - do not set byte lane shift so that data */
/* comes out on AD[31:24] */
//Set Base address
FB_CSAR0 = (uint32)&MRAM_START_ADDRESS;
FB_CSCR0 = FB_CSCR_PS(1) // 8-bit port
| FB_CSCR_AA_MASK // auto-acknowledge
| FB_CSCR_ASET(0x1) // assert chip select on second clock edge after address is asserted
| FB_CSCR_WS(0x1) // 1 wait state - may need a wait state depending on the bus speed
;
FB_CSMR0 = FB_CSMR_BAM(0x7) //Set base address mask for 512K address space
| FB_CSMR_V_MASK //Enable cs signal
;
//enable BE signals - note, not used in this example
FB_CSPMCR = 0x02200000;
//fb clock divider 3
SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV3(0x3);
/* Configure the pins needed to FlexBus Function (Alt 5) */
/* this example uses low drive strength settings */
//address
PORTB_PCR11 = PORT_PCR_MUX(5); // fb_ad[18]
PORTB_PCR16 = PORT_PCR_MUX(5); // fb_ad[17]
PORTB_PCR17 = PORT_PCR_MUX(5); // fb_ad[16]
PORTB_PCR18 = PORT_PCR_MUX(5); // fb_ad[15]
PORTC_PCR0 = PORT_PCR_MUX(5); // fb_ad[14]
PORTC_PCR1 = PORT_PCR_MUX(5); // fb_ad[13]
PORTC_PCR2 = PORT_PCR_MUX(5); // fb_ad[12]
PORTC_PCR4 = PORT_PCR_MUX(5); // fb_ad[11]
PORTC_PCR5 = PORT_PCR_MUX(5); // fb_ad[10]
PORTC_PCR6 = PORT_PCR_MUX(5); // fb_ad[9]
PORTC_PCR7 = PORT_PCR_MUX(5); // fb_ad[8]
PORTC_PCR8 = PORT_PCR_MUX(5); // fb_ad[7]
PORTC_PCR9 = PORT_PCR_MUX(5); // fb_ad[6]
PORTC_PCR10 = PORT_PCR_MUX(5); // fb_ad[5]
PORTD_PCR2 = PORT_PCR_MUX(5); // fb_ad[4]
PORTD_PCR3 = PORT_PCR_MUX(5); // fb_ad[3]
PORTD_PCR4 = PORT_PCR_MUX(5); // fb_ad[2]
PORTD_PCR5 = PORT_PCR_MUX(5); // fb_ad[1]
PORTD_PCR6 = PORT_PCR_MUX(5); // fb_ad[0]
//data
PORTB_PCR20 = PORT_PCR_MUX(5); // fb_ad[31] used as d[7]
PORTB_PCR21 = PORT_PCR_MUX(5); // fb_ad[30] used as d[6]
PORTB_PCR22 = PORT_PCR_MUX(5); // fb_ad[29] used as d[5]
PORTB_PCR23 = PORT_PCR_MUX(5); // fb_ad[28] used as d[4]
PORTC_PCR12 = PORT_PCR_MUX(5); // fb_ad[27] used as d[3]
PORTC_PCR13 = PORT_PCR_MUX(5); // fb_ad[26] used as d[2]
PORTC_PCR14 = PORT_PCR_MUX(5); // fb_ad[25] used as d[1]
PORTC_PCR15 = PORT_PCR_MUX(5); // fb_ad[24] used as d[0]
//control signals
PORTB_PCR19 = PORT_PCR_MUX(5); // fb_oe_b
PORTC_PCR11 = PORT_PCR_MUX(5); // fb_rw_b
PORTD_PCR1 = PORT_PCR_MUX(5); // fb_cs0_b
PORTD_PCR0 = PORT_PCR_MUX(5); // fb_ale
}
