* @IPA_CPU_2_HW_CMD_MHI_INIT_CHANNEL: Initialize specific channel to be ready
* to serve MHI transfers. Once initialization was completed HW shall
* respond with IPA_HW_2_CPU_RESPONSE_MHI_CHANGE_CHANNEL_STATE.
* IPA_HW_MHI_CHANNEL_STATE_ENABLE
* @IPA_CPU_2_HW_CMD_MHI_UPDATE_MSI: Update MHI MSI interrupts data.
* Once operation was completed HW shall respond with
* IPA_HW_2_CPU_RESPONSE_CMD_COMPLETED.
* @IPA_CPU_2_HW_CMD_MHI_CHANGE_CHANNEL_STATE: Change specific channel
* processing state following host request. Once operation was completed
* HW shall respond with IPA_HW_2_CPU_RESPONSE_MHI_CHANGE_CHANNEL_STATE.
* @IPA_CPU_2_HW_CMD_MHI_DL_UL_SYNC_INFO: Info related to DL UL syncronization.
* @IPA_CPU_2_HW_CMD_MHI_STOP_EVENT_UPDATE: Cmd to stop event ring processing.
*/
enum ipa_cpu_2_hw_mhi_commands {
IPA_CPU_2_HW_CMD_MHI_INIT
= FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 0),
IPA_CPU_2_HW_CMD_MHI_INIT_CHANNEL
= FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 1),
IPA_CPU_2_HW_CMD_MHI_UPDATE_MSI
= FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 2),
IPA_CPU_2_HW_CMD_MHI_CHANGE_CHANNEL_STATE
= FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 3),
IPA_CPU_2_HW_CMD_MHI_DL_UL_SYNC_INFO
= FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 4),
IPA_CPU_2_HW_CMD_MHI_STOP_EVENT_UPDATE
= FEATURE_ENUM_VAL(IPA_HW_FEATURE_MHI, 5)
};
/**
* Values that represent MHI related HW responses to CPU commands.
* @IPA_HW_2_CPU_RESPONSE_MHI_CHANGE_CHANNEL_STATE: Response to
* enum ipa_cpu_2_hw_commands - Values that represent the commands from the CPU
* IPA_CPU_2_HW_CMD_NO_OP : No operation is required.
* IPA_CPU_2_HW_CMD_UPDATE_FLAGS : Update SW flags which defines the behavior
* of HW.
* IPA_CPU_2_HW_CMD_DEBUG_RUN_TEST : Launch predefined test over HW.
* IPA_CPU_2_HW_CMD_DEBUG_GET_INFO : Read HW internal debug information.
* IPA_CPU_2_HW_CMD_ERR_FATAL : CPU instructs HW to perform error fatal
* handling.
* IPA_CPU_2_HW_CMD_CLK_GATE : CPU instructs HW to goto Clock Gated state.
* IPA_CPU_2_HW_CMD_CLK_UNGATE : CPU instructs HW to goto Clock Ungated state.
* IPA_CPU_2_HW_CMD_MEMCPY : CPU instructs HW to do memcopy using QMB.
* IPA_CPU_2_HW_CMD_RESET_PIPE : Command to reset a pipe - SW WA for a HW bug.
*/
enum ipa_cpu_2_hw_commands {
IPA_CPU_2_HW_CMD_NO_OP =
FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 0),
IPA_CPU_2_HW_CMD_UPDATE_FLAGS =
FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 1),
IPA_CPU_2_HW_CMD_DEBUG_RUN_TEST =
FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 2),
IPA_CPU_2_HW_CMD_DEBUG_GET_INFO =
FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 3),
IPA_CPU_2_HW_CMD_ERR_FATAL =
FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 4),
IPA_CPU_2_HW_CMD_CLK_GATE =
FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 5),
IPA_CPU_2_HW_CMD_CLK_UNGATE =
FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 6),
IPA_CPU_2_HW_CMD_MEMCPY =
FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 7),
IPA_CPU_2_HW_CMD_RESET_PIPE =
