static unsigned long npcm7xx_clk_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw);
unsigned long fbdv, indv, otdv1, otdv2;
unsigned int val;
u64 ret;
if (parent_rate == 0) {
pr_err("%s: parent rate is zero", __func__);
return 0;
}
val = readl_relaxed(pll->pllcon);
indv = FIELD_GET(PLLCON_INDV, val);
fbdv = FIELD_GET(PLLCON_FBDV, val);
otdv1 = FIELD_GET(PLLCON_OTDV1, val);
otdv2 = FIELD_GET(PLLCON_OTDV2, val);
ret = (u64)parent_rate * fbdv;
do_div(ret, indv * otdv1 * otdv2);
return ret;
}
static unsigned long clk_sccg_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
u32 val, divr1, divf1, divr2, divf2, divq;
u64 temp64;
val = readl_relaxed(pll->base + PLL_CFG2);
divr1 = FIELD_GET(PLL_DIVR1_MASK, val);
divr2 = FIELD_GET(PLL_DIVR2_MASK, val);
divf1 = FIELD_GET(PLL_DIVF1_MASK, val);
divf2 = FIELD_GET(PLL_DIVF2_MASK, val);
divq = FIELD_GET(PLL_DIVQ_MASK, val);
temp64 = parent_rate;
val = readl(pll->base + PLL_CFG0);
if (val & SSCG_PLL_BYPASS2_MASK) {
temp64 = parent_rate;
} else if (val & SSCG_PLL_BYPASS1_MASK) {
temp64 *= divf2;
do_div(temp64, (divr2 + 1) * (divq + 1));
} else {
temp64 *= 2;
temp64 *= (divf1 + 1) * (divf2 + 1);
do_div(temp64, (divr1 + 1) * (divr2 + 1) * (divq + 1));
}
return temp64;
}
unsigned int getPllValue(clock_type_t clockType, pll_value_t *pPLL)
{
unsigned int ulPllReg = 0;
pPLL->inputFreq = DEFAULT_INPUT_CLOCK;
pPLL->clockType = clockType;
switch (clockType)
{
case MXCLK_PLL:
ulPllReg = PEEK32(MXCLK_PLL_CTRL);
break;
case PRIMARY_PLL:
ulPllReg = PEEK32(PANEL_PLL_CTRL);
break;
case SECONDARY_PLL:
ulPllReg = PEEK32(CRT_PLL_CTRL);
break;
case VGA0_PLL:
ulPllReg = PEEK32(VGA_PLL0_CTRL);
break;
case VGA1_PLL:
ulPllReg = PEEK32(VGA_PLL1_CTRL);
break;
}
pPLL->M = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, M);
pPLL->N = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, N);
pPLL->OD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, OD);
pPLL->POD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, POD);
return calcPLL(pPLL);
}
/*
* Use panel vertical sync as time delay function.
* Input: Number of vertical sync to wait.
*/
void panelWaitVerticalSync(unsigned long vsync_count)
{
unsigned long status;
/* Do not wait when the Panel PLL is off or display control is already off.
This will prevent the software to wait forever. */
if ((FIELD_GET(peekRegisterDWord(PANEL_PLL_CTRL), PANEL_PLL_CTRL, POWER) ==
PANEL_PLL_CTRL_POWER_OFF) ||
(FIELD_GET(peekRegisterDWord(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, TIMING) ==
PANEL_DISPLAY_CTRL_TIMING_DISABLE))
{
return;
}
while (vsync_count-- > 0)
{
/* Wait for end of vsync. */
do
{
status = FIELD_GET(peekRegisterDWord(SYSTEM_CTRL),
SYSTEM_CTRL,
PANEL_VSYNC);
}
while (status == SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
/* Wait for start of vsync. */
do
{
status = FIELD_GET(peekRegisterDWord(SYSTEM_CTRL),
SYSTEM_CTRL,
PANEL_VSYNC);
}
while (status == SYSTEM_CTRL_PANEL_VSYNC_INACTIVE);
}
}
/* Drawing Engine Interrupt Service Routine */
void deISR(
uint32_t status
)
{
de_interrupt_t *pfnHandler;
uint32_t deStatus;
if (FIELD_GET(status, INT_STATUS, DE) == INT_STATUS_DE_ACTIVE)
{
deStatus = peekRegisterDWord(DE_STATUS);
/* Walk all registered handlers for handlers that support this interrupt status */
for (pfnHandler = pDEIntHandlers; pfnHandler != ((de_interrupt_t *)0); pfnHandler = pfnHandler->next)
{
if (deStatus & pfnHandler->deMask)
pfnHandler->handler();
}
if (FIELD_GET(deStatus, DE_STATUS, 2D) == DE_STATUS_2D_ACTIVE)
{
pokeRegisterDWord(DE_STATUS,
FIELD_SET(peekRegisterDWord(DE_STATUS), DE_STATUS, 2D, CLEAR));
}
if (FIELD_GET(deStatus, DE_STATUS, CSC) == DE_STATUS_CSC_ACTIVE)
{
pokeRegisterDWord(DE_STATUS,
FIELD_SET(peekRegisterDWord(DE_STATUS), DE_STATUS, CSC, CLEAR));
}
}
}
static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
{
struct pll_params pll_params;
u32 clk_rate = clk_get_rate(usbphyc->clk);
u32 ndiv, frac;
u32 usbphyc_pll;
if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
(clk_rate > PLL_INFF_MAX_RATE_HZ)) {
dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
clk_rate);
return -EINVAL;
}
stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
if (pll_params.frac)
usbphyc_pll |= PLLFRACCTL | frac;
writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
FIELD_GET(PLLFRACIN, usbphyc_pll));
return 0;
}
static void imx_ocotp_field_decode(uint32_t field, unsigned *word,
unsigned *bit, unsigned *mask)
{
unsigned width;
*word = FIELD_GET(OCOTP_WORD_MASK, field) * 4;
*bit = FIELD_GET(OCOTP_BIT_MASK, field);
width = FIELD_GET(OCOTP_WIDTH_MASK, field);
*mask = GENMASK(width, 0);
}
static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
{
int val, cnt, enable;
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
if (val < 0)
return val;
enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
*data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
return 0;
}
static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data)
{
struct stm32_ipcc *ipcc = data;
struct device *dev = ipcc->controller.dev;
u32 status, mr, tosr, chan;
irqreturn_t ret = IRQ_NONE;
int proc_offset;
/* read 'channel occupied' status from other proc */
proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
/* search for unmasked 'channel occupied' */
status = tosr & FIELD_GET(RX_BIT_MASK, ~mr);
for (chan = 0; chan < ipcc->n_chans; chan++) {
if (!(status & (1 << chan)))
continue;
dev_dbg(dev, "%s: chan:%d rx\n", __func__, chan);
mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);
stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR,
RX_BIT_CHAN(chan));
ret = IRQ_HANDLED;
}
return ret;
}
static irqreturn_t stm32_ipcc_tx_irq(int irq, void *data)
{
struct stm32_ipcc *ipcc = data;
struct device *dev = ipcc->controller.dev;
u32 status, mr, tosr, chan;
irqreturn_t ret = IRQ_NONE;
tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR);
mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
/* search for unmasked 'channel free' */
status = ~tosr & FIELD_GET(TX_BIT_MASK, ~mr);
for (chan = 0; chan < ipcc->n_chans ; chan++) {
if (!(status & (1 << chan)))
continue;
dev_dbg(dev, "%s: chan:%d tx\n", __func__, chan);
/* mask 'tx channel free' interrupt */
stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
TX_BIT_CHAN(chan));
mbox_chan_txdone(&ipcc->controller.chans[chan], 0);
ret = IRQ_HANDLED;
}
return ret;
}
unsigned int ddk750_getVMSize()
{
unsigned int reg;
unsigned int data;
/* sm750le only use 64 mb memory*/
if(getChipType() == SM750LE)
return MB(64);
/* for 750,always use power mode0*/
reg = PEEK32(MODE0_GATE);
reg = FIELD_SET(reg,MODE0_GATE,GPIO,ON);
POKE32(MODE0_GATE,reg);
/* get frame buffer size from GPIO */
reg = FIELD_GET(PEEK32(MISC_CTRL),MISC_CTRL,LOCALMEM_SIZE);
switch(reg){
case MISC_CTRL_LOCALMEM_SIZE_8M: data = MB(8); break; /* 8 Mega byte */
case MISC_CTRL_LOCALMEM_SIZE_16M: data = MB(16); break; /* 16 Mega byte */
case MISC_CTRL_LOCALMEM_SIZE_32M: data = MB(32); break; /* 32 Mega byte */
case MISC_CTRL_LOCALMEM_SIZE_64M: data = MB(64); break; /* 64 Mega byte */
default: data = 0;break;
}
return data;
}
static void meson_ao_cec_read(struct meson_ao_cec_device *ao_cec,
unsigned long address, u8 *data,
int *res)
{
unsigned long flags;
u32 reg = FIELD_PREP(CEC_RW_ADDR, address);
int ret = 0;
if (res && *res)
return;
spin_lock_irqsave(&ao_cec->cec_reg_lock, flags);
ret = meson_ao_cec_wait_busy(ao_cec);
if (ret)
goto read_out;
writel_relaxed(reg, ao_cec->base + CEC_RW_REG);
ret = meson_ao_cec_wait_busy(ao_cec);
if (ret)
goto read_out;
*data = FIELD_GET(CEC_RW_RD_DATA,
readl_relaxed(ao_cec->base + CEC_RW_REG));
read_out:
spin_unlock_irqrestore(&ao_cec->cec_reg_lock, flags);
if (res)
*res = ret;
}
static int stm32_sai_sync_conf_provider(struct stm32_sai_data *sai, int synco)
{
u32 prev_synco;
int ret;
/* Enable peripheral clock to allow GCR register access */
ret = clk_prepare_enable(sai->pclk);
if (ret) {
dev_err(&sai->pdev->dev, "failed to enable clock: %d\n", ret);
return ret;
}
dev_dbg(&sai->pdev->dev, "Set %pOFn%s as synchro provider\n",
sai->pdev->dev.of_node,
synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
prev_synco = FIELD_GET(SAI_GCR_SYNCOUT_MASK, readl_relaxed(sai->base));
if (prev_synco != STM_SAI_SYNC_OUT_NONE && synco != prev_synco) {
dev_err(&sai->pdev->dev, "%pOFn%s already set as sync provider\n",
sai->pdev->dev.of_node,
prev_synco == STM_SAI_SYNC_OUT_A ? "A" : "B");
clk_disable_unprepare(sai->pclk);
return -EINVAL;
}
writel_relaxed(FIELD_PREP(SAI_GCR_SYNCOUT_MASK, synco), sai->base);
clk_disable_unprepare(sai->pclk);
return 0;
}
static int stm32_dac_is_enabled(struct iio_dev *indio_dev, int channel)
{
struct stm32_dac *dac = iio_priv(indio_dev);
u32 en, val;
int ret;
ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val);
if (ret < 0)
return ret;
if (STM32_DAC_IS_CHAN_1(channel))
en = FIELD_GET(STM32_DAC_CR_EN1, val);
else
en = FIELD_GET(STM32_DAC_CR_EN2, val);
return !!en;
}
static void mt76x0_rx_process_seg(struct mt76x0_dev *dev, u8 *data,
u32 seg_len, struct page *p)
{
struct sk_buff *skb;
struct mt76x0_rxwi *rxwi;
u32 fce_info, truesize = seg_len;
/* DMA_INFO field at the beginning of the segment contains only some of
* the information, we need to read the FCE descriptor from the end.
*/
fce_info = get_unaligned_le32(data + seg_len - MT_FCE_INFO_LEN);
seg_len -= MT_FCE_INFO_LEN;
data += MT_DMA_HDR_LEN;
seg_len -= MT_DMA_HDR_LEN;
rxwi = (struct mt76x0_rxwi *) data;
data += sizeof(struct mt76x0_rxwi);
seg_len -= sizeof(struct mt76x0_rxwi);
if (unlikely(FIELD_GET(MT_RXD_INFO_TYPE, fce_info)))
dev_err_once(dev->mt76.dev, "Error: RX path seen a non-pkt urb\n");
trace_mt76x0_rx(&dev->mt76, rxwi, fce_info);
skb = mt76x0_rx_skb_from_seg(dev, rxwi, data, seg_len, truesize, p);
if (!skb)
return;
spin_lock(&dev->mac_lock);
ieee80211_rx(dev->mt76.hw, skb);
spin_unlock(&dev->mac_lock);
}
/*
* This function gets the current alpha method and value (when applicable) used.
*
* Input:
* pAlphaValue - Pointer to save the alpha value used (if the return
* value is 1 (Given alpha value method)
*
* Returns:
* 0 - Per-pixel value method
* 1 - Given alpha value method
*/
uint32_t alphaGetAlphaMethod(
uint32_t *pAlphaValue
)
{
uint32_t value;
value = peekRegisterDWord(ALPHA_DISPLAY_CTRL);
if (pAlphaValue)
*pAlphaValue = FIELD_GET(value, ALPHA_DISPLAY_CTRL, ALPHA);
if (FIELD_GET(value, ALPHA_DISPLAY_CTRL, SELECT) == ALPHA_DISPLAY_CTRL_SELECT_ALPHA)
return 1;
return 0;
}
am18x_rt edma_completed(EDMA_con_t* econ, const edma_conf_t* conf) {
EDMA3CC_con_t* ccon = &econ->CC;
EDMA3CC_rgn_t* rgn;
pa_conf_t* pa;
uint32_t msk;
int i;
rgn = region_2_reg(ccon, conf->region);
pa = conf->pa_conf;
for (i = 0; i < conf->pa_cnt; i++, pa++) {
#if 0
if ((pa->flags & FLAG_LAST_PAENTRY) == 0) {
continue;
}
#endif
if ((pa->flags & FLAG_TRANS_INTR) == 0) {
continue;
}
msk = IxR_En_MASK(pa->tcc);
if (FIELD_GET(rgn->IPR, msk) == IxR_En_none(pa->tcc)) {
return AM18X_ERR;
}
}
// clear pending bits in IPR
rgn->ICR = rgn->IPR;
return AM18X_OK;
}
/*
* This function gets the alpha starting coordinate position.
*
* Input:
* pX - Pointer to a buffer to save the x Coordinate of the current alpha coordinate
* pY - Pointer to a buffer to save the y Coordinate of the current alpha coordinate
*
*/
void alphaGetPosition(
uint32_t *pX,
uint32_t *pY
)
{
uint32_t positionTopLeft;
/* Get the starting coordinate of the alpha plane */
positionTopLeft = peekRegisterDWord(ALPHA_PLANE_TL);
if (pX)
*pX = (uint32_t) FIELD_GET(positionTopLeft, ALPHA_PLANE_TL, LEFT);
if (pY)
*pY = (uint32_t) FIELD_GET(positionTopLeft, ALPHA_PLANE_TL, TOP);
}
static void set_cmd_response(struct cvm_mmc_host *host, struct mmc_request *req,
u64 rsp_sts)
{
u64 rsp_hi, rsp_lo;
if (!(rsp_sts & MIO_EMM_RSP_STS_RSP_VAL))
return;
rsp_lo = readq(host->base + MIO_EMM_RSP_LO(host));
switch (FIELD_GET(MIO_EMM_RSP_STS_RSP_TYPE, rsp_sts)) {
case 1:
case 3:
req->cmd->resp[0] = (rsp_lo >> 8) & 0xffffffff;
req->cmd->resp[1] = 0;
req->cmd->resp[2] = 0;
req->cmd->resp[3] = 0;
break;
case 2:
req->cmd->resp[3] = rsp_lo & 0xffffffff;
req->cmd->resp[2] = (rsp_lo >> 32) & 0xffffffff;
rsp_hi = readq(host->base + MIO_EMM_RSP_HI(host));
req->cmd->resp[1] = rsp_hi & 0xffffffff;
req->cmd->resp[0] = (rsp_hi >> 32) & 0xffffffff;
break;
}
}
static int stm32_vrefbuf_get_voltage_sel(struct regulator_dev *rdev)
{
struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
u32 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
return FIELD_GET(STM32_VRS, val);
}
/*
* This function sets the alpha window size.
*
* Input:
* width - Alpha Window width
* height - Alpha Window height
*
*/
void alphaSetWindowSize(
uint32_t width,
uint32_t height
)
{
uint32_t value, startX, startY;
/* Get the video window width and height */
value = peekRegisterDWord(ALPHA_PLANE_TL);
startX = FIELD_GET(value, ALPHA_PLANE_TL, LEFT);
startY = FIELD_GET(value, ALPHA_PLANE_TL, TOP);
/* Set bottom and right position */
pokeRegisterDWord(ALPHA_PLANE_BR,
FIELD_VALUE(0, ALPHA_PLANE_BR, BOTTOM, startY + height - 1) |
FIELD_VALUE(0, ALPHA_PLANE_BR, RIGHT, startX + width - 1));
}
// Program new power mode.
void setPower(unsigned long nGates, unsigned long Clock)
{
unsigned long gate_reg, clock_reg;
unsigned long control_value;
// Get current power mode.
control_value = FIELD_GET(regRead32(POWER_MODE_CTRL),
POWER_MODE_CTRL,
MODE);
switch (control_value)
{
case POWER_MODE_CTRL_MODE_MODE0:
// Switch from mode 0 to mode 1.
gate_reg = POWER_MODE1_GATE;
clock_reg = POWER_MODE1_CLOCK;
control_value = FIELD_SET(control_value,
POWER_MODE_CTRL, MODE, MODE1);
break;
case POWER_MODE_CTRL_MODE_MODE1:
case POWER_MODE_CTRL_MODE_SLEEP:
// Switch from mode 1 or sleep to mode 0.
gate_reg = POWER_MODE0_GATE;
clock_reg = POWER_MODE0_CLOCK;
control_value = FIELD_SET(control_value, POWER_MODE_CTRL, MODE, MODE0);
break;
default:
// Invalid mode
return;
}
// Program new power mode.
regWrite32(gate_reg, nGates);
regWrite32(clock_reg, Clock);
regWrite32(POWER_MODE_CTRL, control_value);
// When returning from sleep, wait until finished.
while (FIELD_GET(regRead32(POWER_MODE_CTRL),
POWER_MODE_CTRL,
SLEEP_STATUS) == POWER_MODE_CTRL_SLEEP_STATUS_ACTIVE) ;
}
struct clk_hw * __init
sam9x60_clk_register_pll(struct regmap *regmap, spinlock_t *lock,
const char *name, const char *parent_name, u8 id,
const struct clk_pll_characteristics *characteristics)
{
struct sam9x60_pll *pll;
struct clk_hw *hw;
struct clk_init_data init;
unsigned int pllr;
int ret;
if (id > PLL_MAX_ID)
return ERR_PTR(-EINVAL);
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
if (!pll)
return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = &pll_ops;
init.parent_names = &parent_name;
init.num_parents = 1;
init.flags = CLK_SET_RATE_GATE;
pll->id = id;
pll->hw.init = &init;
pll->characteristics = characteristics;
pll->regmap = regmap;
pll->lock = lock;
regmap_write(regmap, PMC_PLL_UPDT, id);
regmap_read(regmap, PMC_PLL_CTRL0, &pllr);
pll->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, pllr);
regmap_read(regmap, PMC_PLL_CTRL1, &pllr);
pll->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, pllr);
hw = &pll->hw;
ret = clk_hw_register(NULL, hw);
if (ret) {
kfree(pll);
hw = ERR_PTR(ret);
}
return hw;
}
static void
mt76x2_adjust_agc_gain(struct mt76x02_dev *dev, int reg, s8 offset)
{
s8 gain;
gain = FIELD_GET(MT_BBP_AGC_GAIN, mt76_rr(dev, MT_BBP(AGC, reg)));
gain += offset;
mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_GAIN, gain);
}
static void
mt76x2_adjust_high_lna_gain(struct mt76x02_dev *dev, int reg, s8 offset)
{
s8 gain;
gain = FIELD_GET(MT_BBP_AGC_LNA_HIGH_GAIN, mt76_rr(dev, MT_BBP(AGC, reg)));
gain -= offset / 2;
mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_LNA_HIGH_GAIN, gain);
}
static void aqr107_link_change_notify(struct phy_device *phydev)
{
u8 fw_major, fw_minor;
bool downshift, short_reach, afr;
int mode, val;
if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
return;
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
/* call failed or link partner is no Aquantia PHY */
if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
return;
short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
if (val < 0)
return;
fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
if (val < 0)
return;
afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
fw_major, fw_minor,
short_reach ? ", short reach mode" : "",
downshift ? ", fast-retrain downshift advertised" : "",
afr ? ", fast reframe advertised" : "");
val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
if (val < 0)
return;
mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
}
am18x_rt edma_status(const EDMA_con_t* econ, edma_stat_t* stat) {
static int bit_nrs[] = {0, 1, 2, 3, 4, 16, 17, -1};
static char* inner_status[] = {
"DMA event active",
"QDMA event active",
"transfer request active",
"write status active",
"channel controller active",
"Queue 0 active",
"Queue 1 active",
"none",
};
uint32_t ccstat;
int i;
ccstat = econ->CC.CCSTAT;
if (FIELD_GET(ccstat, 0x0003001FUL) == 0) {
return AM18X_ERR;
}
if (stat == NULL) {
return AM18X_OK;
}
stat->comp_actv = __field_xget(ccstat, CCSTAT_COMPACTV_MASK);
stat->queue_evts[0] = __field_xget(econ->CC.QSTATx[0], QSTAT_NUMVAL_MASK);
if (econ == EDMA0) {
stat->queue_evts[1] = __field_xget(econ->CC.QSTATx[1], QSTAT_NUMVAL_MASK);
} else {
stat->queue_evts[1] = 0;
}
for (i = 0; bit_nrs[i] != -1; i++) {
if (FIELD_GET(ccstat, BIT(bit_nrs[i])) != 0) {
stat->status[i] = inner_status[i];
} else {
stat->status[i] = "none";
}
}
stat->status[i] = NULL;
return AM18X_OK;
}
static int mt76x02u_mcu_wait_resp(struct mt76_dev *dev, u8 seq)
{
struct mt76_usb *usb = &dev->usb;
struct mt76u_buf *buf = &usb->mcu.res;
struct urb *urb = buf->urb;
int i, ret;
u32 rxfce;
u8 *data;
for (i = 0; i < 5; i++) {
if (!wait_for_completion_timeout(&usb->mcu.cmpl,
msecs_to_jiffies(300)))
continue;
if (urb->status)
return -EIO;
data = sg_virt(&urb->sg[0]);
if (usb->mcu.rp)
mt76x02u_multiple_mcu_reads(dev, data + 4,
urb->actual_length - 8);
rxfce = get_unaligned_le32(data);
ret = mt76u_submit_buf(dev, USB_DIR_IN,
MT_EP_IN_CMD_RESP,
buf, GFP_KERNEL,
mt76u_mcu_complete_urb,
&usb->mcu.cmpl);
if (ret)
return ret;
if (seq == FIELD_GET(MT_RX_FCE_INFO_CMD_SEQ, rxfce) &&
FIELD_GET(MT_RX_FCE_INFO_EVT_TYPE, rxfce) == EVT_CMD_DONE)
return 0;
dev_err(dev->dev, "error: MCU resp evt:%lx seq:%hhx-%lx\n",
FIELD_GET(MT_RX_FCE_INFO_EVT_TYPE, rxfce),
seq, FIELD_GET(MT_RX_FCE_INFO_CMD_SEQ, rxfce));
}
dev_err(dev->dev, "error: %s timed out\n", __func__);
return -ETIMEDOUT;
}
static enum nfp_repr_type
nfp_flower_repr_get_type_and_port(struct nfp_app *app, u32 port_id, u8 *port)
{
switch (FIELD_GET(NFP_FLOWER_CMSG_PORT_TYPE, port_id)) {
case NFP_FLOWER_CMSG_PORT_TYPE_PHYS_PORT:
*port = FIELD_GET(NFP_FLOWER_CMSG_PORT_PHYS_PORT_NUM,
port_id);
return NFP_REPR_TYPE_PHYS_PORT;
case NFP_FLOWER_CMSG_PORT_TYPE_PCIE_PORT:
*port = FIELD_GET(NFP_FLOWER_CMSG_PORT_VNIC, port_id);
if (FIELD_GET(NFP_FLOWER_CMSG_PORT_VNIC_TYPE, port_id) ==
NFP_FLOWER_CMSG_PORT_VNIC_TYPE_PF)
return NFP_REPR_TYPE_PF;
else
return NFP_REPR_TYPE_VF;
}
return NFP_FLOWER_CMSG_PORT_TYPE_UNSPEC;
}
static int stm32_lptim_is_enabled(struct stm32_lptim_cnt *priv)
{
u32 val;
int ret;
ret = regmap_read(priv->regmap, STM32_LPTIM_CR, &val);
if (ret)
return ret;
return FIELD_GET(STM32_LPTIM_ENABLE, val);
}