/* Drawing Engine Interrupt Service Routine */
void deISR(
uint32_t status
)
{
de_interrupt_t *pfnHandler;
uint32_t deStatus;
if (FIELD_GET(status, INT_STATUS, DE) == INT_STATUS_DE_ACTIVE)
{
deStatus = peekRegisterDWord(DE_STATUS);
/* Walk all registered handlers for handlers that support this interrupt status */
for (pfnHandler = pDEIntHandlers; pfnHandler != ((de_interrupt_t *)0); pfnHandler = pfnHandler->next)
{
if (deStatus & pfnHandler->deMask)
pfnHandler->handler();
}
if (FIELD_GET(deStatus, DE_STATUS, 2D) == DE_STATUS_2D_ACTIVE)
{
pokeRegisterDWord(DE_STATUS,
FIELD_SET(peekRegisterDWord(DE_STATUS), DE_STATUS, 2D, CLEAR));
}
if (FIELD_GET(deStatus, DE_STATUS, CSC) == DE_STATUS_CSC_ACTIVE)
{
pokeRegisterDWord(DE_STATUS,
FIELD_SET(peekRegisterDWord(DE_STATUS), DE_STATUS, CSC, CLEAR));
}
}
}
/*
* This function sets the alpha FIFO Request Level.
*
* Input:
* alphaFIFO - Alpha FIFO Request Level
*
*/
void alphaSetFIFOLevel(
alpha_fifo_t alphaFIFO
)
{
uint32_t value;
value = peekRegisterDWord(ALPHA_DISPLAY_CTRL);
switch(alphaFIFO)
{
default:
case ALPHA_FIFO_LEVEL_1:
value = FIELD_SET(value, ALPHA_DISPLAY_CTRL, FIFO, 1);
break;
case ALPHA_FIFO_LEVEL_3:
value = FIELD_SET(value, ALPHA_DISPLAY_CTRL, FIFO, 3);
break;
case ALPHA_FIFO_LEVEL_7:
value = FIELD_SET(value, ALPHA_DISPLAY_CTRL, FIFO, 7);
break;
case ALPHA_FIFO_LEVEL_11:
value = FIELD_SET(value, ALPHA_DISPLAY_CTRL, FIFO, 11);
break;
}
pokeRegisterDWord(ALPHA_DISPLAY_CTRL, value);
}
am18x_rt edma_interrupt(EDMA_con_t* econ, const edma_conf_t* conf) {
EDMA3CC_con_t* ccon = &econ->CC;
EDMA3CC_rgn_t* rgn;
pa_conf_t* pa;
uint32_t msk;
int i;
rgn = region_2_reg(ccon, conf->region);
pa = conf->pa_conf;
for (i = 0; i < conf->pa_cnt; i++, pa++) {
if (pa->flags & FLAG_TRANS_INTR) {
if (conf->region != REGION_GLOBAL && pa->tcc != conf->channel) {
uint32_t v;
v = ccon->DRAEx[DRAE_IDX(conf->region)];
v = FIELD_SET(v, DRAE_En_MASK(pa->tcc), DRAE_En_allow(pa->tcc));
ccon->DRAEx[DRAE_IDX(conf->region)] = v;
}
msk = IExR_En_MASK(pa->tcc);
rgn->IESR = FIELD_SET(0, msk, IExR_En_set(pa->tcc));
}
if (pa->flags & FLAG_TRANS_EVT) {
msk = EExR_En_MASK(pa->tcc);
rgn->EESR = FIELD_SET(0, msk, EExR_En_set(pa->tcc));
}
}
return AM18X_OK;
}
int hwI2CInit(
unsigned char busSpeedMode
)
{
unsigned int value;
/* Enable GPIO 30 & 31 as IIC clock & data */
value = PEEK32(GPIO_MUX);
value = FIELD_SET(value, GPIO_MUX, 30, I2C) |
FIELD_SET(0, GPIO_MUX, 31, I2C);
POKE32(GPIO_MUX, value);
/* Enable Hardware I2C power.
TODO: Check if we need to enable GPIO power?
*/
enableI2C(1);
/* Enable the I2C Controller and set the bus speed mode */
value = PEEK32(I2C_CTRL);
if (busSpeedMode == 0)
value = FIELD_SET(value, I2C_CTRL, MODE, STANDARD);
else
value = FIELD_SET(value, I2C_CTRL, MODE, FAST);
value = FIELD_SET(value, I2C_CTRL, EN, ENABLE);
POKE32(I2C_CTRL, value);
return 0;
}
/*
* This function enable/disable the ZV Port.
*/
void enableZVPort(unsigned long enable)
{
unsigned long gate;
/* Enable ZV Port Gate */
gate = peekRegisterDWord(CURRENT_GATE);
if (enable)
{
gate = FIELD_SET(gate, CURRENT_GATE, ZVPORT, ON);
#if 0
/* Using Software I2C */
gate = FIELD_SET(gate, CURRENT_GATE, GPIO, ON);
#else
/* Using Hardware I2C */
gate = FIELD_SET(gate, CURRENT_GATE, I2C, ON);
#endif
}
else
{
/* Disable ZV Port Gate. There is no way to know whether the GPIO pins are being used
or not. Therefore, do not disable the GPIO gate. */
gate = FIELD_SET(gate, CURRENT_GATE, ZVPORT, OFF);
}
setCurrentGate(gate);
}
/*
* This function closes the SSP interface
*/
void sspClose()
{
uint32_t value;
/* Disable SSP Interface. */
pokeRegisterByte(getSSPRegisterOffset(SSP_0_CONTROL_1), 0);
value = peekRegisterDWord(GPIO_MUX);
if (gCurrentSSPIndex == 0)
{
/* Select SSP 0 Pins */
pokeRegisterDWord(GPIO_MUX,
FIELD_SET(value, GPIO_MUX, 24, GPIO) |
FIELD_SET(value, GPIO_MUX, 23, GPIO) |
FIELD_SET(value, GPIO_MUX, 22, GPIO) |
FIELD_SET(value, GPIO_MUX, 21, GPIO) |
FIELD_SET(value, GPIO_MUX, 20, GPIO));
}
else
{
/* Select SSP 1 Pins */
pokeRegisterDWord(GPIO_MUX,
FIELD_SET(value, GPIO_MUX, 29, GPIO) |
FIELD_SET(value, GPIO_MUX, 28, GPIO) |
FIELD_SET(value, GPIO_MUX, 27, GPIO) |
FIELD_SET(value, GPIO_MUX, 26, GPIO) |
FIELD_SET(value, GPIO_MUX, 25, GPIO) );
}
}
/* hw_cursor_xxx works for voyager,718 and 750 */
void hw_cursor_enable(struct lynx_cursor * cursor)
{
u32 reg;
reg = FIELD_VALUE(0,HWC_ADDRESS,ADDRESS,cursor->offset)|
FIELD_SET(0,HWC_ADDRESS,EXT,LOCAL)|
FIELD_SET(0,HWC_ADDRESS,ENABLE,ENABLE);
POKE32(HWC_ADDRESS,reg);
}
/*
* hookSSPInterrupt
* Register SSP Interrupt function.
*/
unsigned short hookSSPInterrupt(
ssp_ctrl_t sspControl,
void (*handler)(void)
)
{
ssp_interrupt_t *pfnNewHandler, *pfnHandler, *pfnInterruptHandler;
unsigned short returnValue = 0;
/* Allocate a new interrupt structure */
pfnNewHandler = (ssp_interrupt_t *)malloc(sizeof(ssp_interrupt_t));
if (pfnNewHandler == ((ssp_interrupt_t *)0))
{
/* No more memory */
return (-1);
}
/* Get the right pointer to the interrupt handler */
if (sspControl == SSP1)
pfnInterruptHandler = ssp1IntHandlers;
else
pfnInterruptHandler = ssp0IntHandlers;
/* Make sure that it has not been register more than once */
for (pfnHandler = pfnInterruptHandler; pfnHandler != ((ssp_interrupt_t *)0); pfnHandler = pfnHandler->next)
{
if (pfnHandler->handler == handler)
return (-1); /* Duplicate entry */
}
/* If this is the first interrupt handler, register this ZV Port ISR */
if (pfnInterruptHandler == ((ssp_interrupt_t *)0))
{
returnValue = registerHandler((sspControl == SSP1) ? ssp1ISR : ssp0ISR,
(sspControl == SSP1) ?
FIELD_SET(0, INT_MASK, SSP1, ENABLE) :
FIELD_SET(0, INT_MASK, SSP0, ENABLE));
}
if (returnValue == 0)
{
/* Fill interrupt structure. */
pfnNewHandler->next = pfnInterruptHandler;
pfnNewHandler->handler = handler;
pfnInterruptHandler = pfnNewHandler;
}
/* Update the actual handler */
if (sspControl == SSP1)
ssp1IntHandlers = pfnInterruptHandler;
else
ssp0IntHandlers = pfnInterruptHandler;
return returnValue;
}
am18x_rt edma_init(EDMA_con_t* econ, const edma_conf_t* conf) {
uint32_t v, ch;
EDMA3CC_con_t* ccon = &econ->CC;
EDMA3CC_rgn_t* rgn;
ch = conf->channel;
if (is_qchannel(conf)) {
v = ccon->QCHMAPx[ch];
v = __field_xset(v, QCHMAP_PAENTRY_MASK, conf->pa_conf[0].index);
v = __field_xset(v, QCHMAP_TRWORD_MASK, conf->tr_word);
ccon->QCHMAPx[ch] = v;
}
rgn = region_2_reg(ccon, conf->region);
if (conf->region != REGION_GLOBAL) {
if (is_qchannel(conf)) {
v = ccon->QRAEx[conf->region];
v = FIELD_SET(v, QRAE_En_MASK(ch), QRAE_En_allow(ch));
ccon->QRAEx[conf->region] = v;
} else {
v = ccon->DRAEx[DRAE_IDX(conf->region)];
v = FIELD_SET(v, DRAE_En_MASK(ch), DRAE_En_allow(ch));
ccon->DRAEx[DRAE_IDX(conf->region)] = v;
}
}
switch(conf->trigger) {
case DMA_EVENT_TRIGGERED:
case DMA_MANUALLY_TRIGGERED:
rgn->EESR = FIELD_SET(0, EExR_En_MASK(ch), EExR_En_set(ch));
break;
case QDMA_AUTO_TRIGGERED:
break;
//case DMA_CHAIN_TRIGGERED:
//case QDMA_LINK_TRIGGERED:
// break;
}
if (econ == EDMA0) {
if (is_qchannel(conf)) {
v = ccon->QDMAQNUM;
v = __field_xset(v, QDMAQNUM_En_MASK(ch), conf->queue);
ccon->QDMAQNUM = v;
} else {
v = ccon->DMAQNUMx[DMAQNUM_IDX(ch)];
v = __field_xset(v, DMAQNUM_En_MASK(ch), conf->queue);
ccon->DMAQNUMx[DMAQNUM_IDX(ch)] = v;
}
}
return AM18X_OK;
}
/*
* This function enable/disable the GPIO Engine
*/
void enableGPIO(unsigned long enable)
{
unsigned long gate;
/* Enable GPIO Gate */
gate = peekRegisterDWord(CURRENT_GATE);
if (enable)
gate = FIELD_SET(gate, CURRENT_GATE, GPIO, ON);
else
gate = FIELD_SET(gate, CURRENT_GATE, GPIO, OFF);
setCurrentGate(gate);
}
void deHorizontalLine(unsigned long dst_base,
unsigned long dst_pitch,
unsigned long nX,
unsigned long nY,
unsigned long dst_width, unsigned long nColor)
{
deWaitForNotBusy();
SMTC_write2Dreg(DE_WINDOW_DESTINATION_BASE,
FIELD_VALUE(0, DE_WINDOW_DESTINATION_BASE, ADDRESS,
dst_base));
SMTC_write2Dreg(DE_PITCH,
FIELD_VALUE(0, DE_PITCH, DESTINATION, dst_pitch) |
FIELD_VALUE(0, DE_PITCH, SOURCE, dst_pitch));
SMTC_write2Dreg(DE_WINDOW_WIDTH,
FIELD_VALUE(0, DE_WINDOW_WIDTH, DESTINATION,
dst_pitch) | FIELD_VALUE(0, DE_WINDOW_WIDTH,
SOURCE,
dst_pitch));
SMTC_write2Dreg(DE_FOREGROUND,
FIELD_VALUE(0, DE_FOREGROUND, COLOR, nColor));
SMTC_write2Dreg(DE_DESTINATION,
FIELD_SET(0, DE_DESTINATION, WRAP,
DISABLE) | FIELD_VALUE(0, DE_DESTINATION, X,
nX) | FIELD_VALUE(0,
DE_DESTINATION,
Y,
nY));
SMTC_write2Dreg(DE_DIMENSION,
FIELD_VALUE(0, DE_DIMENSION, X,
dst_width) | FIELD_VALUE(0, DE_DIMENSION,
Y_ET, 1));
SMTC_write2Dreg(DE_CONTROL,
FIELD_SET(0, DE_CONTROL, STATUS, START) | FIELD_SET(0,
DE_CONTROL,
DIRECTION,
RIGHT_TO_LEFT)
| FIELD_SET(0, DE_CONTROL, MAJOR, X) | FIELD_SET(0,
DE_CONTROL,
STEP_X,
POSITIVE)
| FIELD_SET(0, DE_CONTROL, STEP_Y,
NEGATIVE) | FIELD_SET(0, DE_CONTROL,
LAST_PIXEL,
OFF) | FIELD_SET(0,
DE_CONTROL,
COMMAND,
SHORT_STROKE)
| FIELD_SET(0, DE_CONTROL, ROP_SELECT,
ROP2) | FIELD_VALUE(0, DE_CONTROL, ROP,
0x0C));
smtc_de_busy = 1;
}
/*
* This function enables/disables the alpha display
*
* Input:
* enableAlpha - Enable/Disable Alpha Display Plane
*/
_X_EXPORT void alphaEnableDisplay(
uint32_t enableAlpha
)
{
uint32_t value;
value = peekRegisterDWord(ALPHA_DISPLAY_CTRL);
if (enableAlpha)
value = FIELD_SET(value, ALPHA_DISPLAY_CTRL, PLANE, ENABLE);
else
value = FIELD_SET(value, ALPHA_DISPLAY_CTRL, PLANE, DISABLE);
pokeRegisterDWord(ALPHA_DISPLAY_CTRL, value);
}
unsigned int ddk750_getVMSize()
{
unsigned int reg;
unsigned int data;
/* sm750le only use 64 mb memory*/
if(getChipType() == SM750LE)
return MB(64);
/* for 750,always use power mode0*/
reg = PEEK32(MODE0_GATE);
reg = FIELD_SET(reg,MODE0_GATE,GPIO,ON);
POKE32(MODE0_GATE,reg);
/* get frame buffer size from GPIO */
reg = FIELD_GET(PEEK32(MISC_CTRL),MISC_CTRL,LOCALMEM_SIZE);
switch(reg){
case MISC_CTRL_LOCALMEM_SIZE_8M: data = MB(8); break; /* 8 Mega byte */
case MISC_CTRL_LOCALMEM_SIZE_16M: data = MB(16); break; /* 16 Mega byte */
case MISC_CTRL_LOCALMEM_SIZE_32M: data = MB(32); break; /* 32 Mega byte */
case MISC_CTRL_LOCALMEM_SIZE_64M: data = MB(64); break; /* 64 Mega byte */
default: data = 0;break;
}
return data;
}
/*
* This function enable/disable the 2D engine.
*/
void enable2DEngine(unsigned long enable)
{
unsigned long gate;
gate = peekRegisterDWord(CURRENT_GATE);
if (enable)
{
gate = FIELD_SET(gate, CURRENT_GATE, DE, ON);
gate = FIELD_SET(gate, CURRENT_GATE, CSC, ON);
}
else
{
gate = FIELD_SET(gate, CURRENT_GATE, DE, OFF);
gate = FIELD_SET(gate, CURRENT_GATE, CSC, OFF);
}
setCurrentGate(gate);
}
void set_current_gate(void)
{
unsigned long value, gate;
//change to mode0
value = regRead32(POWER_MODE_CTRL);
value = FIELD_SET(value, POWER_MODE_CTRL, MODE, MODE0);
regWrite32(POWER_MODE_CTRL, value);
// Don't forget to set up power mode0 gate properly.
gate = regRead32(CURRENT_POWER_GATE);
gate = FIELD_SET(gate, CURRENT_POWER_GATE, 2D, ENABLE);
regWrite32(POWER_MODE0_GATE, gate);
}
/*
* This function select the alpha method, either to use per-pixel
* or by the given alpha value.
*
* Input:
* useAlphaValue - Use the given alpha value.
* 0 - Use per-pixel alpha value
* 1 - Use the given alpha value
* alphaValue - Alpha value to be used in the alpha plane
*/
void alphaSelectMethod(
uint32_t useAlphaValue,
uint32_t alphaValue
)
{
uint32_t value;
value = peekRegisterDWord(ALPHA_DISPLAY_CTRL);
if (useAlphaValue)
value = FIELD_SET(0, ALPHA_DISPLAY_CTRL, SELECT, ALPHA) |
FIELD_VALUE(value, ALPHA_DISPLAY_CTRL, ALPHA, alphaValue);
else
value = FIELD_SET(value, ALPHA_DISPLAY_CTRL, SELECT, PER_PIXEL);
pokeRegisterDWord(ALPHA_DISPLAY_CTRL, value);
}
/*
* This function starts the SSP module
*/
void sspStart()
{
unsigned char value;
value = peekRegisterByte(getSSPRegisterOffset(SSP_0_CONTROL_1));
pokeRegisterByte(getSSPRegisterOffset(SSP_0_CONTROL_1),
FIELD_SET(value, SSP_0_CONTROL_1, STATUS, ENABLE));
}
/*
* This functions uses software sequence to turn on/off the panel.
*
*/
void swPanelPowerSequence(disp_state_t dispState, unsigned long vsync_delay)
{
unsigned long panelControl = peekRegisterDWord(PANEL_DISPLAY_CTRL);
if (dispState == DISP_ON)
{
/* Turn on FPVDDEN. */
panelControl = FIELD_SET(panelControl,
PANEL_DISPLAY_CTRL, FPVDDEN, HIGH);
pokeRegisterDWord(PANEL_DISPLAY_CTRL, panelControl);
panelWaitVerticalSync(vsync_delay);
/* Turn on FPDATA. */
panelControl = FIELD_SET(panelControl,
PANEL_DISPLAY_CTRL, DATA, ENABLE);
pokeRegisterDWord(PANEL_DISPLAY_CTRL, panelControl);
panelWaitVerticalSync(vsync_delay);
/* Turn on FPVBIAS. */
panelControl = FIELD_SET(panelControl,
PANEL_DISPLAY_CTRL, VBIASEN, HIGH);
pokeRegisterDWord(PANEL_DISPLAY_CTRL, panelControl);
panelWaitVerticalSync(vsync_delay);
/* Turn on FPEN. */
panelControl = FIELD_SET(panelControl,
PANEL_DISPLAY_CTRL, FPEN, HIGH);
pokeRegisterDWord(PANEL_DISPLAY_CTRL, panelControl);
}
else
{
/* Turn off FPEN. */
panelControl = FIELD_SET(panelControl,
PANEL_DISPLAY_CTRL, FPEN, LOW);
pokeRegisterDWord(PANEL_DISPLAY_CTRL, panelControl);
panelWaitVerticalSync(vsync_delay);
/* Turn off FPVBIASEN. */
panelControl = FIELD_SET(panelControl,
PANEL_DISPLAY_CTRL, VBIASEN, LOW);
pokeRegisterDWord(PANEL_DISPLAY_CTRL, panelControl);
panelWaitVerticalSync(vsync_delay);
/* Turn off FPDATA. */
panelControl = FIELD_SET(panelControl,
PANEL_DISPLAY_CTRL, DATA, DISABLE);
pokeRegisterDWord(PANEL_DISPLAY_CTRL, panelControl);
panelWaitVerticalSync(vsync_delay);
/* Turn off FPVDDEN. */
panelControl = FIELD_SET(panelControl,
PANEL_DISPLAY_CTRL, FPVDDEN, LOW);
pokeRegisterDWord(PANEL_DISPLAY_CTRL, panelControl);
}
}
// Program new power mode.
void setPower(unsigned long nGates, unsigned long Clock)
{
unsigned long gate_reg, clock_reg;
unsigned long control_value;
// Get current power mode.
control_value = FIELD_GET(regRead32(POWER_MODE_CTRL),
POWER_MODE_CTRL,
MODE);
switch (control_value)
{
case POWER_MODE_CTRL_MODE_MODE0:
// Switch from mode 0 to mode 1.
gate_reg = POWER_MODE1_GATE;
clock_reg = POWER_MODE1_CLOCK;
control_value = FIELD_SET(control_value,
POWER_MODE_CTRL, MODE, MODE1);
break;
case POWER_MODE_CTRL_MODE_MODE1:
case POWER_MODE_CTRL_MODE_SLEEP:
// Switch from mode 1 or sleep to mode 0.
gate_reg = POWER_MODE0_GATE;
clock_reg = POWER_MODE0_CLOCK;
control_value = FIELD_SET(control_value, POWER_MODE_CTRL, MODE, MODE0);
break;
default:
// Invalid mode
return;
}
// Program new power mode.
regWrite32(gate_reg, nGates);
regWrite32(clock_reg, Clock);
regWrite32(POWER_MODE_CTRL, control_value);
// When returning from sleep, wait until finished.
while (FIELD_GET(regRead32(POWER_MODE_CTRL),
POWER_MODE_CTRL,
SLEEP_STATUS) == POWER_MODE_CTRL_SLEEP_STATUS_ACTIVE) ;
}
/*
* This function closes the hardware i2c.
*/
void hwI2CClose()
{
unsigned long value;
/* Disable I2C controller */
value = peekRegisterByte(I2C_CTRL);
value = FIELD_SET(value, I2C_CTRL, EN, DISABLE);
pokeRegisterByte(I2C_CTRL, value);
/* Disable I2C Power */
enableI2C(0);
/* Set GPIO 30 & 31 back as GPIO pins */
value = peekRegisterDWord(GPIO_MUX);
value = FIELD_SET(value, GPIO_MUX, 30, GPIO);
value = FIELD_SET(value, GPIO_MUX, 31, GPIO);
pokeRegisterDWord(GPIO_MUX, value);
}
void hwI2CClose(void)
{
unsigned int value;
/* Disable I2C controller */
value = PEEK32(I2C_CTRL);
value = FIELD_SET(value, I2C_CTRL, EN, DISABLE);
POKE32(I2C_CTRL, value);
/* Disable I2C Power */
enableI2C(0);
/* Set GPIO 30 & 31 back as GPIO pins */
value = PEEK32(GPIO_MUX);
value = FIELD_SET(value, GPIO_MUX, 30, GPIO);
value = FIELD_SET(value, GPIO_MUX, 31, GPIO);
POKE32(GPIO_MUX, value);
}
/*
* This function enables/disables the dual panel
*
* Input:
* enable - Flag to enable/disable the dual Panel mode
*/
void setDualPanel(
unsigned long enable
)
{
unsigned long value;
/* Enable/Disable the Dual Display */
value = peekRegisterDWord(PANEL_DISPLAY_CTRL);
if (enable == 1)
value = FIELD_SET(value, PANEL_DISPLAY_CTRL, DUAL_DISPLAY, ENABLE);
else
value = FIELD_SET(value, PANEL_DISPLAY_CTRL, DUAL_DISPLAY, DISABLE);
pokeRegisterDWord(PANEL_DISPLAY_CTRL, value);
/* Force to 18-bit Panel. Do this after enable Dual Panel function above
since setPanelType(TFT_18BIT) will check if the Dual Panel is enable or
not before it set the Panel to 18-bit. */
if (enable == 1)
setPanelType(TFT_18BIT);
}
/*
* Return memory size of sm750 in bytes
*/
int hw_get_memsize(struct ufb_data * ufb)
{
uint32_t ulreg;
ENTER();
ulreg = peek32(ufb,MODE0_GATE);
ulreg = FIELD_SET(ulreg,MODE0_GATE,GPIO,ON);
poke32(ufb,MODE0_GATE,ulreg);
ulreg = ddk750_getFrameBufSize(ufb);
LEAVE ((int)ulreg);
}
unsigned int formatPllReg(pll_value_t *pPLL)
{
unsigned int ulPllReg = 0;
/* Note that all PLL's have the same format. Here, we just use Panel PLL parameter
to work out the bit fields in the register.
On returning a 32 bit number, the value can be applied to any PLL in the calling function.
*/
ulPllReg =
FIELD_SET( 0, PANEL_PLL_CTRL, BYPASS, OFF)
| FIELD_SET( 0, PANEL_PLL_CTRL, POWER, ON)
| FIELD_SET( 0, PANEL_PLL_CTRL, INPUT, OSC)
#ifndef VALIDATION_CHIP
| FIELD_VALUE(0, PANEL_PLL_CTRL, POD, pPLL->POD)
#endif
| FIELD_VALUE(0, PANEL_PLL_CTRL, OD, pPLL->OD)
| FIELD_VALUE(0, PANEL_PLL_CTRL, N, pPLL->N)
| FIELD_VALUE(0, PANEL_PLL_CTRL, M, pPLL->M);
return(ulPllReg);
}
/*
* displaySetInterpolation
* This function enables/disables the horizontal and vertical interpolation
* for the secondary display control. Primary display control does not have
* this capability.
*
* Input:
* enableHorzInterpolation - Flag to enable/disable Horizontal interpolation
* enableVertInterpolation - Flag to enable/disable Vertical interpolation
*/
void displaySetInterpolation(
unsigned long enableHorzInterpolation,
unsigned long enableVertInterpolation
)
{
unsigned long value;
value = peekRegisterDWord(CRT_DISPLAY_CTRL);
if (enableHorzInterpolation)
value = FIELD_SET(value, CRT_DISPLAY_CTRL, HORIZONTAL_MODE, INTERPOLATE);
else
value = FIELD_SET(value, CRT_DISPLAY_CTRL, HORIZONTAL_MODE, REPLICATE);
if (enableVertInterpolation)
value = FIELD_SET(value, CRT_DISPLAY_CTRL, VERTICAL_MODE, INTERPOLATE);
else
value = FIELD_SET(value, CRT_DISPLAY_CTRL, VERTICAL_MODE, REPLICATE);
pokeRegisterDWord(CRT_DISPLAY_CTRL, value);
}
/*
* This function un-register 2D Interrupt handler.
*/
int32_t unhookDEInterrupt(
uint32_t deMask,
void (*handler)(void)
)
{
de_interrupt_t *pfnHandler, *prev;
uint32_t mask;
if (deMask == 0)
mask = FIELD_SET(0, DE_STATUS, 2D, ACTIVE);
else
mask = FIELD_SET(0, DE_STATUS, CSC, ACTIVE);
/* Find the requested handle to unregister */
for (pfnHandler = pDEIntHandlers, prev = ((de_interrupt_t *)0);
pfnHandler != ((de_interrupt_t *)0);
prev = pfnHandler, pfnHandler = pfnHandler->next)
{
if ((pfnHandler->deMask == mask) && (pfnHandler->handler == handler))
{
/* Remove the interrupt handler */
if (prev == ((de_interrupt_t *)0))
pDEIntHandlers = pfnHandler->next;
else
prev->next = pfnHandler->next;
free(pfnHandler);
/* If this was the last interrupt handler, remove the IRQ handler */
if (pDEIntHandlers == ((de_interrupt_t *)0))
unregisterHandler(deISR);
/* Success */
return (0);
}
}
/* Oops, handler is not registered */
return (-1);
}
/*
* This is the main interrupt hook for drawing engine.
* It hooks 2D and CSC engine.
* Note:
* To hook 2D Engine, use hook2DInterrupt.
* To hook CSC Engine, use hookCSCInterrupt.
*/
int32_t hookDEInterrupt(
uint32_t deMask,
void (*handler)(void)
)
{
de_interrupt_t *pfnNewHandler, *pfnHandler;
unsigned short returnValue = 0;
/* Allocate a new interrupt structure */
pfnNewHandler = (de_interrupt_t *)malloc(sizeof(de_interrupt_t));
if (pfnNewHandler == ((de_interrupt_t *)0))
{
/* No more memory */
return (-1);
}
/* Make sure that it has not been register more than once */
for (pfnHandler = pDEIntHandlers; pfnHandler != ((de_interrupt_t *)0); pfnHandler = pfnHandler->next)
{
if (pfnHandler->handler == handler)
return (-1); /* Duplicate entry */
}
/* If this is the first interrupt handler, register this panel VSync ISR */
if (pDEIntHandlers == ((de_interrupt_t *)0))
returnValue = registerHandler(deISR, FIELD_SET(0, INT_MASK, DE, ENABLE));
if (returnValue == 0)
{
/* Fill interrupt structure. */
pfnNewHandler->next = pDEIntHandlers;
pfnNewHandler->handler = handler;
pfnNewHandler->deMask = (deMask == 0) ?
FIELD_SET(0, DE_STATUS, 2D, ACTIVE) :
FIELD_SET(0, DE_STATUS, CSC, ACTIVE);
pDEIntHandlers = pfnNewHandler;
}
return returnValue;
}
/*
* This function set up the master clock (MCLK).
*
* Input: Frequency to be set.
*
* NOTE:
* The maximum frequency the engine can run is 168MHz.
*/
void setMasterClock(unsigned int frequency)
{
unsigned int ulReg, divisor;
#if 1
/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
if (getChipType() == SM750LE)
return;
#endif
if (frequency != 0)
{
/* Set the frequency to the maximum frequency that the SM750 engine can
run, which is about 190 MHz. */
if (frequency > MHz(190))
frequency = MHz(190);
/* Calculate the divisor */
divisor = (unsigned int) roundedDiv(getChipClock(), frequency);
/* Set the corresponding divisor in the register. */
ulReg = PEEK32(CURRENT_GATE);
switch(divisor)
{
default:
case 3:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_3);
break;
case 4:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_4);
break;
case 6:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_6);
break;
case 8:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_8);
break;
}
setCurrentGate(ulReg);
}
}
/*
* This function sets the panel type
*
* Input:
* panelType - The type of the panel to be set
*/
long setPanelType(
panel_type_t panelType
)
{
unsigned long value;
#if 0
/* monk note below*/
/* Setting to TFT_18BIT will force the display to Dual Panel Display. */
if ((panelType == TFT_18BIT) && (isDualPanelEnable() == 0))
setDualPanel(1);
else
setDualPanel(0);
#endif
/* Set the panel type. */
value = peekRegisterDWord(PANEL_DISPLAY_CTRL);
switch (panelType)
{
case TFT_18BIT:
/* TFT 18-bit is the same as TFT 24-bit with the exception that this
setting is only used in Dual Panel. Note: there is no break here. */
value = FIELD_SET(value,PANEL_DISPLAY_CTRL,DUAL_DISPLAY,ENABLE);
case TFT_24BIT:
value = FIELD_SET(value, PANEL_DISPLAY_CTRL, DOUBLE_PIXEL, DISABLE);
break;
case TFT_36BIT:
value = FIELD_SET(value, PANEL_DISPLAY_CTRL, DOUBLE_PIXEL, ENABLE);
break;
default:
return (-1);
}
pokeRegisterDWord(PANEL_DISPLAY_CTRL, value);
return 0;
}
/*
* This function reads data from the slave device and stores them
* in the given buffer
*
* Parameters:
* deviceAddress - i2c Slave device address
* length - Total number of bytes to be read
* pBuffer - Pointer to a buffer to be filled with the data read
* from the slave device. It has to be the same size as the
* length to make sure that it can keep all the data read.
*
* Return Value:
* Total number of actual bytes read from the slave device
*/
unsigned long hwI2CReadData(
unsigned char deviceAddress,
unsigned long length,
unsigned char *pBuffer
)
{
unsigned char value, count, i;
unsigned long totalBytes = 0;
/* Set the Device Address */
pokeRegisterByte(I2C_SLAVE_ADDRESS, deviceAddress | 0x01);
/* Read data and save them to the buffer.
* Note:
* Only 16 byte can be accessed per i2c start instruction.
*/
do
{
/* Reset I2C by writing 0 to I2C_RESET register to clear all the status. */
pokeRegisterByte(I2C_RESET, 0);
/* Set the number of bytes to be read */
if (length <= MAX_HWI2C_FIFO)
count = length - 1;
else
count = MAX_HWI2C_FIFO - 1;
pokeRegisterByte(I2C_BYTE_COUNT, count);
/* Start the I2C */
pokeRegisterByte(I2C_CTRL, FIELD_SET(peekRegisterByte(I2C_CTRL), I2C_CTRL, CTRL, START));
/* Wait until transaction done. */
if (hwI2CWaitTXDone() != 0)
break;
/* Save the data to the given buffer */
for (i = 0; i <= count; i++)
*pBuffer++ = peekRegisterByte(I2C_DATA0 + i);
/* Substract length by 16 */
length -= (count + 1);
/* Number of bytes read. */
totalBytes += (count + 1);
} while (length > 0);
return totalBytes;
}