/** * fm10k_update_hw_stats_rx_q - Updates RX queue statistics counters * @hw: pointer to the hardware structure * @q: pointer to the ring of hardware statistics queue * @idx: index pointing to the start of the ring iteration * * Function updates the RX queue statistics counters that are related to the * hardware. **/ static void fm10k_update_hw_stats_rx_q(struct fm10k_hw *hw, struct fm10k_hw_stats_q *q, u32 idx) { u32 id_rx, id_rx_prev, rx_packets, rx_drops; u64 rx_bytes = 0; /* Retrieve RX Owner Data */ id_rx = fm10k_read_reg(hw, FM10K_RXQCTL(idx)); /* Process RX Ring */ do { rx_drops = fm10k_read_hw_stats_32b(hw, FM10K_QPRDC(idx), &q->rx_drops); rx_packets = fm10k_read_hw_stats_32b(hw, FM10K_QPRC(idx), &q->rx_packets); if (rx_packets) rx_bytes = fm10k_read_hw_stats_48b(hw, FM10K_QBRC_L(idx), &q->rx_bytes); /* Re-Check Owner Data */ id_rx_prev = id_rx; id_rx = fm10k_read_reg(hw, FM10K_RXQCTL(idx)); } while ((id_rx ^ id_rx_prev) & FM10K_RXQCTL_ID_MASK); /* drop non-ID bits and set VALID ID bit */ id_rx &= FM10K_RXQCTL_ID_MASK; id_rx |= FM10K_STAT_VALID; /* update packet counts */ if (q->rx_stats_idx == id_rx) { q->rx_drops.count += rx_drops; q->rx_packets.count += rx_packets; q->rx_bytes.count += rx_bytes; } /* update bases and record ID */ fm10k_update_hw_base_32b(&q->rx_drops, rx_drops); fm10k_update_hw_base_32b(&q->rx_packets, rx_packets); fm10k_update_hw_base_48b(&q->rx_bytes, rx_bytes); q->rx_stats_idx = id_rx; }
/** * fm10k_disable_queues_generic - Stop Tx/Rx queues * @hw: pointer to hardware structure * @q_cnt: number of queues to be disabled * **/ s32 fm10k_disable_queues_generic(struct fm10k_hw *hw, u16 q_cnt) { u32 reg; u16 i, time; /* clear tx_ready to prevent any false hits for reset */ hw->mac.tx_ready = false; /* clear the enable bit for all rings */ for (i = 0; i < q_cnt; i++) { reg = fm10k_read_reg(hw, FM10K_TXDCTL(i)); fm10k_write_reg(hw, FM10K_TXDCTL(i), reg & ~FM10K_TXDCTL_ENABLE); reg = fm10k_read_reg(hw, FM10K_RXQCTL(i)); fm10k_write_reg(hw, FM10K_RXQCTL(i), reg & ~FM10K_RXQCTL_ENABLE); } fm10k_write_flush(hw); udelay(1); /* loop through all queues to verify that they are all disabled */ for (i = 0, time = FM10K_QUEUE_DISABLE_TIMEOUT; time;) { /* if we are at end of rings all rings are disabled */ if (i == q_cnt) return 0; /* if queue enables cleared, then move to next ring pair */ reg = fm10k_read_reg(hw, FM10K_TXDCTL(i)); if (!~reg || !(reg & FM10K_TXDCTL_ENABLE)) { reg = fm10k_read_reg(hw, FM10K_RXQCTL(i)); if (!~reg || !(reg & FM10K_RXQCTL_ENABLE)) { i++; continue; } } /* decrement time and wait 1 usec */ time--; if (time) udelay(1); } return FM10K_ERR_REQUESTS_PENDING; }
static void fm10k_get_reg_q(struct fm10k_hw *hw, u32 *buff, int i) { int idx = 0; buff[idx++] = fm10k_read_reg(hw, FM10K_RDBAL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_RDBAH(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_RDLEN(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TPH_RXCTRL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_RDH(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_RDT(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_RXQCTL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_RXDCTL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_RXINT(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_SRRCTL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_QPRC(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_QPRDC(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_QBRC_L(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_QBRC_H(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TDBAL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TDBAH(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TDLEN(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TPH_TXCTRL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TDH(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TDT(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TXDCTL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TXQCTL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TXINT(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_QPTC(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_QBTC_L(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_QBTC_H(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TQDLOC(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TX_SGLORT(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_PFVTCTL(i)); BUG_ON(idx != FM10K_REGS_LEN_Q); }