static void cmd_normal(BaseSequentialStream *chp, int argc, char *argv[]) { (void)argv; FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; if (argc > 0) { chprintf(chp, "Usage: normal\r\n"); return; } /* Program a self-refresh mode command */ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_normal; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; /* Send the command */ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Wait until the SDRAM controller is ready */ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) { } /* Check the bank mode status */ if(FMC_GetModeStatus(FMC_Bank2_SDRAM) != FMC_NormalMode_Status) { chprintf(chp, "SDRAM is not in normal mode, command FAILED.\r\n"); } else { chprintf(chp, "SDRAM is in normal mode.\r\n"); } }
/** * @brief FMC SDRAM Configuration * @param None * @retval None */ static void FMC_Config(void) { GPIO_InitTypeDef GPIO_InitStructure; FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure; FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure; FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; uint32_t tmpr = 0; uint32_t timeout = SDRAM_TIMEOUT; /* GPIO configuration ------------------------------------------------------*/ /* Enable GPIOs clock */ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOH | RCC_AHB1Periph_GPIOI, ENABLE); /* Common GPIO configuration */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; /* GPIOD configuration */ GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC); GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC); GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC); GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC); GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC); GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC); GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 |GPIO_Pin_1 |GPIO_Pin_8 |GPIO_Pin_9 | GPIO_Pin_10 |GPIO_Pin_14 |GPIO_Pin_15; GPIO_Init(GPIOD, &GPIO_InitStructure); /* GPIOE configuration */ GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11| GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; GPIO_Init(GPIOE, &GPIO_InitStructure); /* GPIOF configuration */ GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; GPIO_Init(GPIOF, &GPIO_InitStructure); /* GPIOG configuration */ GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 |GPIO_Pin_1 |GPIO_Pin_4 |GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15; GPIO_Init(GPIOG, &GPIO_InitStructure); /* GPIOH configuration */ GPIO_PinAFConfig(GPIOH, GPIO_PinSource2 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOH, GPIO_PinSource3 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOH, GPIO_PinSource5 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOH, GPIO_PinSource8 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOH, GPIO_PinSource9 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOH, GPIO_PinSource10 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOH, GPIO_PinSource11 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOH, GPIO_PinSource12 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOH, GPIO_PinSource13 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOH, GPIO_PinSource14 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOH, GPIO_PinSource15 , GPIO_AF_FMC); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; GPIO_Init(GPIOH, &GPIO_InitStructure); /* GPIOI configuration */ GPIO_PinAFConfig(GPIOI, GPIO_PinSource0 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOI, GPIO_PinSource1 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOI, GPIO_PinSource2 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOI, GPIO_PinSource3 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOI, GPIO_PinSource4 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOI, GPIO_PinSource5 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOI, GPIO_PinSource6 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOI, GPIO_PinSource7 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOI, GPIO_PinSource9 , GPIO_AF_FMC); GPIO_PinAFConfig(GPIOI, GPIO_PinSource10 , GPIO_AF_FMC); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_9 | GPIO_Pin_10; GPIO_Init(GPIOI, &GPIO_InitStructure); /* Enable FMC clock */ RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); /* FMC SDRAM device initialization sequence --------------------------------*/ /* Step 1 ----------------------------------------------------*/ /* Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) */ /* TMRD: 2 Clock cycles */ FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2; /* TXSR: min=70ns (6x11.90ns) */ FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6; /* TRAS: min=42ns (4x11.90ns) max=120k (ns) */ FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4; /* TRC: min=70 (6x11.90ns) */ FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6; /* TWR: min=1+ 7ns (1+1x11.90ns) */ FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2; /* TRP: 20ns => 2x11.90ns */ FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2; /* TRCD: 20ns => 2x11.90ns */ FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; /* Step 2 ----------------------------------------------------*/ /* FMC SDRAM control configuration */ FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank1_SDRAM; /* Row addressing: [7:0] */ FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; /* Column addressing: [10:0] */ FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b; FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH; FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4; /* CL: Cas Latency = 3 clock cycles */ FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3; FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable; FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD; FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_Enable; FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1; FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure; /* FMC SDRAM bank initialization */ FMC_SDRAMInit(&FMC_SDRAMInitStructure); /* Step 3 --------------------------------------------------------------------*/ /* Configure a clock configuration enable command */ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; /* Wait until the SDRAM controller is ready */ while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) { timeout--; } /* Send the command */ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Step 4 --------------------------------------------------------------------*/ /* Insert 100 ms delay */ Delay(10); /* Step 5 --------------------------------------------------------------------*/ /* Configure a PALL (precharge all) command */ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; /* Wait until the SDRAM controller is ready */ timeout = SDRAM_TIMEOUT; while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) { timeout--; } /* Send the command */ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Step 6 --------------------------------------------------------------------*/ /* Configure a Auto-Refresh command */ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 8; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; /* Wait until the SDRAM controller is ready */ timeout = SDRAM_TIMEOUT; while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) { timeout--; } /* Send the command */ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Step 7 --------------------------------------------------------------------*/ /* Program the external memory mode register */ tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 | SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | SDRAM_MODEREG_CAS_LATENCY_3 | SDRAM_MODEREG_OPERATING_MODE_STANDARD | SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; /* Configure a load Mode register command*/ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; /* Wait until the SDRAM controller is ready */ timeout = SDRAM_TIMEOUT; while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) { timeout--; } /* Send the command */ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Step 8 --------------------------------------------------------------------*/ /* Set the refresh rate counter */ /* (7.81 us x Freq) - 20 */ /* Set the device refresh counter */ FMC_SetRefreshCount(636); /* Wait until the SDRAM controller is ready */ timeout = SDRAM_TIMEOUT; while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) { timeout--; } }
/** * @brief Executes the SDRAM memory initialization sequence. * @param None. * @retval None. */ void SDRAM_InitSequence(void) { FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; uint32_t tmpr = 0; /* Step 3 --------------------------------------------------------------------*/ /* Configure a clock configuration enable command */ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; /* Wait until the SDRAM controller is ready */ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) { } /* Send the command */ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Step 4 --------------------------------------------------------------------*/ /* Insert 100 ms delay */ __Delay(10); /* Step 5 --------------------------------------------------------------------*/ /* Configure a PALL (precharge all) command */ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; /* Wait until the SDRAM controller is ready */ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) { } /* Send the command */ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Step 6 --------------------------------------------------------------------*/ /* Configure a Auto-Refresh command */ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; /* Wait until the SDRAM controller is ready */ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) { } /* Send the first command */ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Wait until the SDRAM controller is ready */ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) { } /* Send the second command */ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Step 7 --------------------------------------------------------------------*/ /* Program the external memory mode register */ tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 | SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | SDRAM_MODEREG_CAS_LATENCY_3 | SDRAM_MODEREG_OPERATING_MODE_STANDARD | SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; /* Configure a load Mode register command*/ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; /* Wait until the SDRAM controller is ready */ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) { } /* Send the command */ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Step 8 --------------------------------------------------------------------*/ /* Set the refresh rate counter */ /* (15.62 us x Freq) - 20 */ /* Set the device refresh counter */ FMC_SetRefreshCount(1386); /* Wait until the SDRAM controller is ready */ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) { } }
//-------------------------------------------------------------- // interne Funktion // Initsequenz fuer das SDRAM //-------------------------------------------------------------- void P_SDRAM_InitSequence(void) { FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; uint32_t tmpr = 0; FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET); FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); P_SDRAM_delay(10); FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET); FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET); FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET); FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 | SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | SDRAM_MODEREG_CAS_LATENCY_3 | SDRAM_MODEREG_OPERATING_MODE_STANDARD | SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET); FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); //----------------------------------------------- // FMC_CLK = 90MHz // Refresh_Rate = 7.81us // Counter = (FMC_CLK * Refresh_Rate) - 20 //----------------------------------------------- FMC_SetRefreshCount(683); while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET); }
/** * @brief Executes the SDRAM memory initialization sequence. * @param None. * @retval None. */ void SDRAM_InitSequence(void) { FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; uint32_t tmpr = 0; /* Step 3 --------------------------------------------------------------------*/ /* Configure a clock configuration enable command */ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; /* Wait until the SDRAM controller is ready */ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) { } /* Send the command */ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); //In the ST example, this is 100ms, but the 429 RM says 100us is typical, and //the ISSI datasheet confirms this. 1ms seems plenty, and is much shorter than //refresh interval, meaning we won't risk losing contents if the SDRAM is in self-refresh //mode /* Step 4 --------------------------------------------------------------------*/ /* Insert 1 ms delay */ chThdSleepMilliseconds(1); /* Step 5 --------------------------------------------------------------------*/ /* Configure a PALL (precharge all) command */ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; /* Wait until the SDRAM controller is ready */ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) { } /* Send the command */ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Step 6 --------------------------------------------------------------------*/ /* Configure a Auto-Refresh command */ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; /* Wait until the SDRAM controller is ready */ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) { } /* Send the first command */ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Wait until the SDRAM controller is ready */ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) { } /* Send the second command */ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Step 7 --------------------------------------------------------------------*/ /* Program the external memory mode register */ tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 | SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | SDRAM_MODEREG_CAS_LATENCY_3 | SDRAM_MODEREG_OPERATING_MODE_STANDARD | SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; /* Configure a load Mode register command*/ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; /* Wait until the SDRAM controller is ready */ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) { } /* Send the command */ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Step 8 --------------------------------------------------------------------*/ /* Set the refresh rate counter */ /* (7.81 us x Freq) - 20 */ /* Set the device refresh counter */ FMC_SetRefreshCount(683); /* Wait until the SDRAM controller is ready */ while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) { } }
/** * @brief 对SDRAM芯片进行初始化配置 * @param None. * @retval None. */ static void SDRAM_InitSequence(void) { FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; uint32_t tmpr = 0; /* Step 3 --------------------------------------------------------------------*/ /* 配置命令:开启提供给SDRAM的时钟 */ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_COMMAND_TARGET_BANK; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 0; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; /* 检查SDRAM标志,等待至SDRAM空闲 */ while(FMC_GetFlagStatus(FMC_BANK_SDRAM, FMC_FLAG_Busy) != RESET) { } /* 发送上述命令*/ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Step 4 --------------------------------------------------------------------*/ /* 延时 */ SDRAM_delay(10); /* Step 5 --------------------------------------------------------------------*/ /* 配置命令:对所有的bank预充电 */ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_COMMAND_TARGET_BANK; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 0; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; /* 检查SDRAM标志,等待至SDRAM空闲 */ while(FMC_GetFlagStatus(FMC_BANK_SDRAM, FMC_FLAG_Busy) != RESET) { } /* 发送上述命令*/ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Step 6 --------------------------------------------------------------------*/ /* 配置命令:自动刷新 */ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_COMMAND_TARGET_BANK; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 2; //2个自动刷新命令 FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; /* 检查SDRAM标志,等待至SDRAM空闲 */ while(FMC_GetFlagStatus(FMC_BANK_SDRAM, FMC_FLAG_Busy) != RESET) { } /* 发送自动刷新命令*/ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Step 7 --------------------------------------------------------------------*/ /* 设置sdram寄存器配置 */ tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_8 | SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | SDRAM_MODEREG_CAS_LATENCY_2 | SDRAM_MODEREG_OPERATING_MODE_STANDARD | SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; /* 配置命令:设置SDRAM寄存器 */ FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_COMMAND_TARGET_BANK; FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; /* 检查SDRAM标志,等待至SDRAM空闲 */ while(FMC_GetFlagStatus(FMC_BANK_SDRAM, FMC_FLAG_Busy) != RESET) { } /* 发送上述命令*/ FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); /* Step 8 --------------------------------------------------------------------*/ /* 设置刷新计数器 */ /*刷新速率 = (COUNT + 1) x SDRAM 频率时钟 COUNT =( SDRAM 刷新周期/行数) - 20*/ /* 64ms/4096=15.62us (15.62 us x FSDCLK) - 20 =1386 */ FMC_SetRefreshCount(1386); /* 发送上述命令*/ while(FMC_GetFlagStatus(FMC_BANK_SDRAM, FMC_FLAG_Busy) != RESET) { } }