/**
* @brief Configures the FSMC and GPIOs to interface with the NAND memory.
* This function must be called before any write/read operation on the
* NAND.
* @param None
* @retval None
*/
void NAND_Init(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
FSMC_NAND_PCCARDTimingInitTypeDef p;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
/*-- GPIO Configuration ------------------------------------------------------*/
/*!< CLE, ALE, D0->D3, NOE, NWE and NCE2 NAND pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 |
GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
GPIO_Pin_7;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/*!< D4->D7 NAND pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
GPIO_Init(GPIOE, &GPIO_InitStructure);
/*!< NWAIT NAND pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/*!< INT2 NAND pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_Init(GPIOG, &GPIO_InitStructure);
/*-- FSMC Configuration ------------------------------------------------------*/
p.FSMC_SetupTime = 0x0;
p.FSMC_WaitSetupTime = 0x2;
p.FSMC_HoldSetupTime = 0x1;
p.FSMC_HiZSetupTime = 0x0;
FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable;
FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
FSMC_NANDInit(&FSMC_NANDInitStructure);
/*!< FSMC NAND Bank Cmd Test */
FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
}
/**
* @brief Configures the FSMC and GPIOs to interface with the NAND memory.
* This function must be called before any write/read operation on the
* NAND.
* @param None
* @retval None
*/
void NAND_Init(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
FSMC_NAND_PCCARDTimingInitTypeDef p;
FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
/*FSMC总线使用的GPIO组时钟使能*/
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
/*FSMC CLE, ALE, D0->D3, NOE, NWE and NCE2初始化，推挽复用输出*/
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 |
GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
GPIO_Pin_7;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/*FSMC数据线FSMC_D[4:7]初始化，推挽复用输出*/
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
GPIO_Init(GPIOE, &GPIO_InitStructure);
/*FSMC NWAIT初始化，输入上拉*/
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/*FSMC INT2初始化，输入上拉*/
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_Init(GPIOG, &GPIO_InitStructure);
/*--------------FSMC 总线 存储器参数配置------------------------------*/
p.FSMC_SetupTime = 0x1; //建立时间
p.FSMC_WaitSetupTime = 0x3; //等待时间
p.FSMC_HoldSetupTime = 0x2; //保持时间
p.FSMC_HiZSetupTime = 0x1; //高阻建立时间
FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND; //使用FSMC BANK2
FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable; //使能FSMC的等待功能
FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; //NAND Flash的数据宽度为8位
FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable; //使能ECC特性
FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_2048Bytes; //ECC页大小2048
FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
FSMC_NANDInit(&FSMC_NANDInitStructure);
/*!使能FSMC BANK2 */
FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
}
void BSP_NAND_Init (void)
{
GPIO_InitTypeDef gpio_init;
FSMC_NANDInitTypeDef nand_init;
FSMC_NAND_PCCARDTimingInitTypeDef p;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
/* ---------------------- CFG GPIO -------------------- */
/* CLE, ALE, D0..3, NOW, NWE & NCE2 NAND pin cfg. */
gpio_init.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 |
GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_7;
gpio_init.GPIO_Speed = GPIO_Speed_50MHz;
gpio_init.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOD, &gpio_init);
/* D4..7 NAND pin configuration. */
gpio_init.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
GPIO_Init(GPIOE, &gpio_init);
/* NWAIT NAND pin configuration. */
gpio_init.GPIO_Pin = GPIO_Pin_6;
gpio_init.GPIO_Speed = GPIO_Speed_50MHz;
gpio_init.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &gpio_init);
/* INT2 NAND pin configuration. */
gpio_init.GPIO_Pin = GPIO_Pin_6;
GPIO_Init(GPIOG, &gpio_init);
/* ---------------------- CFG FSMC -------------------- */
p.FSMC_SetupTime = 0x1;
p.FSMC_WaitSetupTime = 0x3;
p.FSMC_HoldSetupTime = 0x2;
p.FSMC_HiZSetupTime = 0x1;
nand_init.FSMC_Bank = FSMC_Bank2_NAND;
nand_init.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
nand_init.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
nand_init.FSMC_ECC = FSMC_ECC_Enable;
nand_init.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
nand_init.FSMC_AddressLowMapping = FSMC_AddressLowMapping_Direct;
nand_init.FSMC_TCLRSetupTime = 0x00;
nand_init.FSMC_TARSetupTime = 0x00;
nand_init.FSMC_CommonSpaceTimingStruct = &p;
nand_init.FSMC_AttributeSpaceTimingStruct = &p;
FSMC_NANDInit(&nand_init);
FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE); /* FSMC NAND bank cmd test. */
}
/*******************************************************************************
* Function Name : FSMC_NOR_Init
* Description : Configures the FSMC and GPIOs to interface with the NOR memory.
* This function must be called before any write/read operation
* on the NOR.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void stm32_FsmcInit()
{
FSMC_NORSRAMInitTypeDef xNor;
FSMC_NORSRAMTimingInitTypeDef xNorWriteTiming, xNorReadTiming;
#if NANDFLASH_ENABLE
FSMC_NANDInitTypeDef xNand;
FSMC_NAND_PCCARDTimingInitTypeDef xNandWriteTiming, xNandReadTiming;
#endif
GPIO_InitTypeDef xGpio;
u32 nBank;
/*-- GPIO Configuration ------------------------------------------------------*/
RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
xGpio.GPIO_Speed = GPIO_Speed_50MHz;
xGpio.GPIO_Mode = GPIO_Mode_Out_PP;
xGpio.GPIO_Pin = GPIO_Pin_7;
GPIO_Init(GPIOD, &xGpio);
GPIO_SetBits(GPIOD, xGpio.GPIO_Pin);
xGpio.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_12;
GPIO_Init(GPIOG, &xGpio);
GPIO_SetBits(GPIOG, xGpio.GPIO_Pin);
xGpio.GPIO_Mode = GPIO_Mode_AF_PP;
/* NOE and NWE configuration */
xGpio.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
GPIO_Init(GPIOD, &xGpio);
/* D0-D15 lines configuration */
xGpio.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_Init(GPIOD, &xGpio);
xGpio.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
GPIO_Pin_14 | GPIO_Pin_15;
GPIO_Init(GPIOE, &xGpio);
/* Address lines configuration */
xGpio.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
GPIO_Pin_14 | GPIO_Pin_15;
GPIO_Init(GPIOF, &xGpio);
xGpio.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_13 | GPIO_Pin_14;
GPIO_Init(GPIOG, &xGpio);
xGpio.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
GPIO_Init(GPIOD, &xGpio);
xGpio.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6;
GPIO_Init(GPIOE, &xGpio);
#if EXTSRAM_ENABLE
xGpio.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1;
GPIO_Init(GPIOE, &xGpio);
#endif
#if NANDFLASH_ENABLE
xGpio.GPIO_Mode = GPIO_Mode_IPU;
/* NWAIT NAND pin configuration */
xGpio.GPIO_Pin = GPIO_Pin_6;
GPIO_Init(GPIOD, &xGpio);
#endif
/* FSMC Clock Enable */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
#if NORFLASH_ENABLE
nBank = stm32_Bank(NORFLASH_BASE_ADR);
/*-- FSMC Configuration ----------------------------------------------------*/
xNorReadTiming.FSMC_AddressSetupTime = 1;
xNorReadTiming.FSMC_AddressHoldTime = 0;
xNorReadTiming.FSMC_DataSetupTime = 5;
xNorReadTiming.FSMC_BusTurnAroundDuration = 0;
xNorReadTiming.FSMC_CLKDivision = 0;
xNorReadTiming.FSMC_DataLatency = 0;
xNorReadTiming.FSMC_AccessMode = FSMC_AccessMode_B;
xNorWriteTiming.FSMC_AddressSetupTime = 1;
xNorWriteTiming.FSMC_AddressHoldTime = 0;
xNorWriteTiming.FSMC_DataSetupTime = 5;
xNorWriteTiming.FSMC_BusTurnAroundDuration = 0;
xNorWriteTiming.FSMC_CLKDivision = 0;
xNorWriteTiming.FSMC_DataLatency = 0;
xNorWriteTiming.FSMC_AccessMode = FSMC_AccessMode_B;
xNor.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
xNor.FSMC_MemoryType = FSMC_MemoryType_NOR;
xNor.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
xNor.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
xNor.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
xNor.FSMC_WrapMode = FSMC_WrapMode_Disable;
xNor.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
xNor.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
xNor.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
xNor.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
xNor.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
xNor.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
xNor.FSMC_ReadWriteTimingStruct = &xNorReadTiming;
xNor.FSMC_WriteTimingStruct = &xNorWriteTiming;
xNor.FSMC_Bank = nBank;
FSMC_NORSRAMInit(&xNor);
FSMC_NORSRAMCmd(nBank, ENABLE);
#endif
#if EXTSRAM_ENABLE
nBank = stm32_Bank(EXTSRAM_BASE_ADR);
/*-- FSMC Configuration ----------------------------------------------------*/
xNorReadTiming.FSMC_AddressSetupTime = 0;
xNorReadTiming.FSMC_AddressHoldTime = 0;
xNorReadTiming.FSMC_DataSetupTime = 2;
xNorReadTiming.FSMC_BusTurnAroundDuration = 0;
xNorReadTiming.FSMC_CLKDivision = 0;
xNorReadTiming.FSMC_DataLatency = 0;
xNorReadTiming.FSMC_AccessMode = FSMC_AccessMode_A;
xNorWriteTiming.FSMC_AddressSetupTime = 0;
xNorWriteTiming.FSMC_AddressHoldTime = 0;
xNorWriteTiming.FSMC_DataSetupTime = 2;
xNorWriteTiming.FSMC_BusTurnAroundDuration = 0;
xNorWriteTiming.FSMC_CLKDivision = 0;
xNorWriteTiming.FSMC_DataLatency = 0;
xNorWriteTiming.FSMC_AccessMode = FSMC_AccessMode_A;
xNor.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
xNor.FSMC_MemoryType = FSMC_MemoryType_SRAM;
xNor.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
xNor.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
xNor.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
xNor.FSMC_WrapMode = FSMC_WrapMode_Disable;
xNor.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
xNor.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
xNor.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
xNor.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
xNor.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
xNor.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
xNor.FSMC_ReadWriteTimingStruct = &xNorReadTiming;
xNor.FSMC_WriteTimingStruct = &xNorWriteTiming;
xNor.FSMC_Bank = nBank;
FSMC_NORSRAMInit(&xNor);
FSMC_NORSRAMCmd(nBank, ENABLE);
#endif
#if GUI_ENABLE
nBank = stm32_Bank(GUI_LCD_BASE_ADR);
/*-- FSMC Configuration ----------------------------------------------------*/
xNorReadTiming.FSMC_AddressSetupTime = 0;
xNorReadTiming.FSMC_AddressHoldTime = 0;
xNorReadTiming.FSMC_DataSetupTime = 2;
xNorReadTiming.FSMC_BusTurnAroundDuration = 0;
xNorReadTiming.FSMC_CLKDivision = 0;
xNorReadTiming.FSMC_DataLatency = 0;
xNorReadTiming.FSMC_AccessMode = FSMC_AccessMode_A;
xNorWriteTiming.FSMC_AddressSetupTime = 0;
xNorWriteTiming.FSMC_AddressHoldTime = 0;
xNorWriteTiming.FSMC_DataSetupTime = 2;
xNorWriteTiming.FSMC_BusTurnAroundDuration = 0;
xNorWriteTiming.FSMC_CLKDivision = 0;
xNorWriteTiming.FSMC_DataLatency = 0;
xNorWriteTiming.FSMC_AccessMode = FSMC_AccessMode_A;
xNor.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
xNor.FSMC_MemoryType = FSMC_MemoryType_SRAM;
xNor.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
xNor.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
xNor.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
xNor.FSMC_WrapMode = FSMC_WrapMode_Disable;
xNor.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
xNor.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
xNor.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
xNor.FSMC_ExtendedMode = FSMC_ExtendedMode_Enable;
xNor.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
xNor.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
xNor.FSMC_ReadWriteTimingStruct = &xNorReadTiming;
xNor.FSMC_WriteTimingStruct = &xNorWriteTiming;
xNor.FSMC_Bank = nBank;
FSMC_NORSRAMInit(&xNor);
FSMC_NORSRAMCmd(nBank, ENABLE);
#endif
#if DM9000_ENABLE
nBank = stm32_Bank(DM9000_BASE_ADR);
/*-- FSMC Configuration ----------------------------------------------------*/
xNorReadTiming.FSMC_AddressSetupTime = 0;
xNorReadTiming.FSMC_AddressHoldTime = 0;
xNorReadTiming.FSMC_DataSetupTime = 2;
xNorReadTiming.FSMC_BusTurnAroundDuration = 0;
xNorReadTiming.FSMC_CLKDivision = 0;
xNorReadTiming.FSMC_DataLatency = 0;
xNorReadTiming.FSMC_AccessMode = FSMC_AccessMode_A;
xNorWriteTiming.FSMC_AddressSetupTime = 0;
xNorWriteTiming.FSMC_AddressHoldTime = 0;
xNorWriteTiming.FSMC_DataSetupTime = 2;
xNorWriteTiming.FSMC_BusTurnAroundDuration = 0;
xNorWriteTiming.FSMC_CLKDivision = 0;
xNorWriteTiming.FSMC_DataLatency = 0;
xNorWriteTiming.FSMC_AccessMode = FSMC_AccessMode_A;
xNor.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
xNor.FSMC_MemoryType = FSMC_MemoryType_SRAM;
xNor.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
xNor.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
xNor.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
xNor.FSMC_WrapMode = FSMC_WrapMode_Disable;
xNor.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
xNor.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
xNor.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
xNor.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
xNor.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
xNor.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
xNor.FSMC_ReadWriteTimingStruct = &xNorReadTiming;
xNor.FSMC_WriteTimingStruct = &xNorWriteTiming;
xNor.FSMC_Bank = nBank;
FSMC_NORSRAMInit(&xNor);
FSMC_NORSRAMCmd(nBank, ENABLE);
#endif
#if NANDFLASH_ENABLE
nBank = stm32_Bank(NAND_BASE_ADR);
/*-- FSMC Configuration ------------------------------------------------------*/
xNandReadTiming.FSMC_SetupTime = 1;
xNandReadTiming.FSMC_WaitSetupTime = 3;
xNandReadTiming.FSMC_HoldSetupTime = 2;
xNandReadTiming.FSMC_HiZSetupTime = 1;
xNandWriteTiming.FSMC_SetupTime = 1;
xNandWriteTiming.FSMC_WaitSetupTime = 3;
xNandWriteTiming.FSMC_HoldSetupTime = 2;
xNandWriteTiming.FSMC_HiZSetupTime = 1;
xNand.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
#if NAND_DATA_WIDTH == 16
xNand.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
#else
xNand.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
#endif
xNand.FSMC_ECC = FSMC_ECC_Disable;
#if NAND_PAGE_DATA == 2048
xNand.FSMC_ECCPageSize = FSMC_ECCPageSize_2048Bytes;
#else
xNand.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
#endif
xNand.FSMC_TCLRSetupTime = 0x00;
xNand.FSMC_TARSetupTime = 0x00;
xNand.FSMC_CommonSpaceTimingStruct = &xNandReadTiming;
xNand.FSMC_AttributeSpaceTimingStruct = &xNandWriteTiming;
xNand.FSMC_Bank = nBank;
FSMC_NANDInit(&xNand);
FSMC_NANDCmd(nBank, ENABLE);
#endif
}
void stm32_FsmcInit()
{
FSMC_NORSRAMInitTypeDef xNor;
FSMC_NORSRAMTimingInitTypeDef xNorWriteTiming, xNorReadTiming;
#if NANDFLASH_ENABLE
FSMC_NANDInitTypeDef xNand;
FSMC_NAND_PCCARDTimingInitTypeDef xNandWriteTiming, xNandReadTiming;
#endif
GPIO_InitTypeDef xGpio;
u32 nBank;
/* Enable GPIOs clock */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE |
RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOG, ENABLE);
/*-- GPIO Configuration ------------------------------------------------------*/
/*
+-------------------+--------------------+------------------+------------------+
+ SRAM pins assignment +
+-------------------+--------------------+------------------+------------------+
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
| PD4 <-> FSMC_NOE | PE2 <-> FSMC_A23 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
| PD5 <-> FSMC_NWE | PE3 <-> FSMC_A19 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
| PD8 <-> FSMC_D13 | PE4 <-> FSMC_A20 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
| PD9 <-> FSMC_D14 | PE5 <-> FSMC_A21 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
| PD10 <-> FSMC_D15 | PE6 <-> FSMC_A22 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
| PD11 <-> FSMC_A16 | PE7 <-> FSMC_D4 | PF13 <-> FSMC_A7 |------------------+
| PD12 <-> FSMC_A17 | PE8 <-> FSMC_D5 | PF14 <-> FSMC_A8 |------------------+
| PD13 <-> FSMC_A18 | PE9 <-> FSMC_D6 | PF15 <-> FSMC_A9 |------------------+
| PD14 <-> FSMC_D0 | PE10 <-> FSMC_D7 ------------------+
| PD15 <-> FSMC_D1 | PE11 <-> FSMC_D8 ------------------+
+------------------ | PE12 <-> FSMC_D9 ------------------+
+------------------ | PE13 <-> FSMC_D10 ------------------+
+------------------ | PE14 <-> FSMC_D11 ------------------+
+------------------ | PE15 <-> FSMC_D12 ------------------+
+-------------------+--------------------+
*/
/*-- GPIO ÅäÖÃ -----------------------------------------------------------*/
xGpio.GPIO_Mode = GPIO_Mode_AF;
xGpio.GPIO_Speed = GPIO_Speed_100MHz;
xGpio.GPIO_OType = GPIO_OType_PP;
xGpio.GPIO_PuPd = GPIO_PuPd_NOPULL;
xGpio.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_7 |
GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 |
GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
/* GPIOD configuration */
GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_FSMC); //FSMC_NOE
GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_FSMC); //FSMC_NWE
GPIO_PinAFConfig(GPIOD, GPIO_PinSource7, GPIO_AF_FSMC); //FSMC_NE1
GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource11, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource13, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FSMC);
GPIO_Init(GPIOD, &xGpio);
/* GPIOE configuration */
xGpio.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 |
GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 |
GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_PinAFConfig(GPIOE, GPIO_PinSource2 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource3 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource4 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource5 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource6 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FSMC);
GPIO_Init(GPIOE, &xGpio);
/* GPIOF configuration */
xGpio.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 |
GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FSMC);
GPIO_Init(GPIOF, &xGpio);
/* GPIOG configuration */
GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource2 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource3 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource9 , GPIO_AF_FSMC);
xGpio.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
GPIO_Pin_4 | GPIO_Pin_5 |GPIO_Pin_9;
GPIO_Init(GPIOG, &xGpio);
/* FSMC_NWAIT */
GPIO_PinAFConfig(GPIOD, GPIO_PinSource6 , GPIO_AF_FSMC);
xGpio.GPIO_Pin = GPIO_Pin_6;
xGpio.GPIO_Mode = GPIO_Mode_IN;
xGpio.GPIO_Speed = GPIO_Speed_100MHz;
xGpio.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOD, &xGpio);
#if EXTSRAM_ENABLE
#endif
#if NANDFLASH_ENABLE
#endif
/* FSMC Clock Enable */
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
#if NORFLASH_ENABLE
nBank = stm32_Bank(NORFLASH_BASE_ADR);
/*-- FSMC Configuration ----------------------------------------------------*/
xNorReadTiming.FSMC_AddressSetupTime = 5;
xNorReadTiming.FSMC_AddressHoldTime = 0;
xNorReadTiming.FSMC_DataSetupTime = 7;
xNorReadTiming.FSMC_BusTurnAroundDuration = 0;
xNorReadTiming.FSMC_CLKDivision = 0;
xNorReadTiming.FSMC_DataLatency = 0;
xNorReadTiming.FSMC_AccessMode = FSMC_AccessMode_B;
xNorWriteTiming.FSMC_AddressSetupTime = 5;
xNorWriteTiming.FSMC_AddressHoldTime = 0;
xNorWriteTiming.FSMC_DataSetupTime = 7;
xNorWriteTiming.FSMC_BusTurnAroundDuration = 0;
xNorWriteTiming.FSMC_CLKDivision = 0;
xNorWriteTiming.FSMC_DataLatency = 0;
xNorWriteTiming.FSMC_AccessMode = FSMC_AccessMode_B;
xNor.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
xNor.FSMC_MemoryType = FSMC_MemoryType_NOR;
xNor.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
xNor.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
xNor.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
xNor.FSMC_WrapMode = FSMC_WrapMode_Disable;
xNor.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
xNor.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
xNor.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
xNor.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
xNor.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
xNor.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
xNor.FSMC_ReadWriteTimingStruct = &xNorReadTiming;
xNor.FSMC_WriteTimingStruct = &xNorWriteTiming;
xNor.FSMC_Bank = nBank;
FSMC_NORSRAMInit(&xNor);
FSMC_NORSRAMCmd(nBank, ENABLE);
#endif
#if EXTSRAM_ENABLE
nBank = stm32_Bank(EXTSRAM_BASE_ADR);
/*-- FSMC Configuration ----------------------------------------------------*/
xNorReadTiming.FSMC_AddressSetupTime = 0;
xNorReadTiming.FSMC_AddressHoldTime = 0;
xNorReadTiming.FSMC_DataSetupTime = 2;
xNorReadTiming.FSMC_BusTurnAroundDuration = 0;
xNorReadTiming.FSMC_CLKDivision = 0;
xNorReadTiming.FSMC_DataLatency = 0;
xNorReadTiming.FSMC_AccessMode = FSMC_AccessMode_A;
xNorWriteTiming.FSMC_AddressSetupTime = 0;
xNorWriteTiming.FSMC_AddressHoldTime = 0;
xNorWriteTiming.FSMC_DataSetupTime = 2;
xNorWriteTiming.FSMC_BusTurnAroundDuration = 0;
xNorWriteTiming.FSMC_CLKDivision = 0;
xNorWriteTiming.FSMC_DataLatency = 0;
xNorWriteTiming.FSMC_AccessMode = FSMC_AccessMode_A;
xNor.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
xNor.FSMC_MemoryType = FSMC_MemoryType_SRAM;
xNor.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
xNor.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
xNor.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
xNor.FSMC_WrapMode = FSMC_WrapMode_Disable;
xNor.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
xNor.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
xNor.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
xNor.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
xNor.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
xNor.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
xNor.FSMC_ReadWriteTimingStruct = &xNorReadTiming;
xNor.FSMC_WriteTimingStruct = &xNorWriteTiming;
xNor.FSMC_Bank = nBank;
FSMC_NORSRAMInit(&xNor);
FSMC_NORSRAMCmd(nBank, ENABLE);
#endif
#if GUI_ENABLE
nBank = stm32_Bank(GUI_LCD_BASE_ADR);
/*-- FSMC Configuration ----------------------------------------------------*/
xNorReadTiming.FSMC_AddressSetupTime = 1;
xNorReadTiming.FSMC_AddressHoldTime = 0;
xNorReadTiming.FSMC_DataSetupTime = 9;
xNorReadTiming.FSMC_BusTurnAroundDuration = 0;
xNorReadTiming.FSMC_CLKDivision = 0;
xNorReadTiming.FSMC_DataLatency = 0;
xNorReadTiming.FSMC_AccessMode = FSMC_AccessMode_A;
xNorWriteTiming.FSMC_AddressSetupTime = 1;
xNorWriteTiming.FSMC_AddressHoldTime = 0;
xNorWriteTiming.FSMC_DataSetupTime = 9;
xNorWriteTiming.FSMC_BusTurnAroundDuration = 0;
xNorWriteTiming.FSMC_CLKDivision = 0;
xNorWriteTiming.FSMC_DataLatency = 0;
xNorWriteTiming.FSMC_AccessMode = FSMC_AccessMode_A;
xNor.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
xNor.FSMC_MemoryType = FSMC_MemoryType_SRAM;
xNor.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
xNor.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
xNor.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
xNor.FSMC_WrapMode = FSMC_WrapMode_Disable;
xNor.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
xNor.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
xNor.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
xNor.FSMC_ExtendedMode = FSMC_ExtendedMode_Enable;
xNor.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
xNor.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
xNor.FSMC_ReadWriteTimingStruct = &xNorReadTiming;
xNor.FSMC_WriteTimingStruct = &xNorWriteTiming;
xNor.FSMC_Bank = nBank;
FSMC_NORSRAMInit(&xNor);
FSMC_NORSRAMCmd(nBank, ENABLE);
#endif
#if DM9000_ENABLE
nBank = stm32_Bank(DM9000_BASE_ADR);
/*-- FSMC Configuration ----------------------------------------------------*/
xNorReadTiming.FSMC_AddressSetupTime = 0;
xNorReadTiming.FSMC_AddressHoldTime = 0;
xNorReadTiming.FSMC_DataSetupTime = 1;
xNorReadTiming.FSMC_BusTurnAroundDuration = 0;
xNorReadTiming.FSMC_CLKDivision = 0;
xNorReadTiming.FSMC_DataLatency = 0;
xNorReadTiming.FSMC_AccessMode = FSMC_AccessMode_A;
xNorWriteTiming.FSMC_AddressSetupTime = 0;
xNorWriteTiming.FSMC_AddressHoldTime = 0;
xNorWriteTiming.FSMC_DataSetupTime = 1;
xNorWriteTiming.FSMC_BusTurnAroundDuration = 0;
xNorWriteTiming.FSMC_CLKDivision = 0;
xNorWriteTiming.FSMC_DataLatency = 0;
xNorWriteTiming.FSMC_AccessMode = FSMC_AccessMode_A;
xNor.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
xNor.FSMC_MemoryType = FSMC_MemoryType_SRAM;
xNor.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
xNor.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
xNor.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
xNor.FSMC_WrapMode = FSMC_WrapMode_Disable;
xNor.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
xNor.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
xNor.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
xNor.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
xNor.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
xNor.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
xNor.FSMC_ReadWriteTimingStruct = &xNorReadTiming;
xNor.FSMC_WriteTimingStruct = &xNorWriteTiming;
xNor.FSMC_Bank = nBank;
FSMC_NORSRAMInit(&xNor);
FSMC_NORSRAMCmd(nBank, ENABLE);
#endif
#if NANDFLASH_ENABLE
nBank = stm32_Bank(NAND_BASE_ADR);
/*-- FSMC Configuration ------------------------------------------------------*/
xNandReadTiming.FSMC_SetupTime = 1;
xNandReadTiming.FSMC_WaitSetupTime = 3;
xNandReadTiming.FSMC_HoldSetupTime = 2;
xNandReadTiming.FSMC_HiZSetupTime = 1;
xNandWriteTiming.FSMC_SetupTime = 1;
xNandWriteTiming.FSMC_WaitSetupTime = 3;
xNandWriteTiming.FSMC_HoldSetupTime = 2;
xNandWriteTiming.FSMC_HiZSetupTime = 1;
xNand.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
#if NAND_DATA_WIDTH == 16
xNand.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
#else
xNand.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
#endif
xNand.FSMC_ECC = FSMC_ECC_Disable;
#if NAND_PAGE_DATA == 2048
xNand.FSMC_ECCPageSize = FSMC_ECCPageSize_2048Bytes;
#else
xNand.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
#endif
xNand.FSMC_AddressLowMapping = FSMC_AddressLowMapping_Direct;
xNand.FSMC_TCLRSetupTime = 0x00;
xNand.FSMC_TARSetupTime = 0x00;
xNand.FSMC_CommonSpaceTimingStruct = &xNandReadTiming;
xNand.FSMC_AttributeSpaceTimingStruct = &xNandWriteTiming;
xNand.FSMC_Bank = nBank;
FSMC_NANDInit(&xNand);
FSMC_NANDCmd(nBank, ENABLE);
#endif
}
/*******************************************************************************
* Function Name : FSMC_NAND_Init
* Description : Configures the FSMC and GPIOs to interface with the NAND memory.
* This function must be called before any write/read operation
* on the NAND.
******************************************************************************/
void FSMC_FPGA_Init(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
FSMC_NANDInitTypeDef FSMC_FPGAInitStructure;
FSMC_NAND_PCCARDTimingInitTypeDef p;
EXTI_InitTypeDef EXTI_InitStructure;
NVIC_InitTypeDef NVIC_InitStructure;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE , ENABLE);
RCC_AHB1PeriphClockCmd(DMA_FSMC_STREAM_CLOCK, ENABLE);
/*-- GPIO Configuration ------------------------------------------------------*/
/* CLE, ALE, D0->D3, NOE, NWE and NCE2 NAND pin configuration */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC,ENABLE);
/* D0->D3,*/
GPIO_PinAFConfig(GPIOD, GPIO_PinSource14 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource15 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource0 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource1 , GPIO_AF_FSMC);
/* D4->D7 NAND pin configuration */
GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FSMC);
/*-- GPIO NAND pin configuration ------------------------------------------------------*/
/* D0->D3 NAND pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 |GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* D4->D7 NAND pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
GPIO_Init(GPIOE, &GPIO_InitStructure);
/*ALE and CLE */
GPIO_PinAFConfig(GPIOD, GPIO_PinSource11 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource12 , GPIO_AF_FSMC);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/*NOE and NWE*/
GPIO_PinAFConfig(GPIOD, GPIO_PinSource4 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource5 , GPIO_AF_FSMC);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* CS */
GPIO_PinAFConfig(GPIOD, GPIO_PinSource7 , GPIO_AF_FSMC);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/*-- FSMC Configuration ------------------------------------------------------*/
p.FSMC_SetupTime = 0x01;
p.FSMC_WaitSetupTime = 0x03;
p.FSMC_HoldSetupTime = 0x02;
p.FSMC_HiZSetupTime = 0x01;
FSMC_FPGAInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
FSMC_FPGAInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Disable;
FSMC_FPGAInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
FSMC_FPGAInitStructure.FSMC_ECC = FSMC_ECC_Enable;
FSMC_FPGAInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_2048Bytes;
FSMC_FPGAInitStructure.FSMC_TCLRSetupTime = 0x15;
FSMC_FPGAInitStructure.FSMC_TARSetupTime = 0x15;
FSMC_FPGAInitStructure.FSMC_CommonSpaceTimingStruct = &p;
FSMC_FPGAInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
FSMC_NANDInit(&FSMC_FPGAInitStructure);
/* FSMC NAND Bank Cmd Test */
FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
/*NWAIT*/
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource6 , GPIO_AF_FSMC);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN ;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* Connect EXTI Line6 to PD6 pin */
SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOD, EXTI_PinSource6);
/* Configure EXTI Line6 */
EXTI_InitStructure.EXTI_Line = EXT_LINE_INT_FPGA ;
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_Init(&EXTI_InitStructure);
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
/* Enable and set EXTI Line6 Interrupt to the lowest priority */
NVIC_InitStructure.NVIC_IRQChannel = EXT_INT_FPGA_Channel ;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY+2;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
DMA_DeInit(DMA_FSMC_STREAM);
/* Settings DMA for read bufer */
DMA_FSMC_InitStructure.DMA_Channel = DMA_FSMC_CHANNEL;
DMA_FSMC_InitStructure.DMA_PeripheralBaseAddr = FPGA_FLASH_START_ADDR;
DMA_FSMC_InitStructure.DMA_Memory0BaseAddr = (uint32_t)input_bufer;
DMA_FSMC_InitStructure.DMA_DIR = DMA_DIR_MemoryToMemory;
DMA_FSMC_InitStructure.DMA_BufferSize = (uint32_t)BUFFER_SIZE;
DMA_FSMC_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Enable;
DMA_FSMC_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_FSMC_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_FSMC_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
DMA_FSMC_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_FSMC_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_FSMC_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_FSMC_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
DMA_FSMC_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_FSMC_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
DMA_Init(DMA_FSMC_STREAM, &DMA_FSMC_InitStructure);
DMA_ITConfig(DMA_FSMC_STREAM, DMA_FSMC_IT_TC, ENABLE);
NVIC_InitStructure.NVIC_IRQChannel = DMA_FSMC_STREAM_IRQ;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY+3;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
}
void FSMC_NAND_Init(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
FSMC_NAND_PCCARDTimingInitTypeDef p;
FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
/* Enable GPIOs clock */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF |
RCC_AHB1Periph_GPIOG, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
/* Enable FSMC clock */
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
/*-- GPIOs Configuration ------------------------------------------------------*/
/* GPIOD configuration */
GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC);/*FSMC_D2*/
GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC);/*FSMC_D3*/
GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_FSMC);/*FSMC_NOE*/
GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_FSMC);/*FSMC_NWE*/
GPIO_PinAFConfig(GPIOD, GPIO_PinSource7, GPIO_AF_FSMC);/*FSMC_NCE2*/
GPIO_PinAFConfig(GPIOD, GPIO_PinSource11, GPIO_AF_FSMC);/*FSMC_A16*/
GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_FSMC);/*FSMC_A17*/
GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FSMC);/*FSMC_D0*/
GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FSMC);/*FSMC_D1*/
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
GPIO_Pin_7 | GPIO_Pin_11 |
GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOD, &GPIO_InitStructure);
//GPIO_PinAFConfig(GPIOD, GPIO_PinSource6, GPIO_AF_FSMC);/*FSMC_NWAIT*/
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* GPIOE configuration */
GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FSMC);/*FSMC_D4*/
GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FSMC);/*FSMC_D5*/
GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FSMC);/*FSMC_D6*/
GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FSMC);/*FSMC_D7*/
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 |GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOE, &GPIO_InitStructure);
p.FSMC_SetupTime = 64;
p.FSMC_WaitSetupTime = 128;
p.FSMC_HoldSetupTime =64;
p.FSMC_HiZSetupTime = 32;
/* p.FSMC_SetupTime = 0xf1;
p.FSMC_WaitSetupTime = 0xf3;
p.FSMC_HoldSetupTime = 0xf2;
p.FSMC_HiZSetupTime = 0xf1; */
FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Disable;
FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable;
FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0;
FSMC_NANDInitStructure.FSMC_TARSetupTime = 0;
FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
FSMC_NANDInit(&FSMC_NANDInitStructure);
/*!< FSMC NAND Bank Cmd Test */
FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
}
/**
* @brief Configures the FSMC and GPIOs to interface with the NAND memory.
* This function must be called before any write/read operation on the
* NAND.
* @param None
* @retval None
*/
void NAND_Init(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
FSMC_NAND_PCCARDTimingInitTypeDef p;
FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
/*FSMC总线使用的GPIO组时钟使能*/
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOE |
RCC_AHB1Periph_GPIOF, ENABLE);
//RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
/*FSMC CLE, ALE, D0->D3, NOE, NWE and NCE2初始化，推挽复用输出*/
/* GPIOD configuration */
GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource6, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource7, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource11, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource13, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FSMC);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 |
GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 |
GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* GPIOE configuration */
GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource2 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource3 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource4 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource5 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource6 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FSMC);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7 |
GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11|
GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_Init(GPIOE, &GPIO_InitStructure);
/* GPIOF configuration */
GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FSMC);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
GPIO_Pin_4 | GPIO_Pin_5 |
GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_Init(GPIOF, &GPIO_InitStructure);
/* GPIOG configuration */
GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource2 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource3 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource9 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource10 , GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG, GPIO_PinSource12 , GPIO_AF_FSMC);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_9 | GPIO_Pin_10 |
GPIO_Pin_12 ;
GPIO_Init(GPIOG, &GPIO_InitStructure);
/*--------------FSMC 总线 存储器参数配置------------------------------*/
p.FSMC_SetupTime = 0x0; //建立时间
p.FSMC_WaitSetupTime = 0x4; //等待时间
p.FSMC_HoldSetupTime = 0x2; //保持时间
p.FSMC_HiZSetupTime = 0x0; //高阻建立时间
FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND; //使用FSMC BANK2
FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable; //使能FSMC的等待功能
FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; //NAND Flash的数据宽度为8位
FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable; //使能ECC特性
FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_2048Bytes; //ECC页大小2048
FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
FSMC_NANDInit(&FSMC_NANDInitStructure);
/*!使能FSMC BANK2 */
FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
}
/**
* @brief Configures the FSMC and GPIOs to interface with the NAND memory.
* This function must be called before any write/read operation
* on the NAND.
* @param None
* @retval : None
*/
void FSMC_NAND_Init(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
FSMC_NAND_PCCARDTimingInitTypeDef p;
/* Enable GPIOD, GPIOE, GPIOF, GPIOG and AFIO clocks */
RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOE |
RCC_AHB1Periph_GPIOF, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC); //D2
GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC); //D3
GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_FSMC); //RD
GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_FSMC); //WR
GPIO_PinAFConfig(GPIOD, GPIO_PinSource11, GPIO_AF_FSMC); //ALE
GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_FSMC); //CLE
GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FSMC); //D0
GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FSMC); //D1
GPIO_PinAFConfig(GPIOD, GPIO_PinSource6, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource7, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource7, GPIO_AF_FSMC); //D4
GPIO_PinAFConfig(GPIOE, GPIO_PinSource8, GPIO_AF_FSMC); //D5
GPIO_PinAFConfig(GPIOE, GPIO_PinSource9, GPIO_AF_FSMC); //D6
GPIO_PinAFConfig(GPIOE, GPIO_PinSource10, GPIO_AF_FSMC); //D7
GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC); //D2
GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC); //D3
GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_FSMC); //RD
GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_FSMC); //WR
GPIO_PinAFConfig(GPIOD, GPIO_PinSource11, GPIO_AF_FSMC); //ALE
GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_FSMC); //CLE
GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FSMC); //D0
GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FSMC); //D1
GPIO_PinAFConfig(GPIOD, GPIO_PinSource6, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD, GPIO_PinSource7, GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE, GPIO_PinSource7, GPIO_AF_FSMC); //D4
GPIO_PinAFConfig(GPIOE, GPIO_PinSource8, GPIO_AF_FSMC); //D5
GPIO_PinAFConfig(GPIOE, GPIO_PinSource9, GPIO_AF_FSMC); //D6
GPIO_PinAFConfig(GPIOE, GPIO_PinSource10, GPIO_AF_FSMC); //D7
/*-- GPIO Configuration ------------------------------------------------------*/
/* SRAM Data lines, NOE and NWE configuration */
GPIO_InitStructure.GPIO_Pin = GPIOD_FSMC_D0 | GPIOD_FSMC_D1 | GPIOD_FSMC_D2 | GPIOD_FSMC_D3 |
GPIOD_FSMC_ALE | GPIOD_FSMC_CLE | GPIOD_NF_RB | GPIOD_NF_CS |
GPIOD_FSMC_RD | GPIOD_FSMC_WR;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/**NANDFLASHƬѡʼÖÕÓÐЧ*/
GPIO_ResetBits(GPIOD, GPIOD_NF_CS);
#if 0
/*-- GPIO Configuration ------------------------------------------------------*/
/* SRAM Data lines, NOE and NWE configuration */
GPIO_InitStructure.GPIO_Pin = GPIOD_FSMC_D0 | GPIOD_FSMC_D1 | GPIOD_FSMC_D2 | GPIOD_FSMC_D3 |
GPIOD_FSMC_ALE | GPIOD_FSMC_CLE | GPIOD_NF_RB | GPIOD_NF_CS |
GPIOD_FSMC_RD | GPIOD_FSMC_WR;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/*
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
*/
/*-- GPIO Configuration ------------------------------------------------------*/
/* CLE, ALE, D0->D3, NOE, NWE and NCE2 NAND pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 |
GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
GPIO_Pin_7;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* D4->D7 NAND pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
GPIO_Init(GPIOE, &GPIO_InitStructure);
/* NWAIT NAND pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* INT2 NAND pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_Init(GPIOG, &GPIO_InitStructure);
#endif
/*-- FSMC Configuration ------------------------------------------------------*/
p.FSMC_SetupTime = 0x1;
p.FSMC_WaitSetupTime = 0x3;
p.FSMC_HoldSetupTime = 0x2;
p.FSMC_HiZSetupTime = 0x1;
FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable;
FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
FSMC_NANDInit(&FSMC_NANDInitStructure);
/* FSMC NAND Bank Cmd Test */
FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
}
/*******************************************************************************
* Function Name : FSMC_NAND_Init
* Description : Configures the FSMC and GPIOs to interface with the NAND memory.
* This function must be called before any write/read operation
* on the NAND.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void FSMC_NAND_Init(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
FSMC_NAND_PCCARDTimingInitTypeDef p;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
/*-- GPIO Configuration ------------------------------------------------------*/
/* CLE, ALE, D0->D3, NOE, NWE and NCE2 NAND pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 |
GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
GPIO_Pin_7;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* D4->D7 NAND pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
GPIO_Init(GPIOE, &GPIO_InitStructure);
/* NWAIT NAND pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* INT2 NAND pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_Init(GPIOG, &GPIO_InitStructure);
/*-- FSMC Configuration ------------------------------------------------------*/
p.FSMC_SetupTime = 0x1;
p.FSMC_WaitSetupTime = 0x3;
p.FSMC_HoldSetupTime = 0x2;
p.FSMC_HiZSetupTime = 0x1;
FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable;
FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
FSMC_NANDInit(&FSMC_NANDInitStructure);
/* FSMC NAND Bank Cmd Test */
FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
/**************************************************************************/
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
TIM_TimeBaseStructure.TIM_Period = 1; //自动装载
TIM_TimeBaseStructure.TIM_Prescaler = 72; //72M分频率到1MHz
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Down; //向下计数
TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
/**************************************************************************/
}
