/**
* @brief DeInitializes the LCD.
* @param None
* @retval None
*/
void LCD_DeInit(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
/* LCD Display Off */
LCD_DisplayOff();
/* BANK 4 (of NOR/SRAM Bank 1~4) is disabled */
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
/* LCD_SPI DeInit */
FSMC_NORSRAMDeInit(FSMC_Bank1_NORSRAM4);
/* Set PD.00(D2), PD.01(D3), PD.04(NOE), PD.05(NWE), PD.08(D13), PD.09(D14),
PD.10(D15), PD.14(D0), PD.15(D1) as input floating */
GPIO_InitStructure.GPIO_Pin =
GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 |
GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOD, &GPIO_InitStructure);
/* Set PE.07(D4), PE.08(D5), PE.09(D6), PE.10(D7), PE.11(D8), PE.12(D9), PE.13(D10),
PE.14(D11), PE.15(D12) as alternate function push pull */
GPIO_InitStructure.GPIO_Pin =
GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 |
GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_Init(GPIOE, &GPIO_InitStructure);
/* Set PF.00(A0 (RS)) as alternate function push pull */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
GPIO_Init(GPIOF, &GPIO_InitStructure);
/* Set PG.12(NE4 (LCD/CS)) as alternate function push pull - CE3(LCD /CS) */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
GPIO_Init(GPIOG, &GPIO_InitStructure);
}
static void fsmc_for_sram_configration(void)
{
FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
FSMC_NORSRAMTimingInitTypeDef timing;
FSMC_NORSRAMDeInit(FSMC_Bank1_NORSRAM1);
/*
* ---- 初期调试用参数
* p.FSMC_AddressSetupTime = 15;
* p.FSMC_AddressHoldTime = 15;
* p.FSMC_DataSetupTime = 15;
* p.FSMC_BusTurnAroundDuration = 15;
* p.FSMC_CLKDivision = 8;
* p.FSMC_DataLatency = 15;
*/
timing.FSMC_AddressSetupTime = 0x01; /* It is not used with synchronous NOR Flash memories. */
timing.FSMC_AddressHoldTime = 0x01; /* It is not used with synchronous NOR Flash memories.*/
timing.FSMC_DataSetupTime = 0x01; /* It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
timing.FSMC_BusTurnAroundDuration = 0x00; /* It is only used for multiplexed NOR Flash memories. */
timing.FSMC_CLKDivision = 0x00; /* It is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
timing.FSMC_DataLatency = 0x00; /* It must be set to 0 in case of a CRAM */
timing.FSMC_AccessMode = FSMC_AccessMode_B;
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;
#if RT_EXT_SRAM_MULTIPLEXED
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
#else
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
#endif
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &timing;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &timing;
/* FSMC_NORSRAMStructInit(&FSMC_NORSRAMInitStructure); */
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
/* Enable FSMC Bank1_SRAM Bank */
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);
}
