/**Function************************************************************* Synopsis [Recursively derives the truth table for the cut.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void Fpga_CutVolume_rec( Fpga_Cut_t * pCut, Fpga_NodeVec_t * vVisited ) { assert( !Fpga_IsComplement(pCut) ); if ( pCut->fMark ) return; pCut->fMark = 1; Fpga_CutVolume_rec( Fpga_CutRegular(pCut->pOne), vVisited ); Fpga_CutVolume_rec( Fpga_CutRegular(pCut->pTwo), vVisited ); Fpga_NodeVecPush( vVisited, (Fpga_Node_t *)pCut ); }
/**Function************************************************************* Synopsis [Computes the array of mapping.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ float Fpga_MappingGetSwitching( Fpga_Man_t * pMan, Fpga_NodeVec_t * vMapping ) { Fpga_Node_t * pNode; float Switch; int i; Switch = 0.0; for ( i = 0; i < vMapping->nSize; i++ ) { pNode = vMapping->pArray[i]; // at least one phase has the best cut assigned assert( !Fpga_NodeIsAnd(pNode) || pNode->pCutBest != NULL ); // at least one phase is used in the mapping assert( pNode->nRefs > 0 ); // compute the array due to the supergate Switch += pNode->Switching; } // add buffer for each CO driven by a CI for ( i = 0; i < pMan->nOutputs; i++ ) if ( Fpga_NodeIsVar(pMan->pOutputs[i]) && !Fpga_IsComplement(pMan->pOutputs[i]) ) Switch += pMan->pOutputs[i]->Switching; return Switch; }
/**Function************************************************************* Synopsis [Recursively derives the truth table for the cut.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ DdNode * Fpga_TruthsCutBdd_rec( DdManager * dd, Fpga_Cut_t * pCut, Fpga_NodeVec_t * vVisited ) { DdNode * bFunc, * bFunc0, * bFunc1; assert( !Fpga_IsComplement(pCut) ); // if the cut is visited, return the result if ( pCut->uSign ) return (DdNode *)pCut->uSign; // compute the functions of the children bFunc0 = Fpga_TruthsCutBdd_rec( dd, Fpga_CutRegular(pCut->pOne), vVisited ); Cudd_Ref( bFunc0 ); bFunc0 = Cudd_NotCond( bFunc0, Fpga_CutIsComplement(pCut->pOne) ); bFunc1 = Fpga_TruthsCutBdd_rec( dd, Fpga_CutRegular(pCut->pTwo), vVisited ); Cudd_Ref( bFunc1 ); bFunc1 = Cudd_NotCond( bFunc1, Fpga_CutIsComplement(pCut->pTwo) ); // get the function of the cut bFunc = Cudd_bddAnd( dd, bFunc0, bFunc1 ); Cudd_Ref( bFunc ); bFunc = Cudd_NotCond( bFunc, pCut->Phase ); Cudd_RecursiveDeref( dd, bFunc0 ); Cudd_RecursiveDeref( dd, bFunc1 ); assert( pCut->uSign == 0 ); pCut->uSign = (unsigned)bFunc; // add this cut to the visited list Fpga_NodeVecPush( vVisited, (Fpga_Node_t *)pCut ); return bFunc; }