/**function*************************************************************
synopsis [Dereferences the cut.]
description [This procedure is similar to the procedure NodeRecusiveDeref.]
sideeffects []
seealso []
***********************************************************************/
float Fpga_CutDeref( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, int fFanouts )
{
Fpga_Node_t * pNodeChild;
float aArea;
int i;
// deref the fanouts
// if ( fFanouts )
// Fpga_CutRemoveFanouts( pMan, pNode, pCut );
// start the area of this cut
aArea = pMan->pLutLib->pLutAreas[pCut->nLeaves];
// go through the children
for ( i = 0; i < pCut->nLeaves; i++ )
{
pNodeChild = pCut->ppLeaves[i];
assert( pNodeChild->nRefs > 0 );
if ( --pNodeChild->nRefs > 0 )
continue;
if ( !Fpga_NodeIsAnd(pNodeChild) )
continue;
aArea += Fpga_CutDeref( pMan, pNodeChild, pNodeChild->pCutBest, fFanouts );
}
return aArea;
}
/**Function*************************************************************
Synopsis [Computes the required times of the given nodes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Fpga_TimePropagateRequired( Fpga_Man_t * p, Fpga_NodeVec_t * vNodes )
{
Fpga_Node_t * pNode, * pChild;
float fRequired;
int i, k;
// sorts the nodes in the decreasing order of levels
// Fpga_MappingSortByLevel( p, vNodes, 0 );
// the nodes area already sorted in Fpga_MappingSetRefsAndArea()
// go through the nodes in the reverse topological order
for ( k = 0; k < vNodes->nSize; k++ )
{
pNode = vNodes->pArray[k];
if ( !Fpga_NodeIsAnd(pNode) )
continue;
// get the required time for children
fRequired = pNode->tRequired - p->pLutLib->pLutDelays[(int)pNode->pCutBest->nLeaves][0];
// update the required time of the children
for ( i = 0; i < pNode->pCutBest->nLeaves; i++ )
{
pChild = pNode->pCutBest->ppLeaves[i];
pChild->tRequired = FPGA_MIN( pChild->tRequired, fRequired );
}
}
}
/**Function*************************************************************
Synopsis [Computes the array of mapping.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
float Fpga_MappingGetSwitching( Fpga_Man_t * pMan, Fpga_NodeVec_t * vMapping )
{
Fpga_Node_t * pNode;
float Switch;
int i;
Switch = 0.0;
for ( i = 0; i < vMapping->nSize; i++ )
{
pNode = vMapping->pArray[i];
// at least one phase has the best cut assigned
assert( !Fpga_NodeIsAnd(pNode) || pNode->pCutBest != NULL );
// at least one phase is used in the mapping
assert( pNode->nRefs > 0 );
// compute the array due to the supergate
Switch += pNode->Switching;
}
// add buffer for each CO driven by a CI
for ( i = 0; i < pMan->nOutputs; i++ )
if ( Fpga_NodeIsVar(pMan->pOutputs[i]) && !Fpga_IsComplement(pMan->pOutputs[i]) )
Switch += pMan->pOutputs[i]->Switching;
return Switch;
}
