static int _switch_gate(mod_type_t type, int flag)
{
int ret = 0;
switch(type) {
case MOD_VDEC:
PRINT_INFO("turn %s vdec module\n", flag?"on":"off");
if (flag) {
GATE_ON(DOS);
} else {
GATE_OFF(DOS);
}
break;
case MOD_AUDIO:
PRINT_INFO("turn %s audio module\n", flag?"on":"off");
if (flag) {
GATE_ON(AIU_AMCLK_MEASURE);
GATE_ON(AIU_AIFIFO2);
GATE_ON(AIU_AUD_MIXER);
GATE_ON(AIU_MIXER_REG);
GATE_ON(AIU_IEC958);
GATE_ON(AIU_AI_TOP_GLUE);
GATE_ON(AUD_BUF);
GATE_ON(AIU_I2S_OUT);
GATE_ON(AIU_AMCLK); //this gate should not be turned off
GATE_ON(AIU_ICE958_AMCLK);
GATE_ON(AIU_AOCLK);
//GATE_ON(AUD_IN);
GATE_ON(AIU_ADC);
GATE_ON(AIU_AUDIN_SCLK);
} else {
GATE_OFF(AIU_AMCLK_MEASURE);
GATE_OFF(AIU_AIFIFO2);
GATE_OFF(AIU_AUD_MIXER);
GATE_OFF(AIU_MIXER_REG);
GATE_OFF(AIU_IEC958);
GATE_OFF(AIU_AI_TOP_GLUE);
GATE_OFF(AUD_BUF);
GATE_OFF(AIU_I2S_OUT);
GATE_OFF(AIU_AMCLK); //this gate should not be turned off
GATE_OFF(AIU_ICE958_AMCLK);
GATE_OFF(AIU_AOCLK);
//GATE_OFF(AUD_IN);
GATE_OFF(AIU_ADC);
GATE_OFF(AIU_AUDIN_SCLK);
}
break;
case MOD_HDMI:
PRINT_INFO("turn %s hdmi module\n", flag?"on":"off");
if (flag) {
GATE_ON(HDMI_INTR_SYNC);
GATE_ON(HDMI_PCLK);
GATE_ON(VCLK1_HDMI);
} else {
GATE_OFF(HDMI_INTR_SYNC);
GATE_OFF(HDMI_PCLK);
GATE_OFF(VCLK1_HDMI);
}
break;
case MOD_VENC:
PRINT_INFO("turn %s venc module\n", flag?"on":"off");
if (flag) {
GATE_ON(VCLK2_VENCI);
GATE_ON(VCLK2_VENCI1);
GATE_ON(VCLK2_VENCP);
GATE_ON(VCLK2_VENCP1);
GATE_ON(VENC_P_TOP);
GATE_ON(VENC_I_TOP);
GATE_ON(VENCI_INT);
GATE_ON(VENCP_INT);
GATE_ON(VCLK2_ENCI);
GATE_ON(VCLK2_ENCP);
GATE_ON(VCLK2_VENCT);
GATE_ON(VCLK2_VENCT1);
GATE_ON(VCLK2_OTHER);
GATE_ON(VCLK2_OTHER1);
GATE_ON(ENC480P);
GATE_ON(VENC_DAC);
GATE_ON(DAC_CLK);
} else {
GATE_OFF(VCLK2_VENCI);
GATE_OFF(VCLK2_VENCI1);
GATE_OFF(VCLK2_VENCP);
GATE_OFF(VCLK2_VENCP1);
GATE_OFF(VENC_P_TOP);
GATE_OFF(VENC_I_TOP);
GATE_OFF(VENCI_INT);
GATE_OFF(VENCP_INT);
GATE_OFF(VCLK2_ENCI);
GATE_OFF(VCLK2_ENCP);
GATE_OFF(VCLK2_VENCT);
GATE_OFF(VCLK2_VENCT1);
GATE_OFF(VCLK2_OTHER);
GATE_OFF(VCLK2_OTHER1);
GATE_OFF(ENC480P);
GATE_OFF(VENC_DAC);
GATE_OFF(DAC_CLK);
}
break;
case MOD_TCON:
PRINT_INFO("turn %s tcon module\n", flag?"on":"off");
if (flag) {
GATE_ON(VENC_T_TOP);
GATE_ON(VENCT_INT);
GATE_ON(VCLK2_ENCT);
} else {
GATE_OFF(VENC_T_TOP);
GATE_OFF(VENCT_INT);
GATE_OFF(VCLK2_ENCT);
}
break;
case MOD_LVDS:
PRINT_INFO("turn %s lvds module\n", flag?"on":"off");
if (flag) {
GATE_ON(VENC_L_TOP);
GATE_ON(VENCL_INT);
GATE_ON(VCLK2_ENCL);
} else {
GATE_OFF(VENC_L_TOP);
GATE_OFF(VENCL_INT);
GATE_OFF(VCLK2_ENCL);
}
break;
case MOD_MIPI:
PRINT_INFO("turn %s mipi module\n", flag?"on":"off");
if (flag) {
GATE_ON(MIPI_APB_CLK);
GATE_ON(MIPI_SYS_CLK);
GATE_ON(MIPI_PHY);
} else {
GATE_OFF(MIPI_APB_CLK);
GATE_OFF(MIPI_SYS_CLK);
GATE_OFF(MIPI_PHY);
}
break;
case MOD_BT656:
PRINT_INFO("turn %s bt656 module\n", flag?"on":"off");
if (flag) {
GATE_ON(BT656_IN);
} else {
GATE_OFF(BT656_IN);
}
break;
case MOD_SPI:
PRINT_INFO("turn %s spi module\n", flag?"on":"off");
if (flag) {
GATE_ON(SPICC);
GATE_ON(SPI1);
GATE_ON(SPI2);
} else {
GATE_OFF(SPICC);
GATE_OFF(SPI1);
GATE_OFF(SPI2);
}
break;
case MOD_UART0:
PRINT_INFO("turn %s uart0 module\n", flag?"on":"off");
if (flag) {
GATE_ON(UART0);
} else {
GATE_OFF(UART0);
}
break;
case MOD_UART1:
PRINT_INFO("turn %s uart1 module\n", flag?"on":"off");
if (flag) {
GATE_ON(UART1);
} else {
GATE_OFF(UART1);
}
break;
case MOD_UART2:
PRINT_INFO("turn %s uart2 module\n", flag?"on":"off");
if (flag) {
GATE_ON(UART2);
} else {
GATE_OFF(UART2);
}
break;
case MOD_UART3:
PRINT_INFO("turn %s uart3 module\n", flag?"on":"off");
if (flag) {
GATE_ON(UART3);
} else {
GATE_OFF(UART3);
}
break;
case MOD_ROM:
PRINT_INFO("turn %s rom module\n", flag?"on":"off");
if (flag) {
GATE_ON(ROM_CLK);
} else {
GATE_OFF(ROM_CLK);
}
break;
case MOD_EFUSE:
PRINT_INFO("turn %s efuse module\n", flag?"on":"off");
if (flag) {
GATE_ON(EFUSE);
} else {
GATE_OFF(EFUSE);
}
break;
case MOD_RANDOM_NUM_GEN:
PRINT_INFO("turn %s random_num_gen module\n", flag?"on":"off");
if (flag) {
GATE_ON(RANDOM_NUM_GEN);
} else {
GATE_OFF(RANDOM_NUM_GEN);
}
break;
case MOD_ETHERNET:
PRINT_INFO("turn %s ethernet module\n", flag?"on":"off");
if (flag) {
GATE_ON(ETHERNET);
} else {
GATE_OFF(ETHERNET);
}
break;
case MOD_MEDIA_CPU:
PRINT_INFO("trun %s Audio DSP\n", flag? " on" : "off");
if(flag){
GATE_ON(MEDIA_CPU);
}else{
GATE_OFF(MEDIA_CPU);
}
break;
case MOD_GE2D:
PRINT_INFO("trun %s GE2D\n", flag? " on" : "off");
if(flag){
GATE_ON(GE2D);
}else{
GATE_OFF(GE2D);
}
break;
case MOD_VIDEO_IN:
PRINT_INFO("trun %s video_in\n", flag? " on" : "off");
if(flag){
GATE_ON(VIDEO_IN);
}else{
GATE_OFF(VIDEO_IN);
}
break;
case MOD_VIU2:
PRINT_INFO("trun %s viu2\n", flag? " on" : "off");
if(flag){
GATE_ON(VIU2);
}else{
GATE_OFF(VIU2);
}
break;
case MOD_AUD_IN:
PRINT_INFO("trun %s audio_in\n", flag? " on" : "off");
#if 0
if(flag){
GATE_ON(AIU_ADC);
GATE_ON(AIU_AUDIN_SCLK);
}else{
GATE_OFF(AIU_ADC);
GATE_OFF(AIU_AUDIN_SCLK);
}
#endif
break;
case MOD_AUD_OUT:
PRINT_INFO("trun %s audio_out\n", flag? " on" : "off");
if(flag){
}else{
}
break;
case MOD_AHB:
PRINT_INFO("trun %s ahb\n", flag? " on" : "off");
if(flag){
GATE_ON(AHB_ARB0);
GATE_ON(AHB_BRIDGE);
GATE_ON(AHB_DATA_BUS);
GATE_ON(AHB_CONTROL_BUS);
}else{
GATE_OFF(AHB_ARB0);
GATE_OFF(AHB_BRIDGE);
GATE_OFF(AHB_DATA_BUS);
GATE_OFF(AHB_CONTROL_BUS);
}
break;
case MOD_DEMUX:
PRINT_INFO("trun %s demux\n", flag? " on" : "off");
if(flag){
GATE_ON(DEMUX);
}else{
GATE_OFF(DEMUX);
}
break;
case MOD_SMART_CARD:
PRINT_INFO("trun %s smart card\n", flag? " on" : "off");
if(flag){
GATE_ON(SMART_CARD_MPEG_DOMAIN);
}else{
GATE_OFF(SMART_CARD_MPEG_DOMAIN);
}
break;
case MOD_SDHC:
PRINT_INFO("trun %s sdhc\n", flag? " on" : "off");
if(flag){
GATE_ON(SDHC);
}else{
GATE_OFF(SDHC);
}
break;
case MOD_STREAM:
PRINT_INFO("trun %s stream\n", flag? " on" : "off");
if(flag){
GATE_ON(STREAM);
}else{
GATE_OFF(STREAM);
}
break;
case MOD_BLK_MOV:
PRINT_INFO("trun %s blk_mov\n", flag? " on" : "off");
if(flag){
GATE_ON(BLK_MOV);
}else{
GATE_OFF(BLK_MOV);
}
break;
case MOD_MISC_DVIN:
PRINT_INFO("trun %s dvin\n", flag? " on" : "off");
if(flag){
GATE_ON(MISC_DVIN);
}else{
GATE_OFF(MISC_DVIN);
}
break;
case MOD_MISC_RDMA:
PRINT_INFO("trun %s rdma\n", flag? " on" : "off");
if(flag){
GATE_ON(MISC_RDMA);
}else{
GATE_OFF(MISC_RDMA);
}
break;
case MOD_USB0:
PRINT_INFO("trun %s rdma\n", flag? " on" : "off");
if(flag){
GATE_ON(USB0);
GATE_ON(MISC_USB0_TO_DDR);
}else{
GATE_OFF(USB0);
GATE_ON(MISC_USB0_TO_DDR);
}
break;
case MOD_USB1:
PRINT_INFO("trun %s rdma\n", flag? " on" : "off");
if(flag){
GATE_ON(USB1);
GATE_ON(MISC_USB1_TO_DDR);
}else{
GATE_OFF(USB1);
GATE_ON(MISC_USB1_TO_DDR);
}
break;
case MOD_SDIO:
PRINT_INFO("trun %s rdma\n", flag? " on" : "off");
if(flag){
GATE_ON(SDIO);
}else{
GATE_OFF(SDIO);
}
break;
case MOD_VI_CORE:
PRINT_INFO("trun %s vi core\n", flag? " on" : "off");
if(flag){
GATE_ON(VI_CORE);
}else{
GATE_OFF(VI_CORE);
}
break;
case MOD_LED_PWM:
PRINT_INFO("trun %s led pwm\n", flag? " on" : "off");
if(flag){
GATE_ON(LED_PWM);
}else{
GATE_OFF(LED_PWM);
}
break;
default:
PRINT_INFO("mod type not support\n");
ret = -1;
break;
}
return ret;
}
};
/* List of clock dividers present on S3C6410. */
DIV_CLOCKS(s3c6410_div_clks) __initdata = {
DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 4),
DIV(DOUT_FIMC, "dout_fimc", "hclk", CLK_DIV1, 24, 4),
DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV2, 24, 4),
};
/* List of clock gates present on all S3C64xx SoCs. */
GATE_CLOCKS(s3c64xx_gate_clks) __initdata = {
GATE_BUS(HCLK_UHOST, "hclk_uhost", "hclk", HCLK_GATE, 29),
GATE_BUS(HCLK_SECUR, "hclk_secur", "hclk", HCLK_GATE, 28),
GATE_BUS(HCLK_SDMA1, "hclk_sdma1", "hclk", HCLK_GATE, 27),
GATE_BUS(HCLK_SDMA0, "hclk_sdma0", "hclk", HCLK_GATE, 26),
GATE_ON(HCLK_DDR1, "hclk_ddr1", "hclk", HCLK_GATE, 24),
GATE_BUS(HCLK_USB, "hclk_usb", "hclk", HCLK_GATE, 20),
GATE_BUS(HCLK_HSMMC2, "hclk_hsmmc2", "hclk", HCLK_GATE, 19),
GATE_BUS(HCLK_HSMMC1, "hclk_hsmmc1", "hclk", HCLK_GATE, 18),
GATE_BUS(HCLK_HSMMC0, "hclk_hsmmc0", "hclk", HCLK_GATE, 17),
GATE_BUS(HCLK_MDP, "hclk_mdp", "hclk", HCLK_GATE, 16),
GATE_BUS(HCLK_DHOST, "hclk_dhost", "hclk", HCLK_GATE, 15),
GATE_BUS(HCLK_IHOST, "hclk_ihost", "hclk", HCLK_GATE, 14),
GATE_BUS(HCLK_DMA1, "hclk_dma1", "hclk", HCLK_GATE, 13),
GATE_BUS(HCLK_DMA0, "hclk_dma0", "hclk", HCLK_GATE, 12),
GATE_BUS(HCLK_JPEG, "hclk_jpeg", "hclk", HCLK_GATE, 11),
GATE_BUS(HCLK_CAMIF, "hclk_camif", "hclk", HCLK_GATE, 10),
GATE_BUS(HCLK_SCALER, "hclk_scaler", "hclk", HCLK_GATE, 9),
GATE_BUS(HCLK_2D, "hclk_2d", "hclk", HCLK_GATE, 8),
GATE_BUS(HCLK_TV, "hclk_tv", "hclk", HCLK_GATE, 7),
GATE_BUS(HCLK_POST0, "hclk_post0", "hclk", HCLK_GATE, 5),
