static int i2c_resume_device_from_suspend(struct device *dev)
{
struct i2c_qmsi_driver_data *drv_data = GET_DRIVER_DATA(dev);
qm_i2c_restore_context(GET_CONTROLLER_INSTANCE(dev),
&drv_data->i2c_ctx);
i2c_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
return 0;
}
static int i2c_qmsi_init(struct device *dev)
{
struct i2c_qmsi_driver_data *driver_data = GET_DRIVER_DATA(dev);
const struct i2c_qmsi_config_info *config = dev->config->config_info;
qm_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
u32_t bitrate_cfg;
int err;
k_sem_init(&driver_data->device_sync_sem, 0, UINT_MAX);
k_sem_init(&driver_data->sem, 1, UINT_MAX);
switch (instance) {
case QM_I2C_0:
/* Register interrupt handler, unmask IRQ and route it
* to Lakemont core.
*/
IRQ_CONNECT(CONFIG_I2C_0_IRQ,
CONFIG_I2C_0_IRQ_PRI, qm_i2c_0_irq_isr, NULL,
CONFIG_I2C_0_IRQ_FLAGS);
irq_enable(CONFIG_I2C_0_IRQ);
QM_IR_UNMASK_INTERRUPTS(
QM_INTERRUPT_ROUTER->i2c_master_0_int_mask);
break;
#ifdef CONFIG_I2C_1
case QM_I2C_1:
IRQ_CONNECT(CONFIG_I2C_1_IRQ,
CONFIG_I2C_1_IRQ_PRI, qm_i2c_1_irq_isr, NULL,
CONFIG_I2C_1_IRQ_FLAGS);
irq_enable(CONFIG_I2C_1_IRQ);
QM_IR_UNMASK_INTERRUPTS(
QM_INTERRUPT_ROUTER->i2c_master_1_int_mask);
break;
#endif /* CONFIG_I2C_1 */
default:
return -EIO;
}
clk_periph_enable(config->clock_gate);
bitrate_cfg = _i2c_map_dt_bitrate(config->bitrate);
err = i2c_qmsi_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
if (err < 0) {
return err;
}
dev->driver_api = &api;
i2c_qmsi_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
return 0;
}
static int i2c_qmsi_transfer(struct device *dev, struct i2c_msg *msgs,
u8_t num_msgs, u16_t addr)
{
struct i2c_qmsi_driver_data *driver_data = GET_DRIVER_DATA(dev);
qm_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
int rc;
__ASSERT_NO_MSG(msgs);
if (!num_msgs) {
return 0;
}
device_busy_set(dev);
for (int i = 0; i < num_msgs; i++) {
u8_t op = msgs[i].flags & I2C_MSG_RW_MASK;
bool stop = (msgs[i].flags & I2C_MSG_STOP) == I2C_MSG_STOP;
qm_i2c_transfer_t xfer = { 0 };
if (op == I2C_MSG_WRITE) {
xfer.tx = msgs[i].buf;
xfer.tx_len = msgs[i].len;
} else {
xfer.rx = msgs[i].buf;
xfer.rx_len = msgs[i].len;
}
xfer.callback = transfer_complete;
xfer.callback_data = dev;
xfer.stop = stop;
k_sem_take(&driver_data->sem, K_FOREVER);
rc = qm_i2c_master_irq_transfer(instance, &xfer, addr);
k_sem_give(&driver_data->sem);
if (rc != 0) {
device_busy_clear(dev);
return -EIO;
}
/* Block current thread until the I2C transfer completes. */
k_sem_take(&driver_data->device_sync_sem, K_FOREVER);
if (driver_data->transfer_status != 0) {
device_busy_clear(dev);
return -EIO;
}
}
device_busy_clear(dev);
return 0;
}
static int i2c_suspend_device(struct device *dev)
{
if (device_busy_check(dev)) {
return -EBUSY;
}
struct i2c_qmsi_driver_data *drv_data = GET_DRIVER_DATA(dev);
qm_i2c_save_context(GET_CONTROLLER_INSTANCE(dev), &drv_data->i2c_ctx);
i2c_qmsi_set_power_state(dev, DEVICE_PM_SUSPEND_STATE);
return 0;
}
static int i2c_qmsi_configure(struct device *dev, u32_t config)
{
qm_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
struct i2c_qmsi_driver_data *driver_data = GET_DRIVER_DATA(dev);
qm_i2c_reg_t *const controller = QM_I2C[instance];
int rc;
qm_i2c_config_t qm_cfg;
/* This driver only supports master mode. */
if (!(I2C_MODE_MASTER & config))
return -EINVAL;
qm_cfg.mode = QM_I2C_MASTER;
if (I2C_ADDR_10_BITS & config) {
qm_cfg.address_mode = QM_I2C_10_BIT;
} else {
qm_cfg.address_mode = QM_I2C_7_BIT;
}
switch (I2C_SPEED_GET(config)) {
case I2C_SPEED_STANDARD:
qm_cfg.speed = QM_I2C_SPEED_STD;
break;
case I2C_SPEED_FAST:
qm_cfg.speed = QM_I2C_SPEED_FAST;
break;
case I2C_SPEED_FAST_PLUS:
qm_cfg.speed = QM_I2C_SPEED_FAST_PLUS;
break;
default:
return -EINVAL;
}
k_sem_take(&driver_data->sem, K_FOREVER);
rc = qm_i2c_set_config(instance, &qm_cfg);
k_sem_give(&driver_data->sem);
controller->ic_sda_hold = (CONFIG_I2C_SDA_RX_HOLD << 16) +
CONFIG_I2C_SDA_TX_HOLD;
controller->ic_sda_setup = CONFIG_I2C_SDA_SETUP;
return rc;
}