/* Set up the DPDMA according to the specification configuration details */
Status IP_GPDMA_Setup(IP_GPDMA_001_Type *pGPDMA,
					  GPDMA_Channel_CFG_Type *GPDMAChannelConfig,
					  uint32_t CtrlWord,
					  uint32_t LinkListItem,
					  uint8_t SrcPeripheral,
					  uint8_t DstPeripheral)
{
	IP_GPDMA_001_CH_Type *pDMAch;

	if (pGPDMA->ENBLDCHNS & ((((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF)))) {
		/* This channel is enabled, return ERROR, need to release this channel first */
		return ERROR;
	}

	/* Get Channel pointer */
	pDMAch = (IP_GPDMA_001_CH_Type *) &(pGPDMA->CH[GPDMAChannelConfig->ChannelNum]);

	/* Reset the Interrupt status */
	pGPDMA->INTTCCLEAR = (((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF));
	pGPDMA->INTERRCLR = (((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF));

	/* Assign Linker List Item value */
	pDMAch->LLI = LinkListItem;

	/* Enable DMA channels, little endian */
	pGPDMA->CONFIG = GPDMA_DMACConfig_E;
	while (!(pGPDMA->CONFIG & GPDMA_DMACConfig_E)) {}

	pDMAch->SRCADDR = GPDMAChannelConfig->SrcAddr;
	pDMAch->DESTADDR = GPDMAChannelConfig->DstAddr;

	/* Configure DMA Channel, enable Error Counter and Terminate counter */
	pDMAch->CONFIG = GPDMA_DMACCxConfig_IE
					 | GPDMA_DMACCxConfig_ITC		/*| GPDMA_DMACCxConfig_E*/
					 | GPDMA_DMACCxConfig_TransferType((uint32_t) GPDMAChannelConfig->TransferType)
					 | GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral)
					 | GPDMA_DMACCxConfig_DestPeripheral(DstPeripheral);

	pDMAch->CONTROL = CtrlWord;

	return SUCCESS;
}
/********************************************************************//**
 * @brief 		Setup GPDMA channel peripheral according to the specified
 *               parameters in the GPDMAChannelConfig.
 * @param[in]	GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type
 * 									structure that contains the configuration
 * 									information for the specified GPDMA channel peripheral.
 * @return		ERROR if selected channel is enabled before
 * 				or SUCCESS if channel is configured successfully
 *********************************************************************/
Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)
{
	LPC_GPDMACH_TypeDef *pDMAch;
	uint32_t tmp1, tmp2;

	if (LPC_GPDMA->DMACEnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
		// This channel is enabled, return ERROR, need to release this channel first
		return ERROR;
	}

	// Get Channel pointer
	pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];

	// Reset the Interrupt status
	LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
	LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);

	// Clear DMA configure
	pDMAch->DMACCControl = 0x00;
	pDMAch->DMACCConfig = 0x00;

	/* Assign Linker List Item value */
	pDMAch->DMACCLLI = GPDMAChannelConfig->DMALLI;

	/* Set value to Channel Control Registers */
	switch (GPDMAChannelConfig->TransferType)
	{
	// Memory to memory
	case GPDMA_TRANSFERTYPE_M2M:
		// Assign physical source and destination address
		pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
		pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
		pDMAch->DMACCControl
				= GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
						| GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
						| GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
						| GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
						| GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
						| GPDMA_DMACCxControl_SI \
						| GPDMA_DMACCxControl_DI \
						| GPDMA_DMACCxControl_I;
		break;
	// Memory to peripheral
	case GPDMA_TRANSFERTYPE_M2P:
		// Assign physical source
		pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
		// Assign peripheral destination address
		pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
		pDMAch->DMACCControl
				= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
						| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
						| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
						| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
						| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
						| GPDMA_DMACCxControl_SI \
						| GPDMA_DMACCxControl_I;
		break;
	// Peripheral to memory
	case GPDMA_TRANSFERTYPE_P2M:
		// Assign peripheral source address
		pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
		// Assign memory destination address
		pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
		pDMAch->DMACCControl
				= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
						| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
						| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
						| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
						| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
						| GPDMA_DMACCxControl_DI \
						| GPDMA_DMACCxControl_I;
		break;
	// Peripheral to peripheral
	case GPDMA_TRANSFERTYPE_P2P:
		// Assign peripheral source address
		pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
		// Assign peripheral destination address
		pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
		pDMAch->DMACCControl
				= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
						| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
						| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
						| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
						| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
						| GPDMA_DMACCxControl_I;
		break;
	// Do not support any more transfer type, return ERROR
	default:
		return ERROR;
	}

	/* Re-Configure DMA Request Select for source peripheral */
	if (GPDMAChannelConfig->SrcConn > 15)
	{
		DMAREQSEL |= (1<<(GPDMAChannelConfig->SrcConn - 16));
	} else {
		DMAREQSEL &= ~(1<<(GPDMAChannelConfig->SrcConn - 8));
	}

	/* Re-Configure DMA Request Select for Destination peripheral */
	if (GPDMAChannelConfig->DstConn > 15)
	{
		DMAREQSEL |= (1<<(GPDMAChannelConfig->DstConn - 16));
	} else {
		DMAREQSEL &= ~(1<<(GPDMAChannelConfig->DstConn - 8));
	}

	/* Enable DMA channels, little endian */
	LPC_GPDMA->DMACConfig = GPDMA_DMACConfig_E;
	while (!(LPC_GPDMA->DMACConfig & GPDMA_DMACConfig_E));

	// Calculate absolute value for Connection number
	tmp1 = GPDMAChannelConfig->SrcConn;
	tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
	tmp2 = GPDMAChannelConfig->DstConn;
	tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);

	// Configure DMA Channel, enable Error Counter and Terminate counter
	pDMAch->DMACCConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \
		| GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
		| GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \
		| GPDMA_DMACCxConfig_DestPeripheral(tmp2);

	return SUCCESS;
}
/********************************************************************//**
 * @brief 		Setup GPDMA channel peripheral according to the specified
 *              parameters in the GPDMAChannelConfig.
 * @param[in]	GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type structure
 * 				that contains the configuration information for the specified
 * 				GPDMA channel peripheral.
 * @return		Setup status, could be:
 * 					- ERROR		:if selected channel is enabled before
 * 					- SUCCESS 	:if channel is configured successfully
 *********************************************************************/
Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)
{
	LPC_GPDMACH_TypeDef *pDMAch;
	uint8_t SrcPeripheral=0, DestPeripheral=0;

	if (LPC_GPDMA->ENBLDCHNS & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
		// This channel is enabled, return ERROR, need to release this channel first
		return ERROR;
	}

	// Get Channel pointer
	pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];

	// Reset the Interrupt status
	LPC_GPDMA->INTTCCLEAR = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
	LPC_GPDMA->INTERRCLR = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);

	// Clear DMA configure
	pDMAch->CControl = 0x00;
	pDMAch->CConfig = 0x00;

	/* Assign Linker List Item value */
	pDMAch->CLLI = GPDMAChannelConfig->DMALLI;

	/* Set value to Channel Control Registers */
	switch (GPDMAChannelConfig->TransferType)
	{
	// Memory to memory
	case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:
		// Assign physical source and destination address
		pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;
		pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;
		pDMAch->CControl
				= GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
						| GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
						| GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
						| GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
						| GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
						| GPDMA_DMACCxControl_SI \
						| GPDMA_DMACCxControl_DI \
						| GPDMA_DMACCxControl_I;
		break;
	// Memory to peripheral
	case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:
		// Assign physical source
		pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;
		// Assign peripheral destination address
		pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
		pDMAch->CControl
				= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
						| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
						| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
						| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
						| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
						| GPDMA_DMACCxControl_DestTransUseAHBMaster1 \
						| GPDMA_DMACCxControl_SI \
						| GPDMA_DMACCxControl_I;
		DestPeripheral = DMAMUX_Config(GPDMAChannelConfig->DstConn);
		break;
	// Peripheral to memory
	case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
		// Assign peripheral source address
		pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
		// Assign memory destination address
		pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;
		pDMAch->CControl
				= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
						| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
						| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
						| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
						| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
						| GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \
						| GPDMA_DMACCxControl_DI \
						| GPDMA_DMACCxControl_I;
		SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn);
		break;
	// Peripheral to peripheral
	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:
		// Assign peripheral source address
		pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
		// Assign peripheral destination address
		pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
		pDMAch->CControl
				= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
						| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
						| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
						| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
						| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
						| GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \
						| GPDMA_DMACCxControl_DestTransUseAHBMaster1 \
						| GPDMA_DMACCxControl_I;
		SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn);
		DestPeripheral = DMAMUX_Config(GPDMAChannelConfig->DstConn);
		break;

	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:
	case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:
	case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:
	case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:
		//to be defined
	// Do not support any more transfer type, return ERROR
	default:
		return ERROR;
	}

	/* Enable DMA channels, little endian */
	LPC_GPDMA->CONFIG = GPDMA_DMACConfig_E;
	while (!(LPC_GPDMA->CONFIG & GPDMA_DMACConfig_E));

	// Configure DMA Channel, enable Error Counter and Terminate counter
	pDMAch->CConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \
		| GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
		| GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral) \
		| GPDMA_DMACCxConfig_DestPeripheral(DestPeripheral);

	return SUCCESS;
}
Exemple #4
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void dma_setup(char ChannelNum, unsigned int SrcMemAddr,unsigned int DstMemAddr, unsigned int SrcPeriph, unsigned int DstPeriph, unsigned int TransferSize, unsigned int BurstSize, unsigned int TransferWidth, unsigned int TransferType,  unsigned int Dmalli  ){
	
    LPC_GPDMACH_TypeDef *pDMAch;

    // Get Channel pointer
    pDMAch = ((LPC_GPDMACH_TypeDef *) (LPC_GPDMACH0_BASE + 0x20 * (ChannelNum)));
     
    // Reset the Interrupt status
    LPC_GPDMA->IntTCClear = GPDMA_DMACIntTCClear_Ch(ChannelNum);
    LPC_GPDMA->IntErrClr = GPDMA_DMACIntErrClr_Ch(ChannelNum);

    // Clear DMA configure
    pDMAch->CControl = 0x00;
    pDMAch->CConfig = 0x00;

    /* Assign Linker List Item value */
    pDMAch->CLLI = Dmalli;	
	
    switch (TransferType)
    {
    // Memory to memory
    case GPDMA_TRANSFERTYPE_M2M:
        // Assign physical source and destination address
        pDMAch->CSrcAddr = SrcMemAddr;
        pDMAch->CDestAddr = DstMemAddr;
        pDMAch->CControl  = 
		                      GPDMA_DMACCxControl_TransferSize(TransferSize) \
                        | GPDMA_DMACCxControl_SBSize(BurstSize) \
                        | GPDMA_DMACCxControl_DBSize(BurstSize) \
                        | GPDMA_DMACCxControl_SWidth(TransferWidth) \
                        | GPDMA_DMACCxControl_DWidth(TransferWidth) \
                        | GPDMA_DMACCxControl_SI \
                        | GPDMA_DMACCxControl_DI \
                        | GPDMA_DMACCxControl_I;
        break;
    // Memory to peripheral
    case GPDMA_TRANSFERTYPE_M2P:
    case GPDMA_TRANSFERTYPE_M2P_DEST_CTRL:
        // Assign physical source
        pDMAch->CSrcAddr = SrcMemAddr;
        // Assign peripheral destination address
        pDMAch->CDestAddr = (uint32_t)DMA_LUTPerAddr[DstPeriph]; 
        pDMAch->CControl = 
													GPDMA_DMACCxControl_TransferSize((uint32_t)TransferSize) \
                        | GPDMA_DMACCxControl_SBSize((uint32_t)BurstSize) \
                        | GPDMA_DMACCxControl_DBSize((uint32_t)BurstSize) \
                        | GPDMA_DMACCxControl_SWidth((uint32_t)TransferWidth) \
                        | GPDMA_DMACCxControl_DWidth((uint32_t)TransferWidth) \
                        | GPDMA_DMACCxControl_SI \
                        | GPDMA_DMACCxControl_I;
        break;
    // Peripheral to memory
    case GPDMA_TRANSFERTYPE_P2M:
    case GPDMA_TRANSFERTYPE_P2M_SRC_CTRL:
        // Assign peripheral source address
        pDMAch->CSrcAddr = (uint32_t)DMA_LUTPerAddr[SrcPeriph];
        // Assign memory destination address
        pDMAch->CDestAddr = DstMemAddr;
        pDMAch->CControl  = 
													GPDMA_DMACCxControl_TransferSize((uint32_t)TransferSize) \
                        | GPDMA_DMACCxControl_SBSize((uint32_t)BurstSize) \
                        | GPDMA_DMACCxControl_DBSize((uint32_t)BurstSize) \
                        | GPDMA_DMACCxControl_SWidth((uint32_t)TransferWidth) \
                        | GPDMA_DMACCxControl_DWidth((uint32_t)TransferWidth) \
                        | GPDMA_DMACCxControl_DI \
                        | GPDMA_DMACCxControl_I;
        break;
    // Peripheral to peripheral
    case GPDMA_TRANSFERTYPE_P2P:
        // Assign peripheral source address
       pDMAch->CSrcAddr = (uint32_t)DMA_LUTPerAddr[SrcPeriph];
        // Assign peripheral destination address
       pDMAch->CDestAddr = (uint32_t)DMA_LUTPerAddr[DstPeriph];

       pDMAch->CControl = GPDMA_DMACCxControl_TransferSize((uint32_t)TransferSize) \
                        | GPDMA_DMACCxControl_SBSize((uint32_t)BurstSize) \
                        | GPDMA_DMACCxControl_DBSize((uint32_t)BurstSize) \
                        | GPDMA_DMACCxControl_SWidth((uint32_t)TransferWidth) \
                        | GPDMA_DMACCxControl_DWidth((uint32_t)TransferWidth) \
                        | GPDMA_DMACCxControl_I;
        break;
     }	
//Configure DAM Request Select register
    if((SrcPeriph != 8)&&(SrcPeriph != 9))
    {
        if (SrcPeriph > 15)
        {
            LPC_SC->DMAREQSEL |= (1<< (SrcPeriph - 16));
        } else {
            LPC_SC->DMAREQSEL &= ~(1<<(SrcPeriph));
        }
    }
    if((DstPeriph != 8)&&(DstPeriph != 9))
    {
        if (DstPeriph > 15)
        {
            LPC_SC->DMAREQSEL |= (1<< (DstPeriph - 16));
        } else {
            LPC_SC->DMAREQSEL &= ~(1<<(DstPeriph));
        }
    }

    /* Enable DMA channels, little endian */
    LPC_GPDMA->Config = (0x01);
    while (!(LPC_GPDMA->Config & 0x01));
		
    // Calculate DMA connection
if (SrcPeriph > 15) {SrcPeriph = SrcPeriph -16;}
if (DstPeriph > 15) {DstPeriph = DstPeriph -16;}
		
//Configure GPDMA Config register
   pDMAch->CConfig = GPDMA_DMACCxConfig_ITC 
									 | GPDMA_DMACCxConfig_TransferType((uint32_t)TransferType) \
									 | GPDMA_DMACCxConfig_SrcPeripheral(SrcPeriph) \
									 | GPDMA_DMACCxConfig_DestPeripheral(DstPeriph);		
	}