/*ISR*----------------------------------------------------------------- * * Function Name : card_detect_isr * Returned Value : void * Comments : * *END------------------------------------------------------------------*/ void card_detect_isr(void *lwsem_ptr) { GPIO_DRV_ClearPinIntFlag(CDET_PIN->pinName); /* Post card_detect semaphore */ _lwsem_post(lwsem_ptr); }
// handler associated to SW1 (labeled SW2 on board) void SW1_Intr_Handler(void) { static uint32_t c_ifsr; // port c interrupt flag status register uint32_t c_portBaseAddr = g_portBaseAddr[GPIO_EXTRACT_PORT(kGpioSW1)]; uint32_t portPinMask = (1 << GPIO_EXTRACT_PIN(kGpioSW1)); CPU_CRITICAL_ENTER(); // enter critical section (disable interrupts) OSIntEnter(); // notify to scheduler the beginning of an ISR ("This allows ?C/OS-III to keep track of interrupt nesting") c_ifsr = PORT_HAL_GetPortIntFlag(c_portBaseAddr); // get intr flag reg related to port C if( (c_ifsr & portPinMask) ) // check if kGpioSW1 generated the interrupt [pin 6 -> 7th flag (flags start with index 0)] { //sem_sw1_post OSSemPost(&MySem1, OS_OPT_POST_1 + OS_OPT_POST_NO_SCHED, &os_err); } GPIO_DRV_ClearPinIntFlag( kGpioSW1 ); CPU_CRITICAL_EXIT(); // renable interrupts OSIntExit(); /* notify to scheduler the end of an ISR ("determines if a higher priority task is ready-to-run. If so, the interrupt returns to the higher priority task instead of the interrupted task.") */ }