void gpioConfig(uint32_t inst, uint32_t pin, uint32_t opt)
{
uint32_t base = inst2Base[inst];
/* GPIO Clock */
switch (inst) {
case GPIO_1:
CM_MODULEMODE_ENABLE(CM_PER_GPIO1_CLKCTRL);
CM_PER_GPIO1_CLKCTRL |= BIT_18; /* Debounce Clk */
while(!(CM_PER_L4LS_CLKSTCTRL & CM_CLKACTIVITY_GPIO_1_GDBCLK))
;
break;
}
/* Pin mux */
switch (inst) {
case GPIO_1:
if (pin >= 16 && pin <= 27)
CTRLM_CONF_GPMC_A(pin-16) = CTRLM_CONF_MUXMODE(7);
break;
}
/* I/O */
if (opt & GPIO_CFG_OUTPUT)
GPIO_OE(base) &= ~(1 << pin);
else if (opt & GPIO_CFG_INPUT)
GPIO_OE(base) |= (1 << pin);
}
static void get_gpio_settings(void)
{
unsigned long pmc_ctrl;
int i;
int j;
pmc_ctrl = readl(IO_ADDRESS(TEGRA_PMC_BASE));
printk(KERN_INFO "pICS_%s: pmc_ctrl = 0x%lX...\n",__func__,pmc_ctrl);
for (i = 0; i < 7; i++) {
for (j = 0; j < 4; j++) {
int gpio = tegra_gpio_compose(i, j, 0);
printk(KERN_INFO "pICS_%s: %d:%d %02x %02x %02x %02x %02x %02x %06x\n",__func__,
i, j,
__raw_readl(GPIO_CNF(gpio)),
__raw_readl(GPIO_OE(gpio)),
__raw_readl(GPIO_OUT(gpio)),
__raw_readl(GPIO_IN(gpio)),
__raw_readl(GPIO_INT_STA(gpio)),
__raw_readl(GPIO_INT_ENB(gpio)),
__raw_readl(GPIO_INT_LVL(gpio)));
}
}
}
