static void mask_ack_giuint_low(struct irq_data *d) { unsigned int pin; pin = GPIO_PIN_OF_IRQ(d->irq); giu_clear(GIUINTENL, 1 << pin); giu_write(GIUINTSTATL, 1 << pin); }
static void mask_ack_giuint_high(unsigned int irq) { unsigned int pin; pin = GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET; giu_clear(GIUINTENH, 1 << pin); giu_write(GIUINTSTATH, 1 << pin); }
static void mask_ack_giuint_low(unsigned int irq) { unsigned int pin; pin = GPIO_PIN_OF_IRQ(irq); giu_clear(GIUINTENL, 1 << pin); giu_write(GIUINTSTATL, 1 << pin); }
static unsigned int startup_giuint_high_irq(unsigned int irq) { unsigned int pin; pin = GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET; giu_write(GIUINTSTATH, 1 << pin); giu_set(GIUINTENH, 1 << pin); return 0; }
static unsigned int startup_giuint_low_irq(unsigned int irq) { unsigned int pin; pin = GPIO_PIN_OF_IRQ(irq); giu_write(GIUINTSTATL, 1 << pin); giu_set(GIUINTENL, 1 << pin); return 0; }
static void unmask_giuint_low(unsigned int irq) { giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq)); }
static void ack_giuint_low(unsigned int irq) { giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(irq)); }
static int giu_probe(struct platform_device *pdev) { struct resource *res; unsigned int trigger, i, pin; struct irq_chip *chip; int irq, ret; switch (pdev->id) { case GPIO_50PINS_PULLUPDOWN: giu_flags = GPIO_HAS_PULLUPDOWN_IO; vr41xx_gpio_chip.ngpio = 50; break; case GPIO_36PINS: vr41xx_gpio_chip.ngpio = 36; break; case GPIO_48PINS_EDGE_SELECT: giu_flags = GPIO_HAS_INTERRUPT_EDGE_SELECT; vr41xx_gpio_chip.ngpio = 48; break; default: dev_err(&pdev->dev, "GIU: unknown ID %d\n", pdev->id); return -ENODEV; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -EBUSY; giu_base = ioremap(res->start, resource_size(res)); if (!giu_base) return -ENOMEM; vr41xx_gpio_chip.dev = &pdev->dev; ret = gpiochip_add(&vr41xx_gpio_chip); if (!ret) { iounmap(giu_base); return -ENODEV; } giu_write(GIUINTENL, 0); giu_write(GIUINTENH, 0); trigger = giu_read(GIUINTTYPH) << 16; trigger |= giu_read(GIUINTTYPL); for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) { pin = GPIO_PIN_OF_IRQ(i); if (pin < GIUINT_HIGH_OFFSET) chip = &giuint_low_irq_chip; else chip = &giuint_high_irq_chip; if (trigger & (1 << pin)) irq_set_chip_and_handler(i, chip, handle_edge_irq); else irq_set_chip_and_handler(i, chip, handle_level_irq); } irq = platform_get_irq(pdev, 0); if (irq < 0 || irq >= nr_irqs) return -EBUSY; return cascade_irq(irq, giu_get_irq); }
static void unmask_giuint_high(struct irq_data *d) { giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET)); }
static void ack_giuint_high(struct irq_data *d) { giu_write(GIUINTSTATH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET)); }
static void end_giuint_low_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq)); }
static void unmask_giuint_high(unsigned int irq) { giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET)); }
static void ack_giuint_low(struct irq_data *d) { giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(d->irq)); }
static void end_giuint_high_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET)); }
static void enable_giuint_high_irq(unsigned int irq) { giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET)); }
static void shutdown_giuint_high_irq(unsigned int irq) { giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET)); }
static void ack_giuint_high(unsigned int irq) { giu_write(GIUINTSTATH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET)); }
static void shutdown_giuint_low_irq(unsigned int irq) { giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq)); }
static void enable_giuint_low_irq(unsigned int irq) { giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq)); }
static int __devinit giu_probe(struct platform_device *dev) { struct resource *res; unsigned int trigger, i, pin; struct irq_chip *chip; int irq, retval; switch (dev->id) { case GPIO_50PINS_PULLUPDOWN: giu_flags = GPIO_HAS_PULLUPDOWN_IO; giu_nr_pins = 50; break; case GPIO_36PINS: giu_nr_pins = 36; break; case GPIO_48PINS_EDGE_SELECT: giu_flags = GPIO_HAS_INTERRUPT_EDGE_SELECT; giu_nr_pins = 48; break; default: printk(KERN_ERR "GIU: unknown ID %d\n", dev->id); return -ENODEV; } res = platform_get_resource(dev, IORESOURCE_MEM, 0); if (!res) return -EBUSY; giu_base = ioremap(res->start, res->end - res->start + 1); if (!giu_base) return -ENOMEM; retval = register_chrdev(major, "GIU", &gpio_fops); if (retval < 0) { iounmap(giu_base); giu_base = NULL; return retval; } if (major == 0) { major = retval; printk(KERN_INFO "GIU: major number %d\n", major); } spin_lock_init(&giu_lock); giu_write(GIUINTENL, 0); giu_write(GIUINTENH, 0); trigger = giu_read(GIUINTTYPH) << 16; trigger |= giu_read(GIUINTTYPL); for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) { pin = GPIO_PIN_OF_IRQ(i); if (pin < GIUINT_HIGH_OFFSET) chip = &giuint_low_irq_chip; else chip = &giuint_high_irq_chip; if (trigger & (1 << pin)) set_irq_chip_and_handler(i, chip, handle_edge_irq); else set_irq_chip_and_handler(i, chip, handle_level_irq); } irq = platform_get_irq(dev, 0); if (irq < 0 || irq >= NR_IRQS) return -EBUSY; return cascade_irq(irq, giu_get_irq); }
static void unmask_giuint_low(struct irq_data *d) { giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq)); }