void
imxgpio_v6_set_dir(struct imxgpio_softc *sc, unsigned int gpio, unsigned int dir)
{
int s;
u_int32_t val;
s = splhigh();
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_GDIR);
if (dir == IMXGPIO_DIR_OUT)
val |= 1 << GPIO_PIN_TO_OFFSET(gpio);
else
val &= ~(1 << GPIO_PIN_TO_OFFSET(gpio));
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_GDIR, val);
splx(s);
}
void
omgpio_set_dir(unsigned int gpio, unsigned int dir)
{
struct omgpio_softc *sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
int s;
u_int32_t reg;
s = splhigh();
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_DATAIN);
if (dir == OMGPIO_DIR_IN)
reg |= 1 << GPIO_PIN_TO_OFFSET(gpio);
else
reg &= ~(1 << GPIO_PIN_TO_OFFSET(gpio));
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_OE, reg);
splx(s);
}
void
omgpio_pin_dir_write(struct omgpio_softc *sc, unsigned int gpio,
unsigned int dir)
{
int s;
u_int32_t reg;
s = splhigh();
reg = READ4(sc, sc->sc_regs.oe);
if (dir == OMGPIO_DIR_IN)
reg |= 1 << GPIO_PIN_TO_OFFSET(gpio);
else
reg &= ~(1 << GPIO_PIN_TO_OFFSET(gpio));
WRITE4(sc, sc->sc_regs.oe, reg);
splx(s);
}
void
imxgpio_v6_clear_bit(struct imxgpio_softc *sc, unsigned int gpio)
{
u_int32_t val;
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_DR);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_DR,
val & ~(1 << GPIO_PIN_TO_OFFSET(gpio)));
}
int
omgpio_pin_dir_read(struct omgpio_softc *sc, unsigned int gpio)
{
u_int32_t reg;
reg = READ4(sc, sc->sc_regs.oe);
if (reg & (1 << GPIO_PIN_TO_OFFSET(gpio)))
return OMGPIO_DIR_IN;
else
return OMGPIO_DIR_OUT;
}
void
omgpio_intr_disestablish(void *cookie)
{
int psw;
struct intrhand *ih = cookie;
struct omgpio_softc *sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(ih->ih_gpio)];
int gpio = ih->ih_gpio;
psw = disable_interrupts(I32_bit);
ih = sc->sc_handlers[GPIO_PIN_TO_OFFSET(gpio)];
sc->sc_handlers[GPIO_PIN_TO_OFFSET(gpio)] = NULL;
evcount_detach(&ih->ih_count);
free(ih, M_DEVBUF);
omgpio_intr_level(gpio, IST_NONE);
omgpio_intr_mask(gpio);
omgpio_clear_intr(gpio); /* Just in case */
omgpio_recalc_interrupts(sc);
restore_interrupts(psw);
}
unsigned int
imxgpio_v6_get_dir(struct imxgpio_softc *sc, unsigned int gpio)
{
int s;
u_int32_t val;
s = splhigh();
val = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_GDIR);
if (val & (1 << GPIO_PIN_TO_OFFSET(gpio)))
val = IMXGPIO_DIR_OUT;
else
val = IMXGPIO_DIR_IN;
splx(s);
return val;
}
void
omgpio_intr_level(unsigned int gpio, unsigned int level)
{
u_int32_t fe, re, l0, l1, bit;
struct omgpio_softc *sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
int s;
s = splhigh();
fe = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_FALLINGDETECT);
re = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_RISINGDETECT);
l0 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_LEVELDETECT0);
l1 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, GPIO_LEVELDETECT1);
bit = 1 << GPIO_PIN_TO_OFFSET(gpio);
switch (level) {
case IST_NONE:
fe &= ~bit;
re &= ~bit;
l0 &= ~bit;
l1 &= ~bit;
break;
case IST_EDGE_FALLING:
fe |= bit;
re &= ~bit;
l0 &= ~bit;
l1 &= ~bit;
break;
case IST_EDGE_RISING:
fe &= ~bit;
re |= bit;
l0 &= ~bit;
l1 &= ~bit;
break;
case IST_PULSE: /* XXX */
/* FALLTHRU */
case IST_EDGE_BOTH:
fe |= bit;
re |= bit;
l0 &= ~bit;
l1 &= ~bit;
break;
case IST_LEVEL_LOW:
fe &= ~bit;
re &= ~bit;
l0 |= bit;
l1 &= ~bit;
break;
case IST_LEVEL_HIGH:
fe &= ~bit;
re &= ~bit;
l0 &= ~bit;
l1 |= bit;
break;
break;
default:
panic("omgpio_intr_level: bad level: %d", level);
break;
}
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_FALLINGDETECT, fe);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_RISINGDETECT, re);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_LEVELDETECT0, l0);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, GPIO_LEVELDETECT1, l1);
splx(s);
}
void
omgpio_intr_level(struct omgpio_softc *sc, unsigned int gpio, unsigned int level)
{
u_int32_t fe, re, l0, l1, bit;
struct omgpio_softc *sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(gpio)];
int s;
s = splhigh();
fe = READ4(sc, sc->sc_regs.fallingdetect);
re = READ4(sc, sc->sc_regs.risingdetect);
l0 = READ4(sc, sc->sc_regs.leveldetect0);
l1 = READ4(sc, sc->sc_regs.leveldetect1);
bit = 1 << GPIO_PIN_TO_OFFSET(gpio);
switch (level) {
case IST_NONE:
fe &= ~bit;
re &= ~bit;
l0 &= ~bit;
l1 &= ~bit;
break;
case IST_EDGE_FALLING:
fe |= bit;
re &= ~bit;
l0 &= ~bit;
l1 &= ~bit;
break;
case IST_EDGE_RISING:
fe &= ~bit;
re |= bit;
l0 &= ~bit;
l1 &= ~bit;
break;
case IST_PULSE: /* XXX */
/* FALLTHRU */
case IST_EDGE_BOTH:
fe |= bit;
re |= bit;
l0 &= ~bit;
l1 &= ~bit;
break;
case IST_LEVEL_LOW:
fe &= ~bit;
re &= ~bit;
l0 |= bit;
l1 &= ~bit;
break;
case IST_LEVEL_HIGH:
fe &= ~bit;
re &= ~bit;
l0 &= ~bit;
l1 |= bit;
break;
default:
panic("omgpio_intr_level: bad level: %d", level);
break;
}
WRITE4(sc, sc->sc_regs.fallingdetect, fe);
WRITE4(sc, sc->sc_regs.risingdetect, re);
WRITE4(sc, sc->sc_regs.leveldetect0, l0);
WRITE4(sc, sc->sc_regs.leveldetect1, l1);
splx(s);
}
