ts_unit TS unit list
ts_reg TS register list
ts_mod TS modifier list
*/
#define IOLN_TS 004
DIB ts_dib = {
IOBA_AUTO, IOLN_TS, &ts_rd, &ts_wr,
1, IVCL (TS), VEC_AUTO, { NULL }
};
UNIT ts_unit = { UDATA (&ts_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) };
REG ts_reg[] = {
{ GRDATAD (TSSR, tssr, DEV_RDX, 16, 0, "status register") },
{ GRDATAD (TSBA, tsba, DEV_RDX, 22, 0, "bus address register") },
{ GRDATAD (TSDBX, tsdbx, DEV_RDX, 8, 0, "data buffer extension register") },
{ GRDATAD (CHDR, cmdhdr, DEV_RDX, 16, 0, "command packet header") },
{ GRDATAD (CADL, cmdadl, DEV_RDX, 16, 0, "command packet low address or count") },
{ GRDATAD (CADH, cmdadh, DEV_RDX, 16, 0, "command packet high address") },
{ GRDATAD (CLNT, cmdlnt, DEV_RDX, 16, 0, "command packet length") },
{ GRDATAD (MHDR, msghdr, DEV_RDX, 16, 0, "message packet header") },
{ GRDATAD (MRFC, msgrfc, DEV_RDX, 16, 0, "message packet residual frame count") },
{ GRDATAD (MXS0, msgxs0, DEV_RDX, 16, 0, "message packet extended status 0") },
{ GRDATAD (MXS1, msgxs1, DEV_RDX, 16, 0, "message packet extended status 1") },
{ GRDATAD (MXS2, msgxs2, DEV_RDX, 16, 0, "message packet extended status 2") },
{ GRDATAD (MXS3, msgxs3, DEV_RDX, 16, 0, "message packet extended status 3") },
{ GRDATAD (MSX4, msgxs4, DEV_RDX, 16, 0, "message packet extended status 4") },
{ GRDATAD (WADL, wchadl, DEV_RDX, 16, 0, "write char packet low address") },
{ GRDATAD (WADH, wchadh, DEV_RDX, 16, 0, "write char packet high address") },
#define IOLN_PTR 004
DIB ptr_dib = {
IOBA_AUTO, IOLN_PTR, &ptr_rd, &ptr_wr,
1, IVCL (PTR), VEC_AUTO, { NULL }
};
UNIT ptr_unit = {
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
SERIAL_IN_WAIT
};
extern DEVICE ptr_dev;
REG ptr_reg[] = {
{ GRDATAD (BUF, ptr_unit.buf, DEV_RDX, 8, 0, "last data item processed") },
{ GRDATAD (CSR, ptr_csr, DEV_RDX, 16, 0, "control/status register") },
{ FLDATAD (INT, int_req, INT_V_PTR, "interrupt pending flag") },
{ FLDATAD (ERR, ptr_csr, CSR_V_ERR, "error flag (CSR<15>)") },
{ FLDATAD (BUSY, ptr_csr, CSR_V_BUSY, "busy flag (CSR<11>)") },
{ FLDATAD (DONE, ptr_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, ptr_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, ptr_unit.pos, T_ADDR_W, "position in the input file"), PV_LEFT },
{ DRDATAD (TIME, ptr_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
{ FLDATAD (STOP_IOE, ptr_stopioe, 0, "stop on I/O error") },
{ FLDATA (DEVDIS, ptr_dev.flags, DEV_V_DIS), REG_HRO },
{ GRDATA (DEVADDR, ptr_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, ptr_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
t_stat ng_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
const char *ng_description (DEVICE *dptr);
#define IOLN_NG 4
DIB ng_dib = {
IOBA_AUTO, IOLN_NG, &ng_rd, &ng_wr,
4, IVCL(NG), VEC_AUTO, {NULL}, IOLN_NG
};
UNIT ng_unit = {
UDATA (&ng_svc, 0, 0), NG_DELAY
};
REG ng_reg[] = {
{ DRDATAD (CYCLE, ng_unit.wait, 24, "NG cycle"), REG_NZ + PV_LEFT },
{ GRDATAD(TYPE, ng_type, 16, 16, 0, "Hardware type"), REG_FIT},
{ GRDATAD(SCALE, ng_scale, 16, 16, 0, "Hardware type"), REG_FIT},
{ NULL }
};
MTAB ng_mod[] = {
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "TYPE", "TYPE={DAZZLE|LOGO}",
&ng_set_type, &ng_show_type, NULL, "Hardware Type" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "SCALE", "SCALE={1|2|4|8}",
&ng_set_scale, &ng_show_scale, NULL, "Pixel Scale Factor" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 020, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL, "Bus address" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "VECTOR", "VECTOR",
&set_vec, &show_vec, NULL, "Interrupt vector" },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "AUTOCONFIGURE",
&set_addr_flt, NULL, NULL, "Enable autoconfiguration of address & vector" },
/* TTIx data structures
ttix_dev TTIx device descriptor
ttix_unit TTIx unit descriptor
ttix_reg TTIx register list
ttix_mod TTIx modifiers list
*/
DIB ttix_dib = { DEV_KJ8, 8,
{ &ttix, &ttox, &ttix, &ttox, &ttix, &ttox, &ttix, &ttox } };
UNIT ttix_unit = { UDATA (&ttix_svc, UNIT_IDLE|UNIT_ATTABLE, 0), SERIAL_IN_WAIT };
REG ttix_reg[] = {
{ BRDATAD (BUF, ttix_buf, 8, 8, TTX_LINES, "input buffer, lines 0 to 3") },
{ GRDATAD (DONE, dev_done, 8, TTX_LINES, INT_V_TTI1, "device done flag (line 0 rightmost)") },
{ GRDATAD (ENABLE, int_enable, 8, TTX_LINES, INT_V_TTI1, "interrupt enable flag") },
{ GRDATAD (INT, int_req, 8, TTX_LINES, INT_V_TTI1, "interrupt pending flag") },
{ DRDATAD (TIME, ttix_unit.wait, 24, "initial polling interval"), REG_NZ + PV_LEFT },
{ DRDATAD (TPS, ttx_tps, 10, "polls per second after calibration"), REG_NZ + PV_LEFT },
{ ORDATA (DEVNUM, ttix_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB ttix_mod[] = {
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &ttx_desc },
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, (void *) &ttx_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &ttx_desc },
dci_reg DCI register list
*/
#define IOLN_DC 010
DIB dci_dib = {
IOBA_AUTO, IOLN_DC * DCX_LINES, &dcx_rd, &dcx_wr,
2, IVCL (DCI), VEC_AUTO, { &dci_iack, &dco_iack }, IOLN_DC,
};
UNIT dci_unit = { UDATA (&dci_svc, 0, 0), TMLN_SPD_9600_BPS };
REG dci_reg[] = {
{ BRDATAD (BUF, dci_buf, DEV_RDX, 8, DCX_LINES, "input control/stats register") },
{ BRDATAD (CSR, dci_csr, DEV_RDX, 16, DCX_LINES, "input buffer") },
{ GRDATAD (IREQ, dci_ireq, DEV_RDX, DCX_LINES, 0, "interrupt requests") },
{ DRDATAD (TIME, dci_unit.wait, 24, "input polling interval"), PV_LEFT },
{ DRDATA (LINES, dcx_desc.lines, 6), REG_HRO },
{ GRDATA (DEVADDR, dci_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVIOLN, dci_dib.lnt, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, dci_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB dci_mod[] = {
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &dcx_desc, "Disconnect a specific line" },
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &dcx_desc, "Display a summary of line states" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &dcx_desc, "Display current connections" },
