static irqreturn_t gt64120_irq(int irq, void *dev_id) { unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask; int handled = 0; irq_src = GT_READ(GT_INTRCAUSE_OFS); irq_src_mask = GT_READ(GT_INTRMASK_OFS); int_high_src = GT_READ(GT_HINTRCAUSE_OFS); int_high_src_mask = GT_READ(GT_HINTRMASK_OFS); irq_src = irq_src & irq_src_mask; int_high_src = int_high_src & int_high_src_mask; if (irq_src & 0x00000800) { /* Check for timer interrupt */ handled = 1; irq_src &= ~0x00000800; do_timer(1); #ifndef CONFIG_SMP update_process_times(user_mode(get_irq_regs())); #endif } GT_WRITE(GT_INTRCAUSE_OFS, 0); GT_WRITE(GT_HINTRCAUSE_OFS, 0); return IRQ_HANDLED; }
int __init prom_init(int argc, char **argv, char **envp) { prom_argc = argc; prom_argv = argv; prom_envp = envp; mips_display_message("LINUX"); /* * Setup the North bridge to do Master byte-lane swapping when * running in bigendian. */ #if defined(__MIPSEL__) GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | GT_PCI0_CMD_SBYTESWAP_BIT); #else GT_WRITE(GT_PCI0_CMD_OFS, 0); #endif #if defined(CONFIG_MIPS_MALTA) set_io_port_base(MALTA_PORT_BASE); #else set_io_port_base(KSEG1); #endif setup_prom_printf(0); prom_printf("\nLINUX started...\n"); prom_init_cmdline(); prom_meminit(); return 0; }
int gt641xx_timer0_state(void) { if (GT_READ(GT_TC0_OFS)) return 0; GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ); GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK); return 1; }
static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type, struct pci_bus *bus, unsigned int devfn, int where, u32 * data) { unsigned char busnum = bus->number; u32 intr; if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0))) return -1; /* */ /* */ GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)); /* */ GT_WRITE(GT_PCI0_CFGADDR_OFS, (busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) | (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | GT_PCI0_CFGADDR_CONFIGEN_BIT); if (access_type == PCI_ACCESS_WRITE) { if (busnum == 0 && PCI_SLOT(devfn) == 0) { /* */ GT_WRITE(GT_PCI0_CFGDATA_OFS, *data); } else __GT_WRITE(GT_PCI0_CFGDATA_OFS, *data); } else { if (busnum == 0 && PCI_SLOT(devfn) == 0) { /* */ *data = GT_READ(GT_PCI0_CFGDATA_OFS); } else *data = __GT_READ(GT_PCI0_CFGDATA_OFS); } /* */ intr = GT_READ(GT_INTRCAUSE_OFS); if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) { /* */ /* */ GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)); return -1; } return 0; }
static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type, struct pci_bus *bus, unsigned int devfn, int where, u32 * data) { unsigned char busnum = bus->number; u32 intr; if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0))) return -1; /* Because of a bug in the galileo (for slot 31). */ /* Clear cause register bits */ GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)); /* Setup address */ GT_WRITE(GT_PCI0_CFGADDR_OFS, (busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) | (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) | GT_PCI0_CFGADDR_CONFIGEN_BIT); if (access_type == PCI_ACCESS_WRITE) { if (busnum == 0 && PCI_SLOT(devfn) == 0) { /* * The Galileo system controller is acting * differently than other devices. */ GT_WRITE(GT_PCI0_CFGDATA_OFS, *data); } else __GT_WRITE(GT_PCI0_CFGDATA_OFS, *data); } else { if (busnum == 0 && PCI_SLOT(devfn) == 0) { /* * The Galileo system controller is acting * differently than other devices. */ *data = GT_READ(GT_PCI0_CFGDATA_OFS); } else *data = __GT_READ(GT_PCI0_CFGDATA_OFS); } /* Check for master or target abort */ intr = GT_READ(GT_INTRCAUSE_OFS); if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) { /* Error occurred */ /* Clear bits */ GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)); return -1; } return 0; }
void __init plat_timer_setup(struct irqaction *irq) { /* Load timer value for HZ (TCLK is 50MHz) */ GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ); /* Enable timer */ GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); /* Register interrupt */ setup_irq(COBALT_GALILEO_IRQ, irq); /* Enable interrupt */ GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS)); }
static void mask_ack_gt641xx_irq(struct irq_data *d) { unsigned long flags; u32 cause, mask; raw_spin_lock_irqsave(>641xx_irq_lock, flags); mask = GT_READ(GT_INTRMASK_OFS); mask &= ~GT641XX_IRQ_TO_BIT(d->irq); GT_WRITE(GT_INTRMASK_OFS, mask); cause = GT_READ(GT_INTRCAUSE_OFS); cause &= ~GT641XX_IRQ_TO_BIT(d->irq); GT_WRITE(GT_INTRCAUSE_OFS, cause); raw_spin_unlock_irqrestore(>641xx_irq_lock, flags); }
static void gt64240_p0int_irq(int irq, void *dev_id, struct pt_regs *regs) { uint32_t irq_src, irq_src_mask; int handled; /* get the low interrupt cause register */ GT_READ(LOW_INTERRUPT_CAUSE_REGISTER, &irq_src); /* get the mask register for this pin */ GT_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, &irq_src_mask); /* mask off only the interrupts we're interested in */ irq_src = irq_src & irq_src_mask; handled = 0; /* Check for timer interrupt */ if (irq_src & 0x00000100) { handled = 1; irq_src &= ~0x00000100; /* Clear any pending cause bits */ GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0); /* handle the timer call */ do_timer(regs); } if (irq_src) { printk(KERN_INFO "UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n", irq_src); } }
void __init gt641xx_irq_init(void) { int i; GT_WRITE(GT_INTRMASK_OFS, 0); GT_WRITE(GT_INTRCAUSE_OFS, 0); /* * bit0 : logical or of all the interrupt bits. * bit30: logical or of bits[29:26,20:1]. * bit31: logical or of bits[25:1]. */ for (i = 1; i < 30; i++) irq_set_chip_and_handler(GT641XX_IRQ_BASE + i, >641xx_irq_chip, handle_level_irq); }
static void gt641xx_timer0_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { u32 ctrl; raw_spin_lock(>641xx_timer_lock); ctrl = GT_READ(GT_TC_CONTROL_OFS); ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); switch (mode) { case CLOCK_EVT_MODE_PERIODIC: ctrl |= GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK; break; case CLOCK_EVT_MODE_ONESHOT: ctrl |= GT_TC_CONTROL_ENTC0_MSK; break; default: break; } GT_WRITE(GT_TC_CONTROL_OFS, ctrl); raw_spin_unlock(>641xx_timer_lock); }
static inline void galileo_irq(void) { unsigned int mask, pending, devfn; mask = GT_READ(GT_INTRMASK_OFS); pending = GT_READ(GT_INTRCAUSE_OFS) & mask; if (pending & GT_INTR_T0EXP_MSK) { GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK); do_IRQ(COBALT_GALILEO_IRQ); } else if (pending & GT_INTR_RETRYCTR0_MSK) { devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8; GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK); printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n", PCI_SLOT(devfn), PCI_FUNC(devfn)); } else {
/* * This will ignore the standard MIPS timer interrupt handler that is passed in * as *irq (=irq0 in ../kernel/time.c). We will do our own timer interrupt * handling. */ void gt64120_time_init(void) { static struct irqaction timer; /* Disable timer first */ GT_WRITE(GT_TC_CONTROL_OFS, 0); /* Load timer value for 100 Hz */ GT_WRITE(GT_TC3_OFS, Sys_clock / 100); /* * Create the IRQ structure entry for the timer. Since we're too early * in the boot process to use the "request_irq()" call, we'll hard-code * the values to the correct interrupt line. */ timer.handler = gt64120_irq; timer.flags = IRQF_SHARED | IRQF_DISABLED; timer.name = "timer"; timer.dev_id = NULL; timer.next = NULL; timer.mask = CPU_MASK_NONE; irq_desc[GT_TIMER].action = &timer; enable_irq(GT_TIMER); /* Enable timer ints */ GT_WRITE(GT_TC_CONTROL_OFS, 0xc0); /* clear Cause register first */ GT_WRITE(GT_INTRCAUSE_OFS, 0x0); /* Unmask timer int */ GT_WRITE(GT_INTRMASK_OFS, 0x800); /* Clear High int register */ GT_WRITE(GT_HINTRCAUSE_OFS, 0x0); /* Mask All interrupts at High cause interrupt */ GT_WRITE(GT_HINTRMASK_OFS, 0x0); }
/* * This will ignore the standard MIPS timer interrupt handler that is passed * in as *irq (=irq0 in ../kernel/time.c). We will do our own timer interrupt * handling. */ void galileo_time_init(struct irqaction *irq) { extern irq_desc_t irq_desc[NR_IRQS]; static struct irqaction timer; /* Disable timer first */ GT_WRITE(GT_TC_CONTROL_OFS, 0); /* Load timer value for 100 Hz */ GT_WRITE(GT_TC3_OFS, Sys_clock / 100); /* * Create the IRQ structure entry for the timer. Since we're too early * in the boot process to use the "request_irq()" call, we'll hard-code * the values to the correct interrupt line. */ timer.handler = &galileo_irq; timer.flags = SA_SHIRQ; timer.name = "timer"; timer.dev_id = NULL; timer.next = NULL; timer.mask = 0; irq_desc[TIMER].action = &timer; /* Enable timer ints */ GT_WRITE(GT_TC_CONTROL_OFS, 0xc0); /* clear Cause register first */ GT_WRITE(GT_INTRCAUSE_OFS, 0x0); /* Unmask timer int */ GT_WRITE(GT_INTRMASK_OFS, 0x800); /* Clear High int register */ GT_WRITE(GT_HINTRCAUSE_OFS, 0x0); /* Mask All interrupts at High cause interrupt */ GT_WRITE(GT_HINTRMASK_OFS, 0x0); }
static int gt641xx_timer0_set_next_event(unsigned long delta, struct clock_event_device *evt) { u32 ctrl; raw_spin_lock(>641xx_timer_lock); ctrl = GT_READ(GT_TC_CONTROL_OFS); ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); ctrl |= GT_TC_CONTROL_ENTC0_MSK; GT_WRITE(GT_TC0_OFS, delta); GT_WRITE(GT_TC_CONTROL_OFS, ctrl); raw_spin_unlock(>641xx_timer_lock); return 0; }
static void unmask_gt641xx_irq(struct irq_data *d) { unsigned long flags; u32 mask; raw_spin_lock_irqsave(>641xx_irq_lock, flags); mask = GT_READ(GT_INTRMASK_OFS); mask |= GT641XX_IRQ_TO_BIT(d->irq); GT_WRITE(GT_INTRMASK_OFS, mask); raw_spin_unlock_irqrestore(>641xx_irq_lock, flags); }
static void gt64120_irq(int irq, void *dev_id, struct pt_regs *regs) { unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask; int handled = 0; irq_src = GT_READ(GT_INTRCAUSE_OFS); irq_src_mask = GT_READ(GT_INTRMASK_OFS); int_high_src = GT_READ(GT_HINTRCAUSE_OFS); int_high_src_mask = GT_READ(GT_HINTRMASK_OFS); irq_src = irq_src & irq_src_mask; int_high_src = int_high_src & int_high_src_mask; if (irq_src & 0x00000800) { /* Check for timer interrupt */ handled = 1; irq_src &= ~0x00000800; do_timer(regs); } GT_WRITE(GT_INTRCAUSE_OFS, 0); GT_WRITE(GT_HINTRCAUSE_OFS, 0); }
void __init pcibios_init(void) { printk("PCI: Probing PCI hardware on host bus 0.\n"); switch (mips_revision_corid) { case MIPS_REVISION_CORID_QED_RM5261: case MIPS_REVISION_CORID_CORE_LV: case MIPS_REVISION_CORID_CORE_FPGA: /* * Due to a bug in the Galileo system controller, we need * to setup the PCI BAR for the Galileo internal registers. * This should be done in the bios/bootprom and will be * fixed in a later revision of YAMON (the MIPS boards * boot prom). */ GT_WRITE(GT_PCI0_CFGADDR_OFS, (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */ (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/ ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/ GT_PCI0_CFGADDR_CONFIGEN_BIT ); /* Perform the write */ GT_WRITE( GT_PCI0_CFGDATA_OFS, PHYSADDR(GT64120_BASE)); pci_scan_bus(0, >64120_pci_ops, NULL); break; case MIPS_REVISION_CORID_BONITO64: case MIPS_REVISION_CORID_CORE_20K: pci_scan_bus(0, &bonito64_pci_ops, NULL); break; case MIPS_REVISION_CORID_CORE_MSC: pci_scan_bus(0, &msc_pci_ops, NULL); break; } malta_fixup(); }
static int gt641xx_timer0_set_periodic(struct clock_event_device *evt) { u32 ctrl; raw_spin_lock(>641xx_timer_lock); ctrl = GT_READ(GT_TC_CONTROL_OFS); ctrl |= GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK; GT_WRITE(GT_TC_CONTROL_OFS, ctrl); raw_spin_unlock(>641xx_timer_lock); return 0; }
static void gt64120_irq(int irq, void *dev_id, struct pt_regs *regs) { unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask; int handled = 0; irq_src = GT_READ(GT_INTRCAUSE_OFS); irq_src_mask = GT_READ(GT_INTRMASK_OFS); int_high_src = GT_READ(GT_HINTRCAUSE_OFS); int_high_src_mask = GT_READ(GT_HINTRMASK_OFS); irq_src = irq_src & irq_src_mask; int_high_src = int_high_src & int_high_src_mask; if (irq_src & 0x00000800) { /* Check for timer interrupt */ handled = 1; irq_src &= ~0x00000800; do_timer(regs); #ifndef CONFIG_SMP update_process_times(user_mode(regs)); #endif } GT_WRITE(GT_INTRCAUSE_OFS, 0); GT_WRITE(GT_HINTRCAUSE_OFS, 0); }
/** * Initialize GT64120 Interrupt Controller */ void gt64120_init_pic(void) { /* clear CPU Interrupt Cause Registers */ GT_WRITE(GT_INTRCAUSE_OFS, (0x1F << 21)); GT_WRITE(GT_HINTRCAUSE_OFS, 0x00); /* Disable all interrupts from GT64120 bridge chip */ GT_WRITE(GT_INTRMASK_OFS, 0x00); GT_WRITE(GT_HINTRMASK_OFS, 0x00); GT_WRITE(GT_PCI0_ICMASK_OFS, 0x00); GT_WRITE(GT_PCI0_HICMASK_OFS, 0x00); }
static int __init gt641xx_timer0_clockevent_init(void) { struct clock_event_device *cd; if (!gt641xx_base_clock) return 0; GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ); cd = >641xx_timer0_clockevent; cd->rating = 200 + gt641xx_base_clock / 10000000; clockevent_set_clock(cd, gt641xx_base_clock); cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd); cd->min_delta_ns = clockevent_delta2ns(0x300, cd); cd->cpumask = cpumask_of(0); clockevents_register_device(>641xx_timer0_clockevent); return setup_irq(GT641XX_TIMER0_IRQ, >641xx_timer0_irqaction); }
/* * This will ignore the standard MIPS timer interrupt handler * that is passed in as *irq (=irq0 in ../kernel/time.c). * We will do our own timer interrupt handling. */ void gt64240_time_init(void) { extern irq_desc_t irq_desc[NR_IRQS]; static struct irqaction timer; /* Stop the timer -- we'll use timer #0 */ GT_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0); /* Load timer value for 100 Hz */ GT_WRITE(TIMER_COUNTER0, bus_clock / 100); /* * Create the IRQ structure entry for the timer. Since we're too early * in the boot process to use the "request_irq()" call, we'll hard-code * the values to the correct interrupt line. */ timer.handler = >64240_p0int_irq; timer.flags = SA_SHIRQ | SA_INTERRUPT; timer.name = "timer"; timer.dev_id = NULL; timer.next = NULL; timer.mask = 0; irq_desc[6].action = &timer; enable_irq(6); /* Clear any pending cause bits */ GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0); /* Enable the interrupt for timer 0 */ GT_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1); /* Enable the timer interrupt for GT-64240 pin P0_INT# */ GT_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100); /* Configure and start the timer */ GT_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3); }
void __init mips_pcibios_init(void) { struct pci_controller *controller; unsigned long start, end, map, start1, end1, map1, map2, map3, mask; switch (mips_revision_corid) { case MIPS_REVISION_CORID_QED_RM5261: case MIPS_REVISION_CORID_CORE_LV: case MIPS_REVISION_CORID_CORE_FPGA: case MIPS_REVISION_CORID_CORE_FPGAR2: /* * Due to a bug in the Galileo system controller, we need * to setup the PCI BAR for the Galileo internal registers. * This should be done in the bios/bootprom and will be * fixed in a later revision of YAMON (the MIPS boards * boot prom). */ GT_WRITE(GT_PCI0_CFGADDR_OFS, (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */ (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/ ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/ GT_PCI0_CFGADDR_CONFIGEN_BIT); /* Perform the write */ GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE)); /* Set up resource ranges from the controller's registers. */ start = GT_READ(GT_PCI0M0LD_OFS); end = GT_READ(GT_PCI0M0HD_OFS); map = GT_READ(GT_PCI0M0REMAP_OFS); end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); start1 = GT_READ(GT_PCI0M1LD_OFS); end1 = GT_READ(GT_PCI0M1HD_OFS); map1 = GT_READ(GT_PCI0M1REMAP_OFS); end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK); /* Cannot support multiple windows, use the wider. */ if (end1 - start1 > end - start) { start = start1; end = end1; map = map1; } mask = ~(start ^ end); /* We don't support remapping with a discontiguous mask. */ BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && mask != ~((mask & -mask) - 1)); gt64120_mem_resource.start = start; gt64120_mem_resource.end = end; gt64120_controller.mem_offset = (start & mask) - (map & mask); /* Addresses are 36-bit, so do shifts in the destinations. */ gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF; gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF; gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF; start = GT_READ(GT_PCI0IOLD_OFS); end = GT_READ(GT_PCI0IOHD_OFS); map = GT_READ(GT_PCI0IOREMAP_OFS); end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); mask = ~(start ^ end); /* We don't support remapping with a discontiguous mask. */ BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && mask != ~((mask & -mask) - 1)); gt64120_io_resource.start = map & mask; gt64120_io_resource.end = (map & mask) | ~mask; gt64120_controller.io_offset = 0; /* Addresses are 36-bit, so do shifts in the destinations. */ gt64120_io_resource.start <<= GT_PCI_DCRM_SHF; gt64120_io_resource.end <<= GT_PCI_DCRM_SHF; gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; controller = >64120_controller; break; case MIPS_REVISION_CORID_BONITO64: case MIPS_REVISION_CORID_CORE_20K: case MIPS_REVISION_CORID_CORE_EMUL_BON: /* Set up resource ranges from the controller's registers. */ map = BONITO_PCIMAP; map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >> BONITO_PCIMAP_PCIMAP_LO0_SHIFT; map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >> BONITO_PCIMAP_PCIMAP_LO1_SHIFT; map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >> BONITO_PCIMAP_PCIMAP_LO2_SHIFT; /* Combine as many adjacent windows as possible. */ map = map1; start = BONITO_PCILO0_BASE; end = 1; if (map3 == map2 + 1) { map = map2; start = BONITO_PCILO1_BASE; end++; } if (map2 == map1 + 1) { map = map1; start = BONITO_PCILO0_BASE; end++; } bonito64_mem_resource.start = start; bonito64_mem_resource.end = start + BONITO_PCIMAP_WINBASE(end) - 1; bonito64_controller.mem_offset = start - BONITO_PCIMAP_WINBASE(map); controller = &bonito64_controller; break; case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_EMUL_MSC: /* Set up resource ranges from the controller's registers. */ MSC_READ(MSC01_PCI_SC2PMBASL, start); MSC_READ(MSC01_PCI_SC2PMMSKL, mask); MSC_READ(MSC01_PCI_SC2PMMAPL, map); msc_mem_resource.start = start & mask; msc_mem_resource.end = (start & mask) | ~mask; msc_controller.mem_offset = (start & mask) - (map & mask); MSC_READ(MSC01_PCI_SC2PIOBASL, start); MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); MSC_READ(MSC01_PCI_SC2PIOMAPL, map); msc_io_resource.start = map & mask; msc_io_resource.end = (map & mask) | ~mask; msc_controller.io_offset = 0; ioport_resource.end = ~mask; /* If ranges overlap I/O takes precedence. */ start = start & mask; end = start | ~mask; if ((start >= msc_mem_resource.start && start <= msc_mem_resource.end) || (end >= msc_mem_resource.start && end <= msc_mem_resource.end)) { /* Use the larger space. */ start = max(start, msc_mem_resource.start); end = min(end, msc_mem_resource.end); if (start - msc_mem_resource.start >= msc_mem_resource.end - end) msc_mem_resource.end = start - 1; else msc_mem_resource.start = end + 1; } controller = &msc_controller; break; default: return; } if (controller->io_resource->start < 0x00001000UL) /* FIXME */ controller->io_resource->start = 0x00001000UL; iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ ioport_resource.end = controller->io_resource->end; register_pci_controller (controller); }
void __init mips_pcibios_init(void) { struct pci_controller *controller; resource_size_t start, end, map, start1, end1, map1, map2, map3, mask; switch (mips_revision_sconid) { case MIPS_REVISION_SCON_GT64120: GT_WRITE(GT_PCI0_CFGADDR_OFS, (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | GT_PCI0_CFGADDR_CONFIGEN_BIT); GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE)); start = GT_READ(GT_PCI0M0LD_OFS); end = GT_READ(GT_PCI0M0HD_OFS); map = GT_READ(GT_PCI0M0REMAP_OFS); end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); start1 = GT_READ(GT_PCI0M1LD_OFS); end1 = GT_READ(GT_PCI0M1HD_OFS); map1 = GT_READ(GT_PCI0M1REMAP_OFS); end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK); if (end1 - start1 > end - start) { start = start1; end = end1; map = map1; } mask = ~(start ^ end); BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && mask != ~((mask & -mask) - 1)); gt64120_mem_resource.start = start; gt64120_mem_resource.end = end; gt64120_controller.mem_offset = (start & mask) - (map & mask); gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF; gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF; gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF; start = GT_READ(GT_PCI0IOLD_OFS); end = GT_READ(GT_PCI0IOHD_OFS); map = GT_READ(GT_PCI0IOREMAP_OFS); end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); mask = ~(start ^ end); BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && mask != ~((mask & -mask) - 1)); gt64120_io_resource.start = map & mask; gt64120_io_resource.end = (map & mask) | ~mask; gt64120_controller.io_offset = 0; gt64120_io_resource.start <<= GT_PCI_DCRM_SHF; gt64120_io_resource.end <<= GT_PCI_DCRM_SHF; gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; controller = >64120_controller; break; case MIPS_REVISION_SCON_BONITO: map = BONITO_PCIMAP; map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >> BONITO_PCIMAP_PCIMAP_LO0_SHIFT; map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >> BONITO_PCIMAP_PCIMAP_LO1_SHIFT; map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >> BONITO_PCIMAP_PCIMAP_LO2_SHIFT; map = map1; start = BONITO_PCILO0_BASE; end = 1; if (map3 == map2 + 1) { map = map2; start = BONITO_PCILO1_BASE; end++; } if (map2 == map1 + 1) { map = map1; start = BONITO_PCILO0_BASE; end++; } bonito64_mem_resource.start = start; bonito64_mem_resource.end = start + BONITO_PCIMAP_WINBASE(end) - 1; bonito64_controller.mem_offset = start - BONITO_PCIMAP_WINBASE(map); controller = &bonito64_controller; break; case MIPS_REVISION_SCON_SOCIT: case MIPS_REVISION_SCON_ROCIT: case MIPS_REVISION_SCON_SOCITSC: case MIPS_REVISION_SCON_SOCITSCP: MSC_READ(MSC01_PCI_SC2PMBASL, start); MSC_READ(MSC01_PCI_SC2PMMSKL, mask); MSC_READ(MSC01_PCI_SC2PMMAPL, map); msc_mem_resource.start = start & mask; msc_mem_resource.end = (start & mask) | ~mask; msc_controller.mem_offset = (start & mask) - (map & mask); #ifdef CONFIG_MIPS_CMP if (gcmp_niocu()) gcmp_setregion(0, start, mask, GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); #endif MSC_READ(MSC01_PCI_SC2PIOBASL, start); MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); MSC_READ(MSC01_PCI_SC2PIOMAPL, map); msc_io_resource.start = map & mask; msc_io_resource.end = (map & mask) | ~mask; msc_controller.io_offset = 0; ioport_resource.end = ~mask; #ifdef CONFIG_MIPS_CMP if (gcmp_niocu()) gcmp_setregion(1, start, mask, GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); #endif start = start & mask; end = start | ~mask; if ((start >= msc_mem_resource.start && start <= msc_mem_resource.end) || (end >= msc_mem_resource.start && end <= msc_mem_resource.end)) { start = max(start, msc_mem_resource.start); end = min(end, msc_mem_resource.end); if (start - msc_mem_resource.start >= msc_mem_resource.end - end) msc_mem_resource.end = start - 1; else msc_mem_resource.start = end + 1; } controller = &msc_controller; break; default: return; } if (controller->io_resource->start < 0x00001000UL) controller->io_resource->start = 0x00001000UL; iomem_resource.end &= 0xfffffffffULL; ioport_resource.end = controller->io_resource->end; controller->io_map_base = mips_io_port_base; register_pci_controller(controller); }
void __init mips_pcibios_init(void) { struct pci_controller *controller; resource_size_t start, end, map, start1, end1, map1, map2, map3, mask; switch (mips_revision_sconid) { case MIPS_REVISION_SCON_GT64120: /* * Due to a bug in the Galileo system controller, we need * to setup the PCI BAR for the Galileo internal registers. * This should be done in the bios/bootprom and will be * fixed in a later revision of YAMON (the MIPS boards * boot prom). */ GT_WRITE(GT_PCI0_CFGADDR_OFS, (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */ (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/ ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/ GT_PCI0_CFGADDR_CONFIGEN_BIT); /* Perform the write */ GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE)); /* Set up resource ranges from the controller's registers. */ start = GT_READ(GT_PCI0M0LD_OFS); end = GT_READ(GT_PCI0M0HD_OFS); map = GT_READ(GT_PCI0M0REMAP_OFS); end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); start1 = GT_READ(GT_PCI0M1LD_OFS); end1 = GT_READ(GT_PCI0M1HD_OFS); map1 = GT_READ(GT_PCI0M1REMAP_OFS); end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK); /* Cannot support multiple windows, use the wider. */ if (end1 - start1 > end - start) { start = start1; end = end1; map = map1; } mask = ~(start ^ end); /* We don't support remapping with a discontiguous mask. */ BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && mask != ~((mask & -mask) - 1)); gt64120_mem_resource.start = start; gt64120_mem_resource.end = end; gt64120_controller.mem_offset = (start & mask) - (map & mask); /* Addresses are 36-bit, so do shifts in the destinations. */ gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF; gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF; gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF; start = GT_READ(GT_PCI0IOLD_OFS); end = GT_READ(GT_PCI0IOHD_OFS); map = GT_READ(GT_PCI0IOREMAP_OFS); end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); mask = ~(start ^ end); /* We don't support remapping with a discontiguous mask. */ BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && mask != ~((mask & -mask) - 1)); gt64120_io_resource.start = map & mask; gt64120_io_resource.end = (map & mask) | ~mask; gt64120_controller.io_offset = 0; /* Addresses are 36-bit, so do shifts in the destinations. */ gt64120_io_resource.start <<= GT_PCI_DCRM_SHF; gt64120_io_resource.end <<= GT_PCI_DCRM_SHF; gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; controller = >64120_controller; break; case MIPS_REVISION_SCON_BONITO: /* Set up resource ranges from the controller's registers. */ map = BONITO_PCIMAP; map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >> BONITO_PCIMAP_PCIMAP_LO0_SHIFT; map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >> BONITO_PCIMAP_PCIMAP_LO1_SHIFT; map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >> BONITO_PCIMAP_PCIMAP_LO2_SHIFT; /* Combine as many adjacent windows as possible. */ map = map1; start = BONITO_PCILO0_BASE; end = 1; if (map3 == map2 + 1) { map = map2; start = BONITO_PCILO1_BASE; end++; } if (map2 == map1 + 1) { map = map1; start = BONITO_PCILO0_BASE; end++; } bonito64_mem_resource.start = start; bonito64_mem_resource.end = start + BONITO_PCIMAP_WINBASE(end) - 1; bonito64_controller.mem_offset = start - BONITO_PCIMAP_WINBASE(map); controller = &bonito64_controller; break; case MIPS_REVISION_SCON_SOCIT: case MIPS_REVISION_SCON_ROCIT: case MIPS_REVISION_SCON_SOCITSC: case MIPS_REVISION_SCON_SOCITSCP: /* Set up resource ranges from the controller's registers. */ MSC_READ(MSC01_PCI_SC2PMBASL, start); MSC_READ(MSC01_PCI_SC2PMMSKL, mask); MSC_READ(MSC01_PCI_SC2PMMAPL, map); #if defined(CONFIG_EVA) && !defined(CONFIG_EVA_OLD_MALTA_MAP) /* shift PCI devices to upper 2GB, to prevent PCI bridges loop */ map |= 0xa0000000; MSC_WRITE(MSC01_PCI_SC2PMMAPL, map); MSC_READ(MSC01_PCI_SC2PMMAPL, map); #endif msc_mem_resource.start = start & mask; msc_mem_resource.end = (start & mask) | ~mask; msc_controller.mem_offset = (start & mask) - (map & mask); #ifdef CONFIG_MIPS_CMP if (gcmp_niocu()) gcmp_setregion(0, start, mask, GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); #endif MSC_READ(MSC01_PCI_SC2PIOBASL, start); MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); MSC_READ(MSC01_PCI_SC2PIOMAPL, map); msc_io_resource.start = map & mask; msc_io_resource.end = (map & mask) | ~mask; msc_controller.io_offset = 0; ioport_resource.end = ~mask; #ifdef CONFIG_MIPS_CMP if (gcmp_niocu()) gcmp_setregion(1, start, mask, GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); #endif /* If ranges overlap I/O takes precedence. */ start = start & mask; end = start | ~mask; if ((start >= msc_mem_resource.start && start <= msc_mem_resource.end) || (end >= msc_mem_resource.start && end <= msc_mem_resource.end)) { /* Use the larger space. */ start = max(start, msc_mem_resource.start); end = min(end, msc_mem_resource.end); if (start - msc_mem_resource.start >= msc_mem_resource.end - end) msc_mem_resource.end = start - 1; else msc_mem_resource.start = end + 1; } controller = &msc_controller; break; default: return; } /* Change start address to avoid conflicts with ACPI and SMB devices */ if (controller->io_resource->start < 0x00002000UL) controller->io_resource->start = 0x00002000UL; iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ ioport_resource.end = controller->io_resource->end; controller->io_map_base = mips_io_port_base; register_pci_controller(controller); }
void __init prom_init(void) { mips_display_message("LINUX"); /* * early setup of _pcictrl_bonito so that we can determine * the system controller on a CORE_EMUL board */ _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); mips_revision_corid = MIPS_REVISION_CORID; if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { if (BONITO_PCIDID == 0x0001df53 || BONITO_PCIDID == 0x0003df53) mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; else mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; } mips_revision_sconid = MIPS_REVISION_SCONID; if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { switch (mips_revision_corid) { case MIPS_REVISION_CORID_QED_RM5261: case MIPS_REVISION_CORID_CORE_LV: case MIPS_REVISION_CORID_CORE_FPGA: case MIPS_REVISION_CORID_CORE_FPGAR2: mips_revision_sconid = MIPS_REVISION_SCON_GT64120; break; case MIPS_REVISION_CORID_CORE_EMUL_BON: case MIPS_REVISION_CORID_BONITO64: case MIPS_REVISION_CORID_CORE_20K: mips_revision_sconid = MIPS_REVISION_SCON_BONITO; break; case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_24K: /* * SOCit/ROCit support is essentially identical * but make an attempt to distinguish them */ mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; break; case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_FPGA4: case MIPS_REVISION_CORID_CORE_FPGA5: case MIPS_REVISION_CORID_CORE_EMUL_MSC: default: /* See above */ mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; break; } } switch (mips_revision_sconid) { u32 start, map, mask, data; case MIPS_REVISION_SCON_GT64120: /* * Setup the North bridge to do Master byte-lane swapping * when running in bigendian. */ _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); #ifdef CONFIG_CPU_LITTLE_ENDIAN GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | GT_PCI0_CMD_SBYTESWAP_BIT); #else GT_WRITE(GT_PCI0_CMD_OFS, 0); #endif /* Fix up PCI I/O mapping if necessary (for Atlas). */ start = GT_READ(GT_PCI0IOLD_OFS); map = GT_READ(GT_PCI0IOREMAP_OFS); if ((start & map) != 0) { map &= ~start; GT_WRITE(GT_PCI0IOREMAP_OFS, map); } set_io_port_base(MALTA_GT_PORT_BASE); break; case MIPS_REVISION_SCON_BONITO: _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); /* * Disable Bonito IOBC. */ BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); /* * Setup the North bridge to do Master byte-lane swapping * when running in bigendian. */ #ifdef CONFIG_CPU_LITTLE_ENDIAN BONITO_BONGENCFG = BONITO_BONGENCFG & ~(BONITO_BONGENCFG_MSTRBYTESWAP | BONITO_BONGENCFG_BYTESWAP); #else BONITO_BONGENCFG = BONITO_BONGENCFG | BONITO_BONGENCFG_MSTRBYTESWAP | BONITO_BONGENCFG_BYTESWAP; #endif set_io_port_base(MALTA_BONITO_PORT_BASE); break; case MIPS_REVISION_SCON_SOCIT: case MIPS_REVISION_SCON_ROCIT: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); mips_pci_controller: mb(); MSC_READ(MSC01_PCI_CFG, data); MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); wmb(); /* Fix up lane swapping. */ #ifdef CONFIG_CPU_LITTLE_ENDIAN MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); #else MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); #endif /* Fix up target memory mapping. */ MSC_READ(MSC01_PCI_BAR0, mask); MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); /* Don't handle target retries indefinitely. */ if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == MSC01_PCI_CFG_MAXRTRY_MSK) data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << MSC01_PCI_CFG_MAXRTRY_SHF)) | ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << MSC01_PCI_CFG_MAXRTRY_SHF); wmb(); MSC_WRITE(MSC01_PCI_CFG, data); mb(); set_io_port_base(MALTA_MSC_PORT_BASE); break; case MIPS_REVISION_SCON_SOCITSC: case MIPS_REVISION_SCON_SOCITSCP: _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); goto mips_pci_controller; default: /* Unknown system controller */ mips_display_message("SC Error"); while (1); /* We die here... */ } board_nmi_handler_setup = mips_nmi_setup; board_ejtag_handler_setup = mips_ejtag_setup; fw_init_cmdline(); fw_meminit(); #ifdef CONFIG_SERIAL_8250_CONSOLE console_config(); #endif /* Early detection of CMP support */ if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ)) if (!register_cmp_smp_ops()) return; if (!register_vsmp_smp_ops()) return; #ifdef CONFIG_MIPS_MT_SMTC register_smp_ops(&msmtc_smp_ops); #endif }
void __init prom_init(void) { prom_argc = fw_arg0; _prom_argv = (int *) fw_arg1; _prom_envp = (int *) fw_arg2; mips_display_message("LINUX"); _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); mips_revision_corid = MIPS_REVISION_CORID; if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { if (BONITO_PCIDID == 0x0001df53 || BONITO_PCIDID == 0x0003df53) mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; else mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; } mips_revision_sconid = MIPS_REVISION_SCONID; if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { switch (mips_revision_corid) { case MIPS_REVISION_CORID_QED_RM5261: case MIPS_REVISION_CORID_CORE_LV: case MIPS_REVISION_CORID_CORE_FPGA: case MIPS_REVISION_CORID_CORE_FPGAR2: mips_revision_sconid = MIPS_REVISION_SCON_GT64120; break; case MIPS_REVISION_CORID_CORE_EMUL_BON: case MIPS_REVISION_CORID_BONITO64: case MIPS_REVISION_CORID_CORE_20K: mips_revision_sconid = MIPS_REVISION_SCON_BONITO; break; case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_24K: mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; break; case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_FPGA4: case MIPS_REVISION_CORID_CORE_FPGA5: case MIPS_REVISION_CORID_CORE_EMUL_MSC: default: mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; break; } } switch (mips_revision_sconid) { u32 start, map, mask, data; case MIPS_REVISION_SCON_GT64120: _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); #ifdef CONFIG_CPU_LITTLE_ENDIAN GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | GT_PCI0_CMD_SBYTESWAP_BIT); #else GT_WRITE(GT_PCI0_CMD_OFS, 0); #endif start = GT_READ(GT_PCI0IOLD_OFS); map = GT_READ(GT_PCI0IOREMAP_OFS); if ((start & map) != 0) { map &= ~start; GT_WRITE(GT_PCI0IOREMAP_OFS, map); } set_io_port_base(MALTA_GT_PORT_BASE); break; case MIPS_REVISION_SCON_BONITO: _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); #ifdef CONFIG_CPU_LITTLE_ENDIAN BONITO_BONGENCFG = BONITO_BONGENCFG & ~(BONITO_BONGENCFG_MSTRBYTESWAP | BONITO_BONGENCFG_BYTESWAP); #else BONITO_BONGENCFG = BONITO_BONGENCFG | BONITO_BONGENCFG_MSTRBYTESWAP | BONITO_BONGENCFG_BYTESWAP; #endif set_io_port_base(MALTA_BONITO_PORT_BASE); break; case MIPS_REVISION_SCON_SOCIT: case MIPS_REVISION_SCON_ROCIT: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); mips_pci_controller: mb(); MSC_READ(MSC01_PCI_CFG, data); MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); wmb(); #ifdef CONFIG_CPU_LITTLE_ENDIAN MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); #else MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); #endif MSC_READ(MSC01_PCI_BAR0, mask); MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == MSC01_PCI_CFG_MAXRTRY_MSK) data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << MSC01_PCI_CFG_MAXRTRY_SHF)) | ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << MSC01_PCI_CFG_MAXRTRY_SHF); wmb(); MSC_WRITE(MSC01_PCI_CFG, data); mb(); set_io_port_base(MALTA_MSC_PORT_BASE); break; case MIPS_REVISION_SCON_SOCITSC: case MIPS_REVISION_SCON_SOCITSCP: _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); goto mips_pci_controller; default: mips_display_message("SC Error"); while (1); } board_nmi_handler_setup = mips_nmi_setup; board_ejtag_handler_setup = mips_ejtag_setup; prom_init_cmdline(); prom_meminit(); #ifdef CONFIG_SERIAL_8250_CONSOLE console_config(); #endif if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ)) if (!register_cmp_smp_ops()) return; if (!register_vsmp_smp_ops()) return; #ifdef CONFIG_MIPS_MT_SMTC register_smp_ops(&msmtc_smp_ops); #endif }
void __init prom_init(void) { prom_argc = fw_arg0; _prom_argv = (int *) fw_arg1; _prom_envp = (int *) fw_arg2; #if defined(CONFIG_MIPS_AVALANCHE_PSPBOOT) sys_initenv(); #endif #if !defined(CONFIG_MIPS_AVALANCHE_SOC) mips_display_message("LINUX"); #ifdef CONFIG_MIPS_SEAD set_io_port_base(KSEG1); #else /* * early setup of _pcictrl_bonito so that we can determine * the system controller on a CORE_EMUL board */ _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); mips_revision_corid = MIPS_REVISION_CORID; if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { if (BONITO_PCIDID == 0x0001df53 || BONITO_PCIDID == 0x0003df53) mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; else mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; } switch(mips_revision_corid) { case MIPS_REVISION_CORID_QED_RM5261: case MIPS_REVISION_CORID_CORE_LV: case MIPS_REVISION_CORID_CORE_FPGA: case MIPS_REVISION_CORID_CORE_FPGAR2: /* * Setup the North bridge to do Master byte-lane swapping * when running in bigendian. */ _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); #ifdef CONFIG_CPU_LITTLE_ENDIAN GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | GT_PCI0_CMD_SBYTESWAP_BIT); #else GT_WRITE(GT_PCI0_CMD_OFS, 0); #endif #ifdef CONFIG_MIPS_MALTA set_io_port_base(MALTA_GT_PORT_BASE); #else set_io_port_base((unsigned long)ioremap(0, 0x20000000)); #endif break; case MIPS_REVISION_CORID_CORE_EMUL_BON: case MIPS_REVISION_CORID_BONITO64: case MIPS_REVISION_CORID_CORE_20K: _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); /* * Disable Bonito IOBC. */ BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); /* * Setup the North bridge to do Master byte-lane swapping * when running in bigendian. */ #ifdef CONFIG_CPU_LITTLE_ENDIAN BONITO_BONGENCFG = BONITO_BONGENCFG & ~(BONITO_BONGENCFG_MSTRBYTESWAP | BONITO_BONGENCFG_BYTESWAP); #else BONITO_BONGENCFG = BONITO_BONGENCFG | BONITO_BONGENCFG_MSTRBYTESWAP | BONITO_BONGENCFG_BYTESWAP; #endif #ifdef CONFIG_MIPS_MALTA set_io_port_base(MALTA_BONITO_PORT_BASE); #else set_io_port_base((unsigned long)ioremap(0, 0x20000000)); #endif break; case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_EMUL_MSC: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); #ifdef CONFIG_CPU_LITTLE_ENDIAN MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); #else MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); #endif #ifdef CONFIG_MIPS_MALTA set_io_port_base(MALTA_MSC_PORT_BASE); #else set_io_port_base((unsigned long)ioremap(0, 0x20000000)); #endif break; default: /* Unknown Core card */ mips_display_message("CC Error"); while(1); /* We die here... */ } #endif #endif #if defined(CONFIG_MIPS_AVALANCHE_SOC) set_io_port_base(0); setup_prom_printf(0); #endif /* CONFIG_MIPS_AVALANCHE_SOC */ prom_printf("\nLINUX started...\n"); prom_init_cmdline(); prom_meminit(); #ifdef CONFIG_SERIAL_8250_CONSOLE console_config(); #endif }
/* * Interrupt handler for interrupts coming from the Galileo chip. * It could be built in ethernet ports etc... */ static void gt64240_irq(int irq, void *dev_id, struct pt_regs *regs) { unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask; int handled; #if 0 GT_READ(GT_INTRCAUSE_OFS, &irq_src); GT_READ(GT_INTRMASK_OFS, &irq_src_mask); GT_READ(GT_HINTRCAUSE_OFS, &int_high_src); GT_READ(GT_HINTRMASK_OFS, &int_high_src_mask); #endif irq_src = irq_src & irq_src_mask; int_high_src = int_high_src & int_high_src_mask; handled = 0; /* Execute all interrupt handlers */ /* Check for timer interrupt */ if (irq_src & 0x00000800) { handled = 1; irq_src &= ~0x00000800; // RESET_REG_BITS (INTERRUPT_CAUSE_REGISTER,BIT8); do_timer(regs); } if (irq_src) { printk(KERN_INFO "Other Galileo interrupt received irq_src %x\n", irq_src); #if CURRENTLY_UNUSED for (count = 0; count < MAX_CAUSE_REG_WIDTH; count++) { if (irq_src & (1 << count)) { if (irq_handlers[INT_CAUSE_MAIN][count]. routine) { queue_task(&irq_handlers [INT_CAUSE_MAIN][count], &tq_immediate); mark_bh(IMMEDIATE_BH); handled = 1; } } } #endif /* UNUSED */ } #if 0 GT_WRITE(GT_INTRCAUSE_OFS, 0); GT_WRITE(GT_HINTRCAUSE_OFS, 0); #endif #undef GALILEO_I2O #ifdef GALILEO_I2O /* * Future I2O support. We currently attach I2O interrupt handlers to * the Galileo interrupt (int 4) and handle them in do_IRQ. */ if (isInBoundDoorBellInterruptSet()) { printk(KERN_INFO "I2O doorbell interrupt received.\n"); handled = 1; } if (isInBoundPostQueueInterruptSet()) { printk(KERN_INFO "I2O Queue interrupt received.\n"); handled = 1; } /* * This normally would be outside of the ifdef, but since we're * handling I2O outside of this handler, this printk shows up every * time we get a valid I2O interrupt. So turn this off for now. */ if (handled == 0) { if (counter < 50) { printk("Spurious Galileo interrupt...\n"); counter++; } } #endif }
int __init prom_init(int argc, char **argv, char **envp) { prom_argc = argc; _prom_argv = (int *)argv; _prom_envp = (int *)envp; mips_display_message("LINUX"); #ifdef CONFIG_MIPS_SEAD mips_io_port_base = KSEG1; #else mips_revision_corid = MIPS_REVISION_CORID; switch(mips_revision_corid) { case MIPS_REVISION_CORID_QED_RM5261: case MIPS_REVISION_CORID_CORE_LV: case MIPS_REVISION_CORID_CORE_FPGA: /* * Setup the North bridge to do Master byte-lane swapping * when running in bigendian. */ #if defined(__MIPSEL__) GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | GT_PCI0_CMD_SBYTESWAP_BIT); #else GT_WRITE(GT_PCI0_CMD_OFS, 0); #endif #if defined(CONFIG_MIPS_MALTA) mips_io_port_base = MALTA_GT_PORT_BASE; #else mips_io_port_base = KSEG1; #endif break; case MIPS_REVISION_CORID_BONITO64: case MIPS_REVISION_CORID_CORE_20K: /* * Disable Bonito IOBC. */ BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); /* * Setup the North bridge to do Master byte-lane swapping * when running in bigendian. */ #if defined(__MIPSEL__) BONITO_BONGENCFG = BONITO_BONGENCFG & ~(BONITO_BONGENCFG_MSTRBYTESWAP | BONITO_BONGENCFG_BYTESWAP); #else BONITO_BONGENCFG = BONITO_BONGENCFG | BONITO_BONGENCFG_MSTRBYTESWAP | BONITO_BONGENCFG_BYTESWAP; #endif #if defined(CONFIG_MIPS_MALTA) mips_io_port_base = MALTA_BONITO_PORT_BASE; #else mips_io_port_base = KSEG1; #endif break; case MIPS_REVISION_CORID_CORE_MSC: mips_io_port_base = MALTA_MSC_PORT_BASE; #if defined(__MIPSEL__) MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); #else MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); #endif break; default: /* Unknown Core card */ mips_display_message("CC Error"); while(1); /* We die here... */ } #endif setup_prom_printf(0); prom_printf("\nLINUX started...\n"); prom_init_cmdline(); prom_meminit(); return 0; }